Add tx/rx descriptor initialization
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3104 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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e5e5d8f404
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@ -151,41 +151,127 @@
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#define GPIO_NENET_PINS 10
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/* EMAC DMA RAM and descriptor definitions.
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/* EMAC DMA RAM and descriptor definitions. The configured number of
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* descriptors will determine the organization and the size of the
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* descriptor and status tables. There is a complex interaction between
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* the maximum packet size (CONFIG_NET_BUFSIZE) and the number of
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* Rx and Tx descriptors that can be suppored (CONFIG_ETH_NRXDESC and
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* CONFIG_ETH_NTXDESC): Small buffers -> more packets. This is
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* something that needs to be tuned for you system.
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*
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* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors.
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* For a 16Kb SRAM region, here is the relationship:
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*
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* 16384 <= ntx * (pktsize + 8 + 4) + nrx * (pktsize + 8 + 8)
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*
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* If ntx == nrx and pktsize == 424, then you could have
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* ntx = nrx = 18.
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*
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* An example with all of the details:
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*
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* NTXDESC=18 NRXDESC=18 CONFIG_NET_BUFSIZE=420:
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* LPC17_TXDESCTAB_SIZE = 18*8 = 144
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* LPC17_TXSTATTAB_SIZE = 18*4 = 72
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* LPC17_TXTAB_SIZE = 216
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*
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* LPC17_RXDESCTAB_SIZE = 16*8 = 144
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* LPC17_RXSTATTAB_SIZE = 16*8 = 144
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* LPC17_TXTAB_SIZE = 288
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*
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* LPC17_DESCTAB_SIZE = 504
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* LPC17_DESC_BASE = LPC17_SRAM_BANK0 + 0x00004000 - 504
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* = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_TXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003e98
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* LPC17_RXDESC_BASE = LPC17_SRAM_BANK0 + 0x00003ee0
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* LPC17_RXSTAT_BASE = LPC17_SRAM_BANK0 + 0x00003f70
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*
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* LPC17_PKTMEM_BASE = LPC17_SRAM_BANK0
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* LPC17_PKTMEM_SIZE = 0x00004000-504 = 0x00003e40
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* LPC17_PKTMEM_END = LPC17_SRAM_BANK0 + 0x00003e08
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* LPC17_MAXPACKET_SIZE = ((420 + 3 + 2) & ~3) = 424
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* LPC17_NTXPKTS = 18
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* LPC17_NRXPKTS = 18
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* LPC17_TXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_RXBUFFER_SIZE = 18 * 424 = 0x00001dd0
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* LPC17_BUFFER_SIZE = 0x00003ba0
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* LPC17_BUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_TXBUFFER_BASE = LPC17_SRAM_BANK0
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* LPC17_RXBUFFER_BASE = LPC17_SRAM_BANK0 + 0x00001dd0
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* LPC17_BUFFER_END = LPC17_SRAM_BANK0 + 0x00003ba0
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*
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* Then the check LPC17_BUFFER_END < LPC17_PKTMEM_END passes. The
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* amount of unused memory is small: 0x00003e08-0x00003ba0 or about
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* 616 bytes -- not enough for two more packets.
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*
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* [It is also possible, with some effort, to reclaim any unused
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* SRAM for the use in the heap. But that has not yet been pursued.]
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*/
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#ifndef CONFIG_ETH_NTXDESC
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# define CONFIG_ETH_NTXDESC 18
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#endif
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#define LPC17_TXDESCTAB_SIZE (CONFIG_ETH_NTXDESC*LPC17_TXDESC_SIZE)
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#define LPC17_TXSTATTAB_SIZE (CONFIG_ETH_NTXDESC*LPC17_TXSTAT_SIZE)
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#define LPC17_TXTAB_SIZE (LPC17_TXDESCTAB_SIZE+LPC17_TXSTATTAB_SIZE)
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#ifndef CONFIG_ETH_NRXDESC
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# define CONFIG_ETH_NRXDESC 18
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#endif
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#define LPC17_RXDESCTAB_SIZE (CONFIG_ETH_NRXDESC*LPC17_RXDESC_SIZE)
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#define LPC17_RXSTATTAB_SIZE (CONFIG_ETH_NRXDESC*LPC17_RXSTAT_SIZE)
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#define LPC17_RXTAB_SIZE (LPC17_RXDESCTAB_SIZE+LPC17_RXSTATTAB_SIZE)
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#define LPC17_DESCTAB_SIZE (LPC17_TXTAB_SIZE+LPC17_RXTAB_SIZE)
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/* All of AHB SRAM, Bank 0 is set aside for EMAC Tx and Rx descriptors. */
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#define LPC17_BANK0_SIZE 0x00004000
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#define LPC17_EMACRAM_BASE LPC17_SRAM_BANK0
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#define LPC17_EMACRAM_SIZE LPC17_BANK0_SIZE
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#warning "Need to exclude bank0 from the heap"
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/* Numbers of descriptors and sizes of descriptor and status regions */
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#ifdef CONFIG_ETH_NTXDESC
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# define CONFIG_ETH_NTXDESC 16
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#endif
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#define LPC17_TXDESC_SIZE (8*CONFIG_ETH_NTXDESC)
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#define LPC17_TXSTAT_SIZE (4*CONFIG_ETH_NTXDESC)
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#ifdef CONFIG_ETH_NRXDESC
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# define CONFIG_ETH_NRXDESC 16
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#endif
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#define LPC17_RXDESC_SIZE (8*CONFIG_ETH_NRXDESC)
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#define LPC17_RXSTAT_SIZE (8*CONFIG_ETH_NRXDESC)
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/* Descriptor Memory Organization. Descriptors are packed
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* at the end of AHB SRAM, Bank 0.
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/* Descriptor table memory organization. Descriptor tables are packed at
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* the end of AHB SRAM, Bank 0. The beginning of bank 0 is reserved for
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* packet memory.
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*/
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#define LPC17_DESC_SIZE (LPC17_TXDESC_SIZE+LPC17_RXDESC_SIZE+LPC17_TXSTAT_SIZE+LPC17_RXSTAT_SIZE)
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#define LPC17_DESC_BASE (LPC17_SRAM_BANK0+LPC17_BANK0_SIZE-LPC17_DESC_SIZE)
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#define LPC17_DESC_BASE (LPC17_EMACRAM_BASE+LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_TXDESC_BASE LPC17_DESC_BASE
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#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESC_SIZE)
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#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTAT_SIZE)
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#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESC_SIZE)
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#define LPC17_TXSTAT_BASE (LPC17_TXDESC_BASE+LPC17_TXDESCTAB_SIZE)
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#define LPC17_RXDESC_BASE (LPC17_TXSTAT_BASE+LPC17_TXSTATTAB_SIZE)
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#define LPC17_RXSTAT_BASE (LPC17_RXDESC_BASE + LPC17_RXDESCTAB_SIZE)
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/* Register debug */
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/* Now carve up the beginning of SRAM for packet memory. The size of a
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* packet buffer is related to the size of the MTU. We'll round sizes up
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* to multiples of 256 bytes.
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*/
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#define LPC17_PKTMEM_BASE LPC17_EMACRAM_BASE
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#define LPC17_PKTMEM_SIZE (LPC17_EMACRAM_SIZE-LPC17_DESCTAB_SIZE)
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#define LPC17_PKTMEM_END (LPC17_EMACRAM_BASE+LPC17_PKTMEM_SIZE)
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#define LPC17_MAXPACKET_SIZE ((CONFIG_NET_BUFSIZE + 3 + 2) & ~3)
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#define LPC17_NTXPKTS CONFIG_ETH_NTXDESC
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#define LPC17_NRXPKTS CONFIG_ETH_NRXDESC
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#define LPC17_TXBUFFER_SIZE (LPC17_NTXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_RXBUFFER_SIZE (LPC17_NRXPKTS * LPC17_MAXPACKET_SIZE)
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#define LPC17_BUFFER_SIZE (LPC17_TXBUFFER_SIZE + LPC17_RXBUFFER_SIZE)
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#define LPC17_BUFFER_BASE LPC17_PKTMEM_BASE
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#define LPC17_TXBUFFER_BASE LPC17_BUFFER_BASE
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#define LPC17_RXBUFFER_BASE (LPC17_TXBUFFER_BASE + LPC17_TXBUFFER_SIZE)
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#define LPC17_BUFFER_END (LPC17_BUFFER_BASE + LPC17_BUFFER_SIZE)
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#if LPC17_BUFFER_END > LPC17_PKTMEM_END
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# error "Packet memory overlaps descriptor tables"
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#endif
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/* Register debug -- can only happen of CONFIG_DEBUG is selected */
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#ifndef CONFIG_DEBUG
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# undef CONFIG_LPC17_ENET_REGDEBUG
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@ -318,6 +404,8 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv);
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/* EMAC Initialization functions */
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static inline void lpc17_txdescinit(struct lpc17_driver_s *priv);
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static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv);
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static void lpc17_macmode(uint8_t mode);
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static void lpc17_ethreset(struct lpc17_driver_s *priv);
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@ -794,7 +882,10 @@ static int lpc17_ifup(struct uip_driver_s *dev)
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lpc17_macmode(priv->lp_mode);
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/* Initialize EMAC DMA memory */
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/* Initialize EMAC DMA memory -- descriptors, status, packet buffers, etc. */
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lpc17_txdescinit(priv);
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lpc17_rxdescinit(priv);
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/* Set up RX filter and configure to accept broadcast address and perfect
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* station address matches.
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@ -1255,9 +1346,8 @@ static int lpc17_phymode(uint8_t phyaddr, uint8_t mode)
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* priv - Pointer to EMAC device driver structure
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*
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* Returned Value:
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* None directory.
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* As a side-effect, it will initialize priv->lp_phyaddr and
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* priv->lp_phymode.
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* None directly. As a side-effect, it will initialize priv->lp_phyaddr
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* and priv->lp_phymode.
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*
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* Assumptions:
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*
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@ -1412,8 +1502,127 @@ static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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lpc17_showmii(phyaddr, "After final configuration");
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return ret;
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}
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#else
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static inline int lpc17_phyinit(struct lpc17_driver_s *priv)
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{
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priv->lp_mode = LPC17_MODE_DEFLT;
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return OK;
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}
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#endif
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/****************************************************************************
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* Function: lpc17_txdescinit
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*
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* Description:
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* Initialize the EMAC Tx descriptor table
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*
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* Parameters:
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* priv - Pointer to EMAC device driver structure
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*
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* Returned Value:
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* None directory.
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* As a side-effect, it will initialize priv->lp_phyaddr and
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* priv->lp_phymode.
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*
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* Assumptions:
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*
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****************************************************************************/
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static inline void lpc17_txdescinit(struct lpc17_driver_s *priv)
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{
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uint32_t *txdesc;
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uint32_t *txstat;
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uint32_t pktaddr;
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int i;
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/* Configure Tx descriptor and status tables */
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lpc17_putreg(LPC17_TXDESC_BASE, LPC17_ETH_TXDESC);
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lpc17_putreg(LPC17_TXSTAT_BASE, LPC17_ETH_TXSTAT);
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lpc17_putreg(CONFIG_ETH_NTXDESC-1, LPC17_ETH_TXDESCRNO);
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/* Initialize Tx descriptors and link to packet buffers */
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txdesc = (uint32_t*)LPC17_TXDESC_BASE;
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pktaddr = LPC17_TXBUFFER_BASE;
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for (i = 0; i < CONFIG_ETH_NTXDESC; i++)
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{
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*txdesc++ = pktaddr;
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*txdesc++ = (TXDESC_CONTROL_INT | (LPC17_MAXPACKET_SIZE - 1));
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pktaddr += LPC17_MAXPACKET_SIZE;
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}
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/* Initialize Tx status */
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txstat = (uint32_t*)LPC17_TXSTAT_BASE;
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for (i = 0; i < CONFIG_ETH_NTXDESC; i++)
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{
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*txstat++ = 0;
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}
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/* Point to first Tx descriptor */
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lpc17_putreg(0, LPC17_ETH_TXPRODIDX);
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}
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/****************************************************************************
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* Function: lpc17_rxdescinit
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*
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* Description:
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* Initialize the EMAC Rx descriptor table
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*
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* Parameters:
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* priv - Pointer to EMAC device driver structure
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*
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* Returned Value:
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* None directory.
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* As a side-effect, it will initialize priv->lp_phyaddr and
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* priv->lp_phymode.
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*
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* Assumptions:
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*
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****************************************************************************/
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static inline void lpc17_rxdescinit(struct lpc17_driver_s *priv)
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{
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uint32_t *rxdesc;
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uint32_t *rxstat;
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uint32_t pktaddr;
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int i;
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/* Configure Rx descriptor and status tables */
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lpc17_putreg(LPC17_RXDESC_BASE, LPC17_ETH_RXDESC);
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lpc17_putreg(LPC17_RXSTAT_BASE, LPC17_ETH_RXSTAT);
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lpc17_putreg(CONFIG_ETH_NRXDESC-1, LPC17_ETH_RXDESCNO);
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/* Initialize Rx descriptors and link to packet buffers */
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rxdesc = (uint32_t*)LPC17_RXDESC_BASE;
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pktaddr = LPC17_RXBUFFER_BASE;
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for (i = 0; i < CONFIG_ETH_NRXDESC; i++)
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{
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*rxdesc++ = pktaddr;
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*rxdesc++ = (RXDESC_CONTROL_INT | (LPC17_MAXPACKET_SIZE - 1));
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pktaddr += LPC17_MAXPACKET_SIZE;
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}
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/* Initialize Rx status */
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rxstat = (uint32_t*)LPC17_TXSTAT_BASE;
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for (i = 0; i < CONFIG_ETH_NRXDESC; i++)
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{
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*rxstat++ = 0;
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*rxstat++ = 0;
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}
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/* Point to first Tx descriptor */
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lpc17_putreg(0, LPC17_ETH_RXPRODIDX);
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}
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/****************************************************************************
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* Function: lpc17_macmode
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*
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@ -501,6 +501,87 @@
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/* Bits 0-30: Reserved */
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#define ETH_PWRDOWN_MACAHB (1 << 31) /* Power down MAC/AHB */
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/* Descriptors Offsets **************************************************************/
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/* Tx descriptor offsets */
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#define LPC17_TXDESC_PACKET 0x00 /* Base address of the Tx data buffer */
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#define LPC17_TXDESC_CONTROL 0x04 /* Control Information */
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#define LPC17_TXDESC_SIZE 0x08 /* Size in bytes of one Tx descriptor */
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/* Tx status offsets */
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#define LPC17_TXSTAT_INFO 0x00 /* Transmit status return flags */
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#define LPC17_TXSTAT_SIZE 0x04 /* Size in bytes of one Tx status */
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/* Rx descriptor offsets */
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#define LPC17_RXDESC_PACKET 0x00 /* Base address of the Rx data buffer */
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#define LPC17_RXDESC_CONTROL 0x04 /* Control Information */
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#define LPC17_RXDESC_SIZE 0x08 /* Size in bytes of one Rx descriptor */
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/* Rx status offsets */
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#define LPC17_RXSTAT_INFO 0x00 /* Receive status return flags */
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#define LPC17_RXSTAT_HASHCRC 0x04 /* Dest and source hash CRC */
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#define LPC17_RXSTAT_SIZE 0x08 /* Size in bytes of one Rx status */
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/* Descriptor Bit Definitions *******************************************************/
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/* Tx descriptor bit definitions */
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#define TXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */
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#define TXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT)
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#define TXDESC_CONTROL_OVERRIDE (1 << 26 /* Bit 26: Per-frame override */
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#define TXDESC_CONTROL_HUGE (1 << 27) /* Bit 27: Enable huge frame size */
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#define TXDESC_CONTROL_PAD (1 << 28) /* Bit 28: Pad short frames */
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#define TXDESC_CONTROL_CRC (1 << 29) /* Bit 29: Append CRC */
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#define TXDESC_CONTROL_LAST (1 << 30) /* Bit 30: Last descriptor of a fragment */
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#define TXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate TxDone interrupt */
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/* Tx statis bit definitions */
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#define TXSTAT_INFO_COLCNT_SHIFT (21) /* Bits 21-24: Number of collisions */
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#define TXSTAT_INFO_COLCNT_MASK (15 << TXSTAT_INFO_COLCNT_SHIFT)
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#define TXSTAT_INFO_DEFER (1 << 25) /* Bit 25: Packet deffered */
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#define TXSTAT_INFO_EXCESSDEFER (1 << 26) /* Bit 26: Excessive packet defferals */
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#define TXSTAT_INFO_EXCESSCOL (1 << 27) /* Bit 27: Excessive packet collisions */
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#define TXSTAT_INFO_LATECOL (1 << 28) /* Bit 28: Out of window collision */
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#define TXSTAT_INFO_UNDERRUN (1 << 29) /* Bit 29: Tx underrun */
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#define TXSTAT_INFO_NODESC (1 << 30) /* Bit 29: No Tx descriptor available */
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#define TXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */
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/* Rx descriptor bit definitions */
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#define RXDESC_CONTROL_SIZE_SHIFT (0) /* Bits 0-10: Size of data buffer */
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#define RXDESC_CONTROL_SIZE_MASK (0x7ff << RXDESC_CONTROL_SIZE_SHIFT)
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#define RXDESC_CONTROL_INT (1 << 31) /* Bit 31: Generate RxDone interrupt */
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/* Rx status bit definitions */
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#define RXSTAT_SAHASHCRC_SHIFT (0) /* Bits 0-8: Hash CRC calculated from the source address */
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#define RXSTAT_SAHASHCRC_MASK (0x1ff << RXSTAT_SAHASHCRC_SHIFT)
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#define RXSTAT_DAHASHCRC_SHIFT (16) /* Bits 16-24: Hash CRC calculated from the dest address */
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#define RXSTAT_DAHASHCRC_MASK (0x1ff << RXSTAT_DAHASHCRC_SHIFT)
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#define RXSTAT_INFO_RXSIZE_SHIFT (0) /* Bits 0-10: Size of actual data transferred */
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#define RXSTAT_INFO_RXSIZE_MASK (0x7ff << RXSTAT_INFO_RXSIZE_SHIFT)
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#define RXSTAT_INFO_CONTROL (1 << 18) /* Bit 18: This is a control frame */
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#define RXSTAT_INFO_VLAN (1 << 19) /* Bit 19: This is a VLAN frame */
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#define RXSTAT_INFO_FAILFILTER (1 << 20) /* Bit 20: Frame failed Rx filter */
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#define RXSTAT_INFO_MULTICAST (1 << 21) /* Bit 21: This is a multicast frame */
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#define RXSTAT_INFO_BROADCAST (1 << 22) /* Bit 22: This is a broadcast frame */
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#define RXSTAT_INFO_CRCERROR (1 << 23) /* Bit 23: Received frame had a CRC error */
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#define RXSTAT_INFO_SYMBOLERROR (1 << 24) /* Bit 24: PHY reported bit error */
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#define RXSTAT_INFO_LENGTHERROR (1 << 25) /* Bit 25: Invalid frame length */
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#define RXSTAT_INFO_RANGEERROR (1 << 26) /* Bit 26: Exceeds maximum packet size */
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#define RXSTAT_INFO_ALIGNERROR (1 << 27) /* Bit 27: Alignment error */
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||||
#define RXSTAT_INFO_OVERRUN (1 << 28) /* Bit 28: Receive overrun error */
|
||||
#define RXSTAT_INFO_NODESC (1 << 29) /* Bit 29: No Rx descriptor available */
|
||||
#define RXSTAT_INFO_LASTFLAG (1 << 30) /* Bit 30: Last fragment of a frame */
|
||||
#define RXSTAT_INFO_ERROR (1 << 31) /* Bit 31: OR of other error conditions */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user