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LPC43xx: Fix some NVIC priority definitions

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Lok Tep 2016-01-25 07:23:28 -06:00 committed by Gregory Nutt
parent fb3baae5a4
commit 1f4ce9e7f9
3 changed files with 4 additions and 4 deletions
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4
arch/arm/include/lpc43xx/chip.h
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@ -648,12 +648,12 @@
#define LPC43M4_SYSH_PRIORITY_MIN 0xe0 /* All bits[7:5] set is minimum priority */
#define LPC43M4_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define LPC43M4_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define LPC43M4_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
#define LPC43M4_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
#define LPC43M0_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define LPC43M0_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define LPC43M0_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define LPC43M0_SYSH_PRIORITY_STEP 0x20 /* Steps between priorities */
#define LPC43M0_SYSH_PRIORITY_STEP 0x40 /* Steps between priorities */
/* Only the Cortex-M4 is supported by Nuttx */

2
arch/arm/include/nuc1xx/chip.h
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@ -641,7 +641,7 @@
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */

2
arch/arm/include/samdl/chip.h
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@ -973,7 +973,7 @@
* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:3] set is minimum priority */
#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Five bits of interrupt priority used */