After cached related fix, the ELF example is now functional
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@ -130,6 +130,10 @@ config ARCH_L2CACHE
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bool
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default n
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config ARCH_HAVE_COHERENT_DCACHE
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bool
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default n
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config CUSTOM_STACK
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bool
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default n
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@ -212,12 +212,14 @@ config ARCH_CORTEXA5
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_MMU
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select ARCH_HAVE_COHERENT_DCACHE if ELF
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config ARCH_CORTEXA8
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bool
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default n
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_MMU
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select ARCH_HAVE_COHERENT_DCACHE if ELF
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config ARCH_FAMILY
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string
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@ -87,7 +87,7 @@ CMN_CSRCS += arm_addrenv.c
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endif
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ifeq ($(CONFIG_ELF),y)
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CMN_CSRCS += arm_elf.c
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CMN_CSRCS += arm_elf.c arch_coherent_dcache.c
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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@ -9,7 +9,8 @@ config ARMV7A_HAVE_L2CC
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bool
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default n
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---help---
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Selected by the configuration tool if the architecutre supports any kind of L2 cache.
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Selected by the configuration tool if the architecutre supports any
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kind of L2 cache.
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config ARMV7A_HAVE_L2CC_PL310
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bool
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94
arch/arm/src/armv7-a/arch_coherent_dcache.c
Normal file
94
arch/arm/src/armv7-a/arch_coherent_dcache.c
Normal file
@ -0,0 +1,94 @@
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/****************************************************************************
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* arch/arm/src/armv7/arch_undefinedinsn.c
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include "cp15_cacheops.h"
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#include <nuttx/binfmt/elf.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: arch_coherent_dcache
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*
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* Description:
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* Ensure that the I and D caches are coherent within specified region
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* by cleaning the D cache (i.e., flushing the D cache contents to memory
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* and invalidating the I cache. This is typically used when code has been
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* written to a memory region, and will be executed.
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*
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* Input Parameters:
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* addr - virtual start address of region
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* len - Size of the address region in bytes
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void arch_coherent_dcache(uintptr_t addr, size_t len)
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{
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/* Perform the operation on the L1 cache */
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cp15_coherent_dcache(addr, addr+len);
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#ifdef CONFIG_ARCH_L2CACHE
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/* If we have an L2 cache, then there more things that need to done */
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# warning This is insufficient
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#endif
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}
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@ -89,7 +89,7 @@ CMN_CSRCS += arm_addrenv.c
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endif
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ifeq ($(CONFIG_ELF),y)
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CMN_CSRCS += arm_elf.c
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CMN_CSRCS += arm_elf.c arch_coherent_dcache.c
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endif
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ifeq ($(CONFIG_ARCH_FPU),y)
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