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arch: arm: kinetis: fix nxstyle errors

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fix nxstyle errors to pass CI

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-22 17:19:33 +01:00 committed by Xiang Xiao
parent b6a987afe0
commit 1fdae80321
17 changed files with 453 additions and 317 deletions
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41
arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
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@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k20pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,31 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Reference: Paragraph 10.3.1, p 207, of FreeScale document K20P64M72SF1RM
****************************************************************************/
/* Reference:
* Paragraph 10.3.1, p 207, of FreeScale document K20P64M72SF1RM
*
* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labelled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labelled with a suffix like _1, _2, etc.
* in order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin configuration
* (with no suffix) that maps to the correct alternative.
*/
#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
@ -317,21 +320,21 @@
# define PIN_XTAL0 (PIN_ALT0 | PIN_PORTA | PIN19)
#else
/* The pin muxing for other K20 parts is defined in other documents */
/* The pin muxing for other K20 parts is defined in other documents */
# error "No pin multiplexing for this Kinetis K20 part"
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K20PINMUX_H */

39
arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
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@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k28k64k66mpu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */
@ -124,7 +124,7 @@
#define KINETIS_MPU_RGDAAC10_OFFSET 0x0828 /* Region Descriptor Alternate Access Control 10 */
#define KINETIS_MPU_RGDAAC11_OFFSET 0x082c /* Region Descriptor Alternate Access Control 11 */
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET)
@ -215,7 +215,7 @@
#define KINETIS_MPU_RGDAAC10 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC10_OFFSET)
#define KINETIS_MPU_RGDAAC11 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC11_OFFSET)
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Control/Error Status Register */
@ -226,6 +226,7 @@
# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */
# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */
# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */
#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */
#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT)
#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */
@ -234,6 +235,7 @@
#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */
#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT)
# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */
# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */
# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */
# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */
@ -251,6 +253,7 @@
# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */
# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */
# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */
#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */
#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT)
#if defined(KINETIS_K28)
@ -261,11 +264,13 @@
#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT)
/* Region Descriptor n, Word 0 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */
#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0)
/* Region Descriptor n, Word 1 */
/* Bits 0-4: Reserved */
#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */
#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0)
@ -285,7 +290,7 @@
#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT)
#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */
#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT)
#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */
#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */
#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */
#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT)
#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */
@ -360,16 +365,16 @@
#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */
#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K64K66MPU_H */

49
arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
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@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k28k66fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */
#define KINETIS_FMC_PFB01CR_OFFSET 0x0004 /* Flash Bank 0-1 Control Register */
@ -63,7 +63,9 @@
#define KINETIS_FMC_TAGVDW3S2_OFFSET 0x0138 /* Cache Directory Storage */
#define KINETIS_FMC_TAGVDW3S3_OFFSET 0x013c /* Cache Directory Storage */
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for way=w and set=s, w=0..3, s=0..7 */
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for
* way=w and set=s, w=0..3, s=0..7
*/
#define KINETIS_FMC_DATAUM_OFFSET(w,s) (0x200 + ((w) << 6) + ((s) << 2))
#define KINETIS_FMC_DATAMU_OFFSET(w,s) (0x204 + ((w) << 6) + ((s) << 2))
@ -138,7 +140,7 @@
#define KINETIS_FMC_DATAW3S3ML_OFFSET 0x02f8 /* Cache Data Storage (mid-lower word) */
#define KINETIS_FMC_DATAW3S3LM_OFFSET 0x02fc /* Cache Data Storage (lowermost word) */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET)
#define KINETIS_FMC_PFB01CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB01CR_OFFSET)
@ -168,7 +170,9 @@
#define KINETIS_FMC_TAGVDW3S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S2_OFFSET)
#define KINETIS_FMC_TAGVDW3S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S3_OFFSET)
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for way=w and set=s, w=0..3, s=0..7 */
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for
* way=w and set=s, w=0..3, s=0..7
*/
#define KINETIS_FMC_DATAUM(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAUM_OFFSET(w,s))
#define KINETIS_FMC_DATAMU(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAMU_OFFSET(w,s))
@ -243,9 +247,10 @@
#define KINETIS_FMC_DATAW3S3ML (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3ML_OFFSET)
#define KINETIS_FMC_DATAW3S3LM (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3LM_OFFSET)
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* Flash Access Protection Register */
/* Access protection bits (all masters) */
#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */
@ -278,6 +283,7 @@
#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */
#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */
/* Bits 24-31: Reserved */
/* Flash Bank 0-1 Control Register */
#define FMC_PFB01CR_RFU (1 << 0) /* Bit 0: Reserved for future use */
@ -290,12 +296,14 @@
# define FMC_PFB01CR_CRC_ALL (0 << FMC_PFB01CR_CRC_SHIFT) /* LRU all four ways */
# define FMC_PFB01CR_CRC_I01D23 (2 << FMC_PFB01CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */
# define FMC_PFB01CR_CRC_I012D3 (3 << FMC_PFB01CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */
/* Bits 8-16: Reserved */
#define FMC_PFB01CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */
#define FMC_PFB01CR_B0MW_MASK (3 << FMC_PFB01CR_B0MW_SHIFT)
# define FMC_PFB01CR_B0MW_32BITS (0 << FMC_PFB01CR_B0MW_SHIFT) /* 32 bits */
# define FMC_PFB01CR_B0MW_64BITS (1 << FMC_PFB01CR_B0MW_SHIFT) /* 64 bits */
# define FMC_PFB01CR_B0MW_128BITS (2 << FMC_PFB01CR_B0MW_SHIFT) /* 128 bits */
#define FMC_PFB01CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */
#define FMC_PFB01CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */
#define FMC_PFB01CR_CINV_WAY_MASK (15 << FMC_PFB01CR_CINV_WAY_SHIFT)
@ -317,6 +325,7 @@
# define FMC_PFB23CR_B1MW_32BITS (0 << FMC_PFB23CR_B1MW_SHIFT) /* 32 bits */
# define FMC_PFB23CR_B1MW_64BITS (1 << FMC_PFB23CR_B1MW_SHIFT) /* 64 bits */
# define FMC_PFB23CR_B1MW_128BITS (2 << FMC_PFB23CR_B1MW_SHIFT) /* 128 bits */
/* Bits 19-27: Reserved */
#define FMC_PFB23CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */
#define FMC_PFB23CR_B1RWSC_MASK (15 << FMC_PFB23CR_B0RWSC_SHIFT)
@ -329,20 +338,20 @@
#define FMC_TAGVD_TAG_MASK (0xffff << FMC_TAGVD_TAG_SHIFT)
/* Bits 19-31: Reserved */
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for way=w and set=s,
* w=0..3, s=0..7 128-bit data in four 32-bit registers.
/* Cache Data Storage (UpperMost, MidUpper, MidLower LowerMost) for
* way=w and set=s, w=0..3, s=0..7 128-bit data in four 32-bit registers.
*/
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K28K66FMC_H */

38
arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k40pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,30 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Reference: Paragraph 10.3.1, p 227, of FreeScale document K40P144M100SF2RM
*
* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labeled with a suffix like _1, _2, etc. in
* order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin configuration
* (with no suffix) that maps to the correct alternative.
*/
#if defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
@ -483,21 +485,21 @@
#define PIN_FB_AD20 (PIN_ALT5 | PIN_PORTE | PIN28)
#else
/* The pin muxing for other K40 parts is defined in other documents */
/* The pin muxing for other K40 parts is defined in other documents */
# error "No pin multiplexing for this Kinetis K40 part"
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K40PINMUX_H */

38
arch/arm/src/kinetis/hardware/kinetis_k60pinmux.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k60pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,28 +16,30 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
****************************************************************************/
/* Reference: Paragraph 10.3.1, p 258, of FreeScale document K60P144M100SF2RM
*
* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labeled with a suffix like _1, _2, etc. in
* order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin configuration
* (with no suffix) that maps to the correct alternative.
*/
#if defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
@ -451,21 +453,21 @@
#define PIN_UART4_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN27)
#else
/* The pin muxing for other K60 parts is defined in other documents */
/* The pin muxing for other K60 parts is defined in other documents */
# error "No pin multiplexing for this Kinetis K60 part"
#endif
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K60PINMUX_H */

44
arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k64pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -31,18 +31,20 @@
#ifdef KINETIS_K64
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
****************************************************************************/
/* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labeled with a suffix like _1, _2, etc. in
* order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin configuration
* (with no suffix) that maps to the correct alternative.
*
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in the initial version of this file.
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in the initial version of this file.
*/
/* ADC */
@ -609,17 +611,17 @@
#define PIN_EXTAL0 (PIN_ANALOG | PIN_PORTA | PIN18)
#define PIN_XTAL0 (PIN_ANALOG | PIN_PORTA | PIN19)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K64 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K64PINMUX_H */

48
arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k66memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -31,11 +31,12 @@
#ifdef KINETIS_K66
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Memory Map ***************************************************************/
/* Memory Map ***********************************************************************/
/* K66 Family
*
* The memory map for the following parts is defined in NXP document
@ -69,8 +70,10 @@
* (ICODE/DCODE) */
# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband
* region */
/* 0x20100000 * -0x21ffffff Reserved */
# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */
/* 0x24000000 * -0x2fffffff Reserved */
# define KINETIS_FDATALIAS_BASE 0x30000000 /* -0x33ffffff Flash Data Alias */
# define KINETIS_FLEXNVMCO_BASE 0x34000000 /* -0x3fffffff FlexNVM Cortex-M4 core only */
@ -80,10 +83,12 @@
* bridge 1 (AIPS-Lite1) */
# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general
* purpose input/output (GPIO) */
/* 0x40100000 * -0x41ffffff Reserved */
# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge
* (AIPS-Lite) and general purpose
* input/output (GPIO) bitband */
/* 0x44000000 * -0x5fffffff Reserved */
# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - Write-back) */
# define KINETIS_SDRAMWB_BASE 0x70000000 /* -0x7fffffff SDRAM (External RAM - Write-back) */
@ -91,9 +96,10 @@
# define KINETIS_FLEXBUSWT_BASE 0x90000000 /* -0x9fffffff FlexBus (External RAM - Write-through) */
# define KINETIS_FLEXBUSEP_BASE 0xa0000000 /* -0xdfffffff FlexBus External Peripheral - Not executable)*/
# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */
/* 0xe0100000 * -0xffffffff Reserved */
/* Peripheral Bridge 0 Memory Map ***************************************************/
/* Peripheral Bridge 0 Memory Map *******************************************/
# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */
# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */
@ -151,7 +157,7 @@
# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */
# define KINETIS_RCM_BASE 0x4007f000 /* Reset Control Module (RCM) */
/* Peripheral Bridge 1 Memory Map ***************************************************/
/* Peripheral Bridge 1 Memory Map *******************************************/
# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */
# define KINETIS_RNGA_ALT_BASE 0x400a0000 /* Alternate address Random number generator (RNGA) */
@ -184,7 +190,7 @@
# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
/* Private Peripheral Bus (PPB) Memory Map **********************************/
# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */
# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */
@ -200,26 +206,26 @@
# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */
#else
/* The memory map for other parts is defined in other documents and may or may not
* be the same as above (the family members are all very similar) This error just
* means that you have to look at the document and determine for yourself if the
* memory map is the same.
/* The memory map for other parts is defined in other documents and may or
* may not be the same as above (the family members are all very similar)
* This error just means that you have to look at the document and
* determine for yourself if the memory map is the same.
*/
# error "No memory map for this K66 part"
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K66 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66MEMORYMAP_H */

44
arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
View File

@ -1,4 +1,4 @@
/********************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_k66pinmux.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
********************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H
/********************************************************************************************
/****************************************************************************
* Included Files
********************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
@ -31,18 +31,20 @@
#ifdef KINETIS_K66
/********************************************************************************************
/****************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* In most cases, there are alternative configurations for various pins. Those alternative
* pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in
* the board.h file must select the correct pin configuration for the board by defining a pin
* configuration (with no suffix) that maps to the correct alternative.
****************************************************************************/
/* In most cases, there are alternative configurations for various pins.
* Those alternative pins are labeled with a suffix like _1, _2, etc. in
* order to distinguish them. Logic in the board.h file must select the
* correct pin configuration for the board by defining a pin configuration
* (with no suffix) that maps to the correct alternative.
*
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as frequency,
* open-drain/push-pull, and pull-up/down! Just the basics are defined for most
* pins in the initial version of this file.
* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
* Additional effort is required to select specific GPIO options such as
* frequency, open-drain/push-pull, and pull-up/down! Just the basics are
* defined for most pins in the initial version of this file.
*/
/* ADC */
@ -730,17 +732,17 @@
#define PIN_EXTAL0 (PIN_ANALOG | PIN_PORTA | PIN18)
#define PIN_XTAL0 (PIN_ANALOG | PIN_PORTA | PIN19)
/********************************************************************************************
/****************************************************************************
* Public Types
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
/****************************************************************************
* Public Data
********************************************************************************************/
****************************************************************************/
/********************************************************************************************
* Public Functions
********************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* KINETIS_K66 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_K66PINMUX_H */

12
arch/arm/src/kinetis/hardware/kinetis_kx6tpm.h
View File

@ -103,15 +103,19 @@
/* Bits 9-31: Reserved */
#define TPM_CNT_SHIFT 0 /* Bits 0-15: Counter value */
#define TPM_CNT_MASK (0xffff << TPM_COUNT_SHIFT) /* Any write clears Count */
/* Bits 16-31: Reserved */
#define TPM_MOD_SHIFT 0 /* Bits 0-15: Mod value */
#define TPM_MOD_MASK (0xffff << TPM_MOD_SHIFT) /* This field must be written with single 16 or 32-bit access */
/* Bits 16-31: Reserved */
#define TPM_CnSC_DMA (1 << 0) /* Bit 0: Enables DMA transfers for the channel */
/* Bit 1: Reserved*/
/* Bit 1: Reserved */
#define TPM_CnSC_ELSA (1 << 2) /* Bit 2: Edge or Level Select */
#define TPM_CnSC_ELSB (1 << 3) /* Bit 3: Edge or Level Select */
#define TPM_CnSC_MSA (1 << 4) /* Bit 4: Channel Mode Select */
@ -121,9 +125,11 @@
/* Bits 8-31: Reserved */
#define TPM_VAL_SHIFT 0 /* Bits 0-15: Channel value */
#define TPM_VAL_MASK (0xffff << TPM_VAL_SHIFT) /* Captured TPM counter value of the input modes or
* the match value for the output modes. This field
* must be written with single 16 or 32-bit access.*/
* must be written with single 16 or 32-bit access. */
/* Bits 16-31: Reserved */
#define TPM_STATUS_CH0F (1 << 0) /* Bit 0: Channel 0 Flag */
@ -153,10 +159,12 @@
/* Bits 4-31: Reserved */
#define TPM_CONF_DOZEEN (1 << 5) /* Bit 5: Doze Enable */
#define TPM_CONF_DBGMODE_SHIFT 6 /* Bits 6-7: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (3 << TPM_CONF_DBGMODE_SHIFT)
# define TPM_CONF_DBGMODE_PAUSE (0 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter will pause during DEBUG mode */
# define TPM_CONF_DBGMODE_CONT (3 << TPM_CONF_DBGMODE_SHIFT) /* TPM counter continue working in DEBUG mode */
#define TPM_CONF_GTBSYNC (1 << 8) /* Bit 8: Global Time Base Synchronization */
#define TPM_CONF_GTBEEN (1 << 9) /* Bit 9: Global Time Base Enable */
/* Bits 10-15: Reserved */

42
arch/arm/src/kinetis/hardware/kinetis_lpuart.h
View File

@ -1,4 +1,4 @@
/****************************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_lpuart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H
/****************************************************************************************************
/****************************************************************************
* Included Files
****************************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************************************
/****************************************************************************
* Pre-processor Definitions
****************************************************************************************************/
****************************************************************************/
/* Register Offsets *********************************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_LPUART_BAUD_OFFSET 0x0000 /* Low Power UART Baud Rate Register */
#define KINETIS_LPUART_STAT_OFFSET 0x0004 /* Low Power UART Status Register */
@ -48,7 +48,7 @@
# define KINETIS_LPUART_WATER_OFFSET 0x001c /* Low Power UART Watermark Register */
#endif
/* Register Addresses *******************************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_LPUART0_BAUD (KINETIS_LPUART0_BASE + KINETIS_LPUART_BAUD_OFFSET)
#define KINETIS_LPUART0_STAT (KINETIS_LPUART0_BASE + KINETIS_LPUART_STAT_OFFSET)
@ -115,13 +115,14 @@
# define KINETIS_LPUART4_WATER (KINETIS_LPUART4_BASE + KINETIS_LPUART_WATER_OFFSET)
#endif
/* Register Bit Definitions *************************************************************************/
/* Register Bit Definitions *************************************************/
/* Low Power UART Baud Rate Register */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) (((n) & 0x1fff) << LPUART_BAUD_SBR_SHIFT) /* n= 1..8191*/
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable */
@ -133,6 +134,7 @@
# define LPUART_BAUD_MATCFG_IMW (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_MONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWU (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable */
/* Bit 22: Reserved */
@ -140,6 +142,7 @@
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-28: Over Sampling Ratio */
#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT)
#define LPUART_BAUD_OSR(n) ((((n)-1) & 0x1f) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode select */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 */
@ -186,6 +189,7 @@
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
/* Bits 11-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable */
@ -229,7 +233,7 @@
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: The current received dataword contained in DATA[R9:R0] was received with a parity error */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: The current received dataword contained in DATA[R9:R0] was received with noise */
/* Bits 16-31: This field is reserved */
/* Bits 16-31: This field is reserved */
/* Low Power UART Match Address Register */
@ -257,6 +261,7 @@
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse */
#define LPUART_MODIR_TNP_MASK (3 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) ((uint32_t)((n)-1) << LPUART_MODIR_TNP_SHIFT) /* n=1-4 */
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable */
/* Bits 19-31: Reserved */
@ -273,6 +278,7 @@
# define LPUART_FIFO_RXFIFOSIZE_64WDS (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 64 datawords */
# define LPUART_FIFO_RXFIFOSIZE_128WDS (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 128 datawords */
# define LPUART_FIFO_RXFIFOSIZE_256WDS (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 256 datawords */
# define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable */
# define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO buffer depth */
# define LPUART_FIFO_TXFIFOSIZE_MASK (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
@ -284,6 +290,7 @@
# define LPUART_FIFO_TXFIFOSIZE_64WDS (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 64 datawords */
# define LPUART_FIFO_TXFIFOSIZE_128WDS (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 128 datawords */
# define LPUART_FIFO_TXFIFOSIZE_256WDS (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* Transmit FIFO depth = 256 datawords */
# define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable */
# define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable */
# define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable */
@ -297,6 +304,7 @@
# define LPUART_FIFO_RXIDEN_16CH (5 << LPUART_FIFO_RXIDEN_SHIFT) /* RDRF when receiver is idle for 16 characters */
# define LPUART_FIFO_RXIDEN_32CH (6 << LPUART_FIFO_RXIDEN_SHIFT) /* RDRF when receiver is idle for 32 characters */
# define LPUART_FIFO_RXIDEN_64CH (7 << LPUART_FIFO_RXIDEN_SHIFT) /* RDRF when receiver is idle for 64 characters */
/* Bit 13: Reserved */
# define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO/Buffer Flush */
# define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO/Buffer Flush */
@ -325,16 +333,16 @@
# define LPUART_WATER_RXCOUNT(n) ((uint32_t)(n) << LPUART_WATER_RXCOUNT_SHIFT)
#endif
/****************************************************************************************************
/****************************************************************************
* Public Types
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
/****************************************************************************
* Public Data
****************************************************************************************************/
****************************************************************************/
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_LPUART_H */

50
arch/arm/src/kinetis/hardware/kinetis_mcg.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_mcg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_MCG_C1_OFFSET 0x0000 /* MCG Control 1 Register */
#define KINETIS_MCG_C2_OFFSET 0x0001 /* MCG Control 2 Register */
@ -81,7 +81,7 @@
# define KINETIS_MCG_T3_OFFSET 0x0013 /* MCG Control T3 Register */
#endif
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#define KINETIS_MCG_C1 (KINETIS_MCG_BASE+KINETIS_MCG_C1_OFFSET)
#define KINETIS_MCG_C2 (KINETIS_MCG_BASE+KINETIS_MCG_C2_OFFSET)
@ -127,7 +127,7 @@
# define KINETIS_MCG_T3 (KINETIS_MCG_BASE+KINETIS_MCG_T3_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* MCG Control 1 Register (8-bit) */
@ -160,6 +160,7 @@
# define MCG_C1_FRDIV_DIV1536 (7 << MCG_C1_FRDIV_SHIFT) /* RANGE!=0 divider=1536 */
# endif
#endif /* defined (KINETIS_MCG_HAS _C1_FRDIV) */
#define MCG_C1_CLKS_SHIFT (6) /* Bits 6-7: Clock Source Select */
#define MCG_C1_CLKS_MASK (3 << MCG_C1_CLKS_SHIFT)
# define MCG_C1_CLKS_PLL (0 << MCG_C1_CLKS_SHIFT) /* FLL or PLL output */
@ -181,6 +182,7 @@
# define MCG_C2_RANGE_HIGH (1 << MCG_C2_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */
# define MCG_C2_RANGE_VHIGH (2 << MCG_C2_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */
#endif
#if defined(KINETIS_MCG_HAS_C2_FCFTRIM)
# define MCG_C2_FCFTRIM (1 << 6) /* Bit 6: Fast Internal Reference Clock Fine Trim */
#endif
@ -188,7 +190,9 @@
# define MCG_C2_LOCRE0 (1 << 7) /* Bit 7: Loss of Clock Reset Enable */
#endif
/* MCG Control 3 Register (8-bit Slow Internal Reference Clock Trim Setting) */
/* MCG Control 3 Register
* (8-bit Slow Internal Reference Clock Trim Setting)
*/
/* MCG Control 4 Register (8-bit) */
@ -244,7 +248,9 @@
# define MCG_S_CLKST_INTREF (1 << MCG_S_CLKST_SHIFT) /* Internal reference clock */
# define MCG_S_CLKST_EXTREF (2 << MCG_S_CLKST_SHIFT) /* External reference clock */
# define MCG_S_CLKST_PLL (3 << MCG_S_CLKST_SHIFT) /* Output of the PLL */
# define MCG_S_IREFST (1 << 4) /* Bit 4: Internal Reference Status */
# if defined(KINETIS_MCG_HAS_S_PLLST)
# define MCG_S_PLLST (1 << 5) /* Bit 5: PLL Select Status */
# endif
@ -272,6 +278,7 @@
# define MCG_SC_FCRDIV_SHIFT (1) /* Bits 1-3: Fast Clock Internal Reference Divider */
# define MCG_SC_FCRDIV_MASK (7 << MCG_SC_FLTPRSRV_SHIFT)
# define MCG_SC_FCRDIV(n) (((n)) << MCG_SC_FLTPRSRV_SHIFT) /* n=0..7 */
# define MCG_SC_FCRDIV_1 (0 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 1 */
# define MCG_SC_FCRDIV_2 (1 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 2 */
# define MCG_SC_FCRDIV_4 (2 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 4 */
@ -280,6 +287,7 @@
# define MCG_SC_FCRDIV_32 (5 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 32 */
# define MCG_SC_FCRDIV_64 (6 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 64 */
# define MCG_SC_FCRDIV_128 (7 << MCG_SC_FLTPRSRV_SHIFT) /* Divide Factor is 128 */
# define MCG_SC_FLTPRSRV (1 << 4) /* Bit 4: FLL Filter Preserve Enable */
# if defined(KINETIS_MCG_HAS_SC_ATMF)
# define MCG_SC_ATMF (1 << 5) /* Bit 5: Automatic Trim machine Fail Flag */
@ -298,10 +306,10 @@
# if defined(KINETIS_MCG_HAS_C7_OSCSEL)
# define MCG_C7_OSCSEL_SHIFT (0) /* Bits 0-[1]: MCG OSC Clock Select */
# define MCG_C7_OSCSEL_MASK (KINETIS_MCG_C7_OSCSEL_MASK << MCG_C7_OSCSEL_SHIFT)
# define MCG_C7_OSCSEL_OSCCLK (0 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK) */
# define MCG_C7_OSCSEL_32KHZ (1 << MCG_C7_OSCSEL_SHIFT) /* Selects 32 kHz RTC Oscillator */
# define MCG_C7_OSCSEL_OSCCLK (0 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK) */
# define MCG_C7_OSCSEL_32KHZ (1 << MCG_C7_OSCSEL_SHIFT) /* Selects 32 kHz RTC Oscillator */
# if (KINETIS_MCG_C7_OSCSEL_MASK & 2) != 0
# define MCG_C7_OSCSEL_OSCCLK1 (2 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK1). */
# define MCG_C7_OSCSEL_OSCCLK1 (2 << MCG_C7_OSCSEL_SHIFT) /* Selects Oscillator (OSCCLK1). */
# endif
# endif
#endif
@ -354,6 +362,7 @@
# define MCG_C10_RANGE_LOW (0 << MCG_C10_RANGE_SHIFT) /* Oscillator of 32 kHz to 40 kHz */
# define MCG_C10_RANGE_HIGH (1 << MCG_C10_RANGE_SHIFT) /* Oscillator of 1 MHz to 8 MHz */
# define MCG_C10_RANGE_VHIGH (2 << MCG_C10_RANGE_SHIFT) /* Oscillator of 8 MHz to 32 MHz */
/* Bit 6: Reserved */
# define MCG_C10_LOCRE2 (1 << 7) /* Bit 7: OSC1 Loss of Clock Reset Enable */
#endif
@ -385,6 +394,7 @@
# define MCG_C12_VDIV1_SHIFT (0) /* Bits 0-4: VCO Divider */
# define MCG_C12_VDIV1_MASK (31 << MCG_C12_VDIV1_SHIFT)
# define MCG_C12_VDIV(n) (((n)-16) << MCG_C12_VDIV1_SHIFT) /* n=16..47 */
# define MCG_C12_CME2 (1 << 5) /* Bit 5: Clock Monitor Enable2 */
/* Bit 6: Reserved */
# define MCG_C12_LOLIE1 (1 << 7) /* Bit 7: PLL1 Loss of Lock Interrupt Enable */
@ -408,16 +418,16 @@
# endif
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MCG_H */

150
arch/arm/src/kinetis/hardware/kinetis_sim.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_sim.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */
#if defined (KINETIS_SIM_HAS_SOPT1CFG)
@ -78,8 +78,10 @@
# define KINETIS_SIM_CLKDIV4_OFFSET 0x0068 /* System Clock Divider Register 4 */
#endif
/* Register Addresses ***************************************************************/
/* NOTE: The SIM_SOPT1, SIM_SOPT1CFG and SIM_USBPHYCTL registers are located at a
/* Register Addresses *******************************************************/
/* NOTE:
* The SIM_SOPT1, SIM_SOPT1CFG and SIM_USBPHYCTL registers are located at a
* different base address than the other SIM registers.
*/
@ -126,10 +128,13 @@
# define KINETIS_SIM_CLKDIV4 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV4_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* System Options Register 1 */
/* Bits 0-11: Reserved */
/* Bits 0-11:
* Reserved
*/
#if defined(KINETIS_SIM_HAS_SOPT1_RAMSIZE)
# define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */
# define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT)
@ -139,7 +144,10 @@
# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */
# define SIM_SOPT1_RAMSIZE_256KB (10 << SIM_SOPT1_RAMSIZE_SHIFT) /* 256 KBytes */
#endif
/* Bits 16-18: Reserved */
/* Bits 16-18:
* Reserved
*/
#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL)
# define SIM_SOPT1_OSC32KSEL_SHIFT (20-KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS) /* Bit 19 or 18: 32K oscillator clock select */
# define SIM_SOPT1_OSC32KSEL_MASK (KINETIS_SIM_SOPT1_OSC32KSEL_MASK << SIM_SOPT1_OSC32KSEL_SHIFT)
@ -154,9 +162,15 @@
# define SIM_SOPT1_OSC32KSEL_LPO1KZ (((3 & KINETIS_SIM_SOPT1_OSC32KSEL_MASK)) << SIM_SOPT1_OSC32KSEL_SHIFT)
# endif
#endif
/* Bits 20-28: Reserved */
/* Bits 20-28:
* Reserved
*/
#if defined(KINETIS_SIM_HAS_SOPT1_USBVSTBY)
/* Bits 24-28: Reserved */
/* Bits 24-28:
* Reserved
*/
# define SIM_SOPT1_USBVSTBY (1 << 29) /* Bit 29: USB voltage regulator in standby mode during VLPR and VLPW modes */
#endif
#if defined(KINETIS_SIM_HAS_SOPT1_USBSSTBY)
@ -169,7 +183,10 @@
/* SOPT1 Configuration Register */
#if defined(KINETIS_SIM_HAS_SOPT1CFG)
/* Bits 0-22: Reserved */
/* Bits 0-22:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_SOPT1CFG_URWE)
# define SIM_SOPT1CFG_URWE (1 << 24) /* Bit 24: USB voltage regulator enable write enable */
# endif
@ -185,7 +202,10 @@
/* USB PHY Control Register */
#if defined(KINETIS_SIM_HAS_USBPHYCTL)
/* Bits 0-7: Reserved */
/* Bits 0-7:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL)
# define SIM_USBPHYCTL_USBVREGSEL (1 << 8) /* Bit 8: Selects the default input voltage source */
# endif
@ -205,10 +225,11 @@
# define SIM_USBPHYCTL_USB3VOUTTRG_3V310 (6 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.310V (default) */
# define SIM_USBPHYCTL_USB3VOUTTRG_3V662 (7 << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT) /* 3.662V (For Freescale use only, not for customer use) */
# endif
# if defined(KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM)
# define SIM_USBPHYCTL_USBDISILIM (1 << 23) /* Bit 23: USB Disable Inrush Current Limit */
# endif
/* Bits 24-31: Reserved */
/* Bits 24-31: Reserved */
#endif
/* System Options Register 2 */
@ -282,6 +303,7 @@
/* Bit 19: Reserved */
# if defined(KINETIS_SIM_HAS_SOPT2_RMIISRC)
# define SIM_SOPT2_RMIISRC_SHIFT (19) /* Bit 19: RMII clock source select */
# define SIM_SOPT2_RMIISRC_EXTAL (0 << SIM_SOPT2_RMIISRC_SHIFT) /* EXTAL clock */
# define SIM_SOPT2_RMIISRC_EXTBYP (1 << SIM_SOPT2_RMIISRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */
# endif
@ -290,7 +312,7 @@
# define SIM_SOPT2_TIMESRC_MASK (3 << SIM_SOPT2_TIMESRC_SHIFT)
# define SIM_SOPT2_TIMESRC_CORE (0 << SIM_SOPT2_TIMESRC_SHIFT) /* Core/system clock */
# define SIM_SOPT2_TIMESRC_PLLSEL (1 << SIM_SOPT2_TIMESRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
clock as selected by SOPT2[PLLFLLSEL] */
* clock as selected by SOPT2[PLLFLLSEL] */
# define SIM_SOPT2_TIMESRC_OSCERCLK (2 << SIM_SOPT2_TIMESRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_TIMESRC_EXTBYP (3 << SIM_SOPT2_TIMESRC_SHIFT) /* External bypass clock (ENET_1588_CLKIN) */
# endif
@ -316,9 +338,9 @@
# define SIM_SOPT2_TPMSRC_MASK (3 << SIM_SOPT2_TPMSRC_SHIFT)
# define SIM_SOPT2_TPMSRC_CORE (0 << SIM_SOPT2_TPMSRC_SHIFT) /* Clock disabled */
# define SIM_SOPT2_TPMSRC_MCGCLK (1 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
clock as selected by SOPT2[PLLFLLSEL] and then
divided by the PLLFLLCLK fractional divider
as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
* clock as selected by SOPT2[PLLFLLSEL] and then
* divided by the PLLFLLCLK fractional divider
* as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
# define SIM_SOPT2_TPMSRC_OCSERCLK (2 << SIM_SOPT2_TPMSRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_TPMSRC_MCGIRCLK (3 << SIM_SOPT2_TPMSRC_SHIFT) /* MCGIRCLK clock */
# endif
@ -336,9 +358,9 @@
# define SIM_SOPT2_LPUARTSRC_MASK (3 << SIM_SOPT2_LPUARTSRC_SHIFT)
# define SIM_SOPT2_LPUARTSRC_CORE (0 << SIM_SOPT2_LPUARTSRC_SHIFT) /* Clock disabled */
# define SIM_SOPT2_LPUARTSRC_MCGCLK (1 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGFLLCLK,MCGPLLCLK,IRC48M,USB1 PFD
clock as selected by SOPT2[PLLFLLSEL] and then
divided by the PLLFLLCLK fractional divider
as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
* clock as selected by SOPT2[PLLFLLSEL] and then
* divided by the PLLFLLCLK fractional divider
* as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV] */
# define SIM_SOPT2_LPUARTSRC_OCSERCLK (2 << SIM_SOPT2_LPUARTSRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_LPUARTSRC_MCGIRCLK (3 << SIM_SOPT2_LPUARTSRC_SHIFT) /* MCGIRCLK clock */
# endif
@ -349,9 +371,15 @@
# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */
# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */
# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */
/* Bits 30-31: Reserved */
/* Bits 30-31:
* Reserved
*/
# endif
/* Bits 30-31: Reserved */
/* Bits 30-31:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_SOPT2_NFCSRC)
# define SIM_SOPT2_NFCSRC_SHIFT (30) /* Bits 30-31: NFC Flash clock source select */
# define SIM_SOPT2_NFCSRC_MASK (3 << SIM_SOPT2_NFCSRC_SHIFT)
@ -475,7 +503,11 @@
#endif
#if defined(KINETIS_SIM_HAS_SOPT5_LPUART1TXSRC)
/* Bits 8-15, 18-31: Reserved */
/* Bits 8-15,
* 18-31:
* Reserved
*/
# define SIM_SOPT5_LPUART1TXSRC_SHIFT (16) /* Bit 16: LPUART1 transmit data source select */
# define SIM_SOPT5_LPUART1TXSRC_MASK (3 << SIM_SOPT5_LPUART1TXSRC_SHIFT)
# define SIM_SOPT5_LPUART1TXSRC_TX (0 << SIM_SOPT5_LPUART1TXSRC_SHIFT) /* LPUART1_TX pin */
@ -495,9 +527,15 @@
/* System Options Register 6 */
#if defined(KINETIS_SIM_HAS_SOPT6)
/* Bits 0-23: Reserved */
/* Bits 0-23:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_SOPT6_MCC)
/* Bits 16-23: Reserved */
/* Bits 16-23:
* Reserved
*/
# define SIM_SOPT6_MCC_SHIFT (0) /* Bits 0-15: NFC hold cycle in case FlexBus request while NFC is granted */
# define SIM_SOPT6_MCC_MASK (0xffff << SIM_SOPT6_MCC_SHIFT)
# define SIM_SOPT6_MCC(n) (((n) & 0xffff) << SIM_SOPT6_MCC_SHIFT)
@ -749,7 +787,10 @@
/* System Options Register 9 */
#if defined(KINETIS_SIM_HAS_SOPT9)
/* Bits 0-17: Reserved */
/* Bits 0-17:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC)
# define SIM_SOPT9_TPM1CH0SRC_SHIFT (18) /* Bits 18-19: TPM1 channel 0 input capture source select */
# define SIM_SOPT9_TPM1CH0SRC_MASK (3 << SIM_SOPT9_TPM1CH0SRC_SHIFT)
@ -854,13 +895,18 @@
# define SIM_SDID_FAMILYID_K8X (8 << SIM_SDID_FAMILYID_SHIFT) /* K8x Family */
#endif
/* System Clock Gating Control Register 1 */
#if defined(KINETIS_SIM_HAS_SCGC1)
/* Bits 0-9: Reserved */
/* Bits 0-9:
* Reserved
*/
# if defined(KINETIS_SIM_HAS_SCGC1_OSC1)
/* Bits 0-4: Reserved */
/* Bits 0-4:
* Reserved
*/
# define SIM_SCGC1_OSC1 (1 << 5) /* OSC1 clock gate control */
# endif
/* Bits 6-9: Reserved */
@ -1103,12 +1149,16 @@
/* System Clock Divider Register 1 */
#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV5)
/* Bits 0-15: Reserved */
/* Bits 0-15:
* Reserved
*/
#endif
#if defined(KINETIS_SIM_HAS_CLKDIV1_OUTDIV4)
# define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */
# define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT)
# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */
@ -1130,6 +1180,7 @@
# define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */
# define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT)
# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */
@ -1151,6 +1202,7 @@
# define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */
# define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT)
# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */
@ -1171,6 +1223,7 @@
#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */
#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT)
# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)(((n)-1) & 0xf) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */
# define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */
# define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */
# define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */
@ -1295,6 +1348,7 @@
#endif
/* Flash Configuration Register 2 */
/* Bits 0-15: Reserved */
#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR1)
# define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-[21|22]: Max address block 1 */
@ -1316,8 +1370,11 @@
#endif
/* Unique Identification Register High. 32-bit Unique Identification. */
/* Unique Identification Register Mid-High. 32-bit Unique Identification. */
/* Unique Identification Register Mid Low. 32-bit Unique Identification. */
/* Unique Identification Register Low. 32-bit Unique Identification. */
#if defined(KINETIS_SIM_HAS_CLKDIV3)
@ -1363,22 +1420,25 @@
/* Misc Control Register */
#if defined(KINETIS_SIM_HAS_MCR)
/* Bits 0-28: Reserved */
# define SIM_MCR_PDBLOOP (1<< 29) /* Bit 29: PDB Loop Mode */
/* Bit 30: Reserved */
# define SIM_MCR_TRACECLKDIS (1<< 31) /* Bit 31: Trace clock disable. */
/* Bits 0-28:
* Reserved
*/
# define SIM_MCR_PDBLOOP (1<< 29) /* Bit 29: PDB Loop Mode */
/* Bit 30: Reserved */
# define SIM_MCR_TRACECLKDIS (1<< 31) /* Bit 31: Trace clock disable. */
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_SIM_H */

41
arch/arm/src/kinetis/hardware/kinetis_uart.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/hardware/kinetis_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,24 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H
#define __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/kinetis_memorymap.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Register Offsets *****************************************************************/
/* Register Offsets *********************************************************/
#define KINETIS_UART_BDH_OFFSET 0x0000 /* UART Baud Rate Register High */
#define KINETIS_UART_BDL_OFFSET 0x0001 /* UART Baud Rate Register Low */
@ -67,7 +67,7 @@
#define KINETIS_UART_ET7816_OFFSET 0x001e /* UART 7816 Error Threshold Register */
#define KINETIS_UART_TL7816_OFFSET 0x001f /* UART 7816 Transmit Length Register */
/* Register Addresses ***************************************************************/
/* Register Addresses *******************************************************/
#if (KINETIS_NISO7816+KINETIS_NUART) > 0
# define KINETIS_UART0_BDH (KINETIS_UART0_BASE+KINETIS_UART_BDH_OFFSET)
@ -273,7 +273,8 @@
# define KINETIS_UART5_TL7816 (KINETIS_UART5_BASE+KINETIS_UART_TL7816_OFFSET)
#endif
/* Register Bit Definitions *********************************************************/
/* Register Bit Definitions *************************************************/
/* UART Baud Rate Register High */
#define UART_BDH_SBR_SHIFT (0) /* Bits 0-4: MS Bits 8-13 of the UART Baud Rate Bits */
@ -341,6 +342,7 @@
#define UART_C3_R8 (1 << 7) /* Bit 7: Received Bit 8 */
/* UART Data Register: 8-bit data register. */
/* UART Match Address Registers 1 & 2: 8-bit address registers */
/* UART Control Register 4 */
@ -382,6 +384,7 @@
# define UART_IR_TNP_16TH (1 << UART_IR_TNP_SHIFT) /* 1/16 */
# define UART_IR_TNP_32ND (2 << UART_IR_TNP_SHIFT) /* 1/32 */
# define UART_IR_TNP_4TH (3 << UART_IR_TNP_SHIFT) /* 1/4 */
#define UART_IR_IREN (1 << 2) /* Bit 2: Infrared enable */
/* Bits 3-7: Reserved */
@ -396,6 +399,7 @@
# define UART_PFIFO_RXFIFOSIZE_32 (4 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 32 */
# define UART_PFIFO_RXFIFOSIZE_64 (5 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 64 */
# define UART_PFIFO_RXFIFOSIZE_128 (6 << UART_PFIFO_RXFIFOSIZE_SHIFT) /* 128 */
#define UART_PFIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable */
#define UART_PFIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO. Buffer Depth */
#define UART_PFIFO_TXFIFOSIZE_MASK (7 << UART_PFIFO_TXFIFOSIZE_SHIFT)
@ -406,6 +410,7 @@
# define UART_PFIFO_TXFIFOSIZE_32 (4 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 32 */
# define UART_PFIFO_TXFIFOSIZE_64 (5 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 64 */
# define UART_PFIFO_TXFIFOSIZE_128 (6 << UART_PFIFO_TXFIFOSIZE_SHIFT) /* 128 */
#define UART_PFIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable */
/* UART FIFO Control Register */
@ -425,8 +430,11 @@
#define UART_SFIFO_TXEMPT (1 << 7) /* Bit 7: Transmit Buffer/FIFO Empty */
/* UART FIFO Transmit Watermark. 8-bit watermark value. */
/* UART FIFO Transmit Count. 8-bit count value */
/* UART FIFO Receive Watermark. 8-bit watermark value. */
/* UART FIFO Receive Count. 8-bit count value */
/* UART 7816 Control Register */
@ -470,6 +478,7 @@
#define UART_WP7816T1_CWI_MASK (15 << UART_WP7816T1_CWI_SHIFT)
/* UART 7816 Wait N Register. 8-bit Guard Band value. */
/* UART 7816 Wait FD Register. 8-bit FD Multiplier value. */
/* UART 7816 Error Threshold Register */
@ -481,16 +490,16 @@
/* UART 7816 Transmit Length Register. 8-bit Transmit Length value */
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_UART_H */

13
arch/arm/src/kinetis/kinetis_clockconfig.c
View File

@ -141,7 +141,8 @@
****************************************************************************/
void __ramfunc__
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4);
kinesis_setdividers(uint32_t div1, uint32_t div2,
uint32_t div3, uint32_t div4);
/****************************************************************************
* Private Functions
@ -310,7 +311,8 @@ void kinetis_pllconfig(void)
* Flash clock = MCG / BOARD_OUTDIV4
*/
kinesis_setdividers(BOARD_OUTDIV1, BOARD_OUTDIV2, BOARD_OUTDIV3, BOARD_OUTDIV4);
kinesis_setdividers(BOARD_OUTDIV1, BOARD_OUTDIV2,
BOARD_OUTDIV3, BOARD_OUTDIV4);
/* Set the VCO divider, VDIV, is defined in the board.h file. VDIV
* selects the amount to divide the VCO output of the PLL. The VDIV bits
@ -391,7 +393,9 @@ static inline void kinetis_traceconfig(void)
{
uint32_t regval;
/* Set the trace clock to the core clock frequency in the SIM SOPT2 register */
/* Set the trace clock to the core clock frequency in the SIM SOPT2
* register
*/
regval = getreg32(KINETIS_SIM_SOPT2);
regval |= SIM_SOPT2_TRACECLKSEL;
@ -480,7 +484,8 @@ void kinetis_clockconfig(void)
****************************************************************************/
void __ramfunc__
kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4)
kinesis_setdividers(uint32_t div1, uint32_t div2,
uint32_t div3, uint32_t div4)
{
uint32_t regval;
volatile int i;

53
arch/arm/src/kinetis/kinetis_config.h
View File

@ -1,4 +1,4 @@
/************************************************************************************
/****************************************************************************
* arch/arm/src/kinetis/kinetis_config.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@ -16,25 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
************************************************************************************/
****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H
/************************************************************************************
/****************************************************************************
* Included Files
************************************************************************************/
****************************************************************************/
#include <nuttx/config.h>
#include <arch/board/board.h>
#include "chip.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
/* Configuration ************************************************************/
/* Configuration *********************************************************************/
/* Make sure that no unsupported UARTs are enabled */
#ifndef KINETIS_NLPUART
@ -96,8 +97,8 @@
# define HAVE_LPUART_DEVICE 1
#endif
/* Is there a serial console? There should be at most one defined. It could be on
* any UARTn, n=0,1,2,3,4,5
/* Is there a serial console? There should be at most one defined.
* It could be on any UARTn, n=0,1,2,3,4,5
*/
#undef HAVE_UART_CONSOLE
@ -268,14 +269,14 @@
/* Which version of up_putc() should be built?
*
* --------------------+-------------------+-----------------+------------------
* HAVE_UART_DEVICE && HAVE_UART_DEVICE HAVE_LPUART_DEVICE
* HAVE_LPUART_DEVICE (only) (only)
* --------------------+-------------------+-----------------+------------------
* HAVE_UART_CONSOLE kinetis_serial kinetis_serial (impossible)
* HAVE_LPUART_CONSOLE kinetis_lpserial (impossible) kinetis_lpserial
* No serial console kinetis_serial kinetis_serial kinetis_lpserial
* --------------------+-------------------+-----------------+------------------
* -------------------+------------------+----------------+------------------
* HAVE_UART_DEVICE && HAVE_UART_DEVICE HAVE_LPUART_DEVICE
* HAVE_LPUART_DEVICE (only) (only)
* -------------------+------------------+----------------+------------------
* HAVE_UART_CONSOLE kinetis_serial kinetis_serial (impossible)
* HAVE_LPUART_CONSOLE kinetis_lpserial (impossible) kinetis_lpserial
* No serial console kinetis_serial kinetis_serial kinetis_lpserial
* --------------------+------------------+----------------+-----------------
*/
#undef HAVE_UART_PUTC
@ -336,20 +337,20 @@
# define CONFIG_ENETNETHIFS 1
#endif
/************************************************************************************
/****************************************************************************
* Public Types
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Inline Functions
************************************************************************************/
****************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H */

5
arch/arm/src/kinetis/kinetis_serialinit.c
View File

@ -91,7 +91,7 @@ void arm_serialinit(void)
#if defined(HAVE_LPUART_DEVICE) && defined(CONFIG_KINETS_LPUART_LOWEST)
/* Register LPUART drivers in starting positions */
start = kinetis_lpuart_serialinit(start);
start = kinetis_lpuart_serialinit(start);
#endif
#if defined(HAVE_UART_DEVICE)
@ -103,8 +103,7 @@ void arm_serialinit(void)
#if defined(HAVE_LPUART_DEVICE) && !defined(CONFIG_KINETS_LPUART_LOWEST)
/* Register LPUART drivers in last positions */
start = kinetis_lpuart_serialinit(start);
start = kinetis_lpuart_serialinit(start);
#endif
}
#endif /* USE_SERIALDRIVER */

63
arch/arm/src/kinetis/kinetis_spi.h
View File

@ -29,9 +29,9 @@
#include "hardware/kinetis_dspi.h"
/************************************************************************************
/****************************************************************************
* Pre-processor Definitions
************************************************************************************/
****************************************************************************/
#ifndef __ASSEMBLY__
@ -44,9 +44,9 @@ extern "C"
#define EXTERN extern
#endif
/************************************************************************************
/****************************************************************************
* Public Data
************************************************************************************/
****************************************************************************/
struct spi_dev_s;
@ -54,7 +54,7 @@ struct spi_dev_s;
* Public Function Prototypes
****************************************************************************/
/************************************************************************************
/****************************************************************************
* Name: kinetis_spibus_initialize
*
* Description:
@ -66,54 +66,60 @@ struct spi_dev_s;
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
************************************************************************************/
****************************************************************************/
FAR struct spi_dev_s *kinetis_spibus_initialize(int bus);
/************************************************************************************
* Name: kinetis_spi[n]select, kinetis_spi[n]status, and kinetis_spi[n]cmddata
/****************************************************************************
* Name:
* kinetis_spi[n]select, kinetis_spi[n]status, and kinetis_spi[n]cmddata
*
* Description:
* These external functions must be provided by board-specific logic. They are
* implementations of the select, status, and cmddata methods of the SPI interface
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
* including kinetis_spibus_initialize()) are provided by common Kinetis logic. To use
* this common SPI logic on your board:
* These external functions must be provided by board-specific logic.
* They are implementations of the select, status, and cmddata methods of
* the SPI interface defined by struct spi_ops_s
* (see include/nuttx/spi/spi.h). All other methods including
* kinetis_spibus_initialize()) are provided by common Kinetis logic.
* To use this common SPI logic on your board:
*
* 1. Provide logic in kinetis_boardinitialize() to configure SPI chip select
* pins.
* 1. Provide logic in kinetis_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide kinetis_spi[n]select() and kinetis_spi[n]status() functions
* in your board-specific logic. These functions will perform chip selection
* and status operations using GPIOs in the way your board is configured.
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board is
* configured.
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
* kinetis_spi[n]cmddata() functions in your board-specific logic. These
* functions will perform cmd/data selection operations using GPIOs in the way
* your board is configured.
* 3. Add a call to kinetis_spibus_initialize() in your low level application
* initialization logic
* 4. The handle returned by kinetis_spibus_initialize() may then be used to bind the
* SPI driver to higher level logic (e.g., calling
* kinetis_spi[n]cmddata() functions in your board-specific logic.
* These functions will perform cmd/data selection operations using
* GPIOs in the way your board is configured.
* 3. Add a call to kinetis_spibus_initialize() in your low level
* application initialization logic
* 4. The handle returned by kinetis_spibus_initialize() may then be used
* to bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
************************************************************************************/
****************************************************************************/
#ifdef CONFIG_KINETIS_SPI0
void kinetis_spi0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void kinetis_spi0select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t kinetis_spi0status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int kinetis_spi0cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_KINETIS_SPI1
void kinetis_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void kinetis_spi1select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t kinetis_spi1status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int kinetis_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#endif
#ifdef CONFIG_KINETIS_SPI2
void kinetis_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected);
void kinetis_spi2select(FAR struct spi_dev_s *dev,
uint32_t devid, bool selected);
uint8_t kinetis_spi2status(FAR struct spi_dev_s *dev, uint32_t devid);
#ifdef CONFIG_SPI_CMDDATA
int kinetis_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd);
@ -145,6 +151,5 @@ struct spi_dev_s;
void spi_flush(FAR struct spi_dev_s *dev);
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SPI_H */