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risc-v/rv-virt: revise mstatus operations

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- drop set of SUM as it is done in  riscv_set_idleintctx()
- fix the CLEAR_CSR() before setting MPP field

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
This commit is contained in:
Yanfeng Liu 2024-01-06 11:36:11 +08:00 committed by Xiang Xiao
parent 438439c1a6
commit 207efa047b
1 changed files with 3 additions and 3 deletions
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arch/risc-v/src/qemu-rv/qemu_rv_start.c
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@ -191,10 +191,10 @@ void qemu_rv_start(int mhartid, const char *dtb)
CLEAR_CSR(mstatus, MSTATUS_TVM);
/* Set mstatus to S-mode and enable SUM */
/* Set mstatus to S-mode */
CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK);
SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM);
CLEAR_CSR(mstatus, MSTATUS_MPP_MASK);
SET_CSR(mstatus, MSTATUS_MPPS);
/* Set the trap vector for S-mode */