From 207efa047b707ab2d4167e6f0d9f23d353f53efc Mon Sep 17 00:00:00 2001 From: Yanfeng Liu Date: Sat, 6 Jan 2024 11:36:11 +0800 Subject: [PATCH] risc-v/rv-virt: revise mstatus operations - drop set of SUM as it is done in riscv_set_idleintctx() - fix the CLEAR_CSR() before setting MPP field Signed-off-by: Yanfeng Liu --- arch/risc-v/src/qemu-rv/qemu_rv_start.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_start.c b/arch/risc-v/src/qemu-rv/qemu_rv_start.c index e3465bcac5..132b7fbf88 100644 --- a/arch/risc-v/src/qemu-rv/qemu_rv_start.c +++ b/arch/risc-v/src/qemu-rv/qemu_rv_start.c @@ -191,10 +191,10 @@ void qemu_rv_start(int mhartid, const char *dtb) CLEAR_CSR(mstatus, MSTATUS_TVM); - /* Set mstatus to S-mode and enable SUM */ + /* Set mstatus to S-mode */ - CLEAR_CSR(mstatus, ~MSTATUS_MPP_MASK); - SET_CSR(mstatus, MSTATUS_MPPS | SSTATUS_SUM); + CLEAR_CSR(mstatus, MSTATUS_MPP_MASK); + SET_CSR(mstatus, MSTATUS_MPPS); /* Set the trap vector for S-mode */