Add MIPS32 interrupt controls
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3620 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
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@ -1,5 +1,5 @@
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/********************************************************************************************
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* arch/mips/src/mips32/mips32-cp0.h
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* arch/mips/include/mips32/cp0.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -33,8 +33,8 @@
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H
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#define __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H
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#ifndef __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
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#define __ARCH_MIPS_INCLUDE_MIPS32_CP0_H
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/********************************************************************************************
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* Included Files
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@ -178,15 +178,18 @@
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#define CP0_STATUS_KX (1 << 7) /* Bit 7: Enables 64-bit kernel address space (Not MIPS32) */
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#define CP0_STATUS_IM_SHIFT (8) /* Bits 8-15: Interrupt Mask */
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#define CP0_STATUS_IM_MASK (0xff << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM_SWINTS (0x03 << CP0_STATUS_IM_SHIFT) /* IM0-1 = Software interrupts */
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# define CP0_STATUS_IM0 (0x01 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM1 (0x02 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM_HWINTS (0x7c << CP0_STATUS_IM_SHIFT) /* IM2-6 = Hardware interrupts */
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# define CP0_STATUS_IM2 (0x04 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM3 (0x08 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM4 (0x10 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM5 (0x20 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM6 (0x40 << CP0_STATUS_IM_SHIFT)
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# define CP0_STATUS_IM_TIMER (0x80 << CP0_STATUS_IM_SHIFT) /* IM7 = Hardware/Timer/Perf interrupts */
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# define CP0_STATUS_IM7 (0x80 << CP0_STATUS_IM_SHIFT)
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#define CP0_STATUS_IMPL_SHIFT (16) /* Bits 16-17: Interrupt Mask */
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#define CP0_STATUS_IMPL_SHIFT (16) /* Bits 16-17: Implementation dependent */
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#define CP0_STATUS_IMPL_MASK (3 << CP0_STATUS_IMPL_SHIFT)
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#define CP0_STATUS_NMI (1 << 19) /* Bit 19: Reset exception due to an NMI */
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#define CP0_STATUS_SR (1 << 20) /* Bit 20: Reset exception due to a Soft Reset */
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@ -532,4 +535,4 @@ extern "C" {
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_MIPS32_MIPS32_CP0_H */
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#endif /* __ARCH_MIPS_INCLUDE_MIPS32_CP0_H */
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@ -44,6 +44,8 @@
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* Included Files
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****************************************************************************/
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#include <arch/types.h>
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/****************************************************************************
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* Definitions
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****************************************************************************/
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@ -92,6 +94,39 @@ extern "C" {
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: irqsave
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*
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* Description:
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* Save the current interrupt state and disable interrupts.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Interrupt state prior to disabling interrupts.
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*
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****************************************************************************/
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EXTERN irqstate_t irqsave(void);
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/****************************************************************************
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* Name: irqrestore
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*
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* Description:
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* Restore the previous interrupt state (i.e., the one previously returned
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* by irqsave())
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*
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* Input Parameters:
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* state - The interrupt state to be restored.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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EXTERN void irqrestore(irqstate_t irqtate);
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#undef EXTERN
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#ifdef __cplusplus
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}
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/mips/src/pic32mx/pic32mx-cp0.h
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* arch/mips/include/pic32mx/cp0.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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@ -33,8 +33,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H
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#ifndef __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
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#define __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H
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/****************************************************************************
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* Included Files
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@ -42,7 +42,7 @@
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#include <nuttx/config.h>
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#include "mips32-cp0.h"
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#include <arch/mips32/cp0.h>
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/****************************************************************************
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* Pre-Processor Definitions
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@ -71,13 +71,13 @@
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* exception
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 9 Sel: 0 Name: Count
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* Function: Processor cycle count
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 10 Reserved.
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* Compliance Level: Required for TLB-based MMU; Optional otherwise.
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@ -86,20 +86,20 @@
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* Function: Timer interrupt control
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 12 Sel: 0 Name: Status
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* Function: Processor status and control
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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* NOTES:
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* 1. The following are reserved bits in the PIC32:
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* CP0_STATUS_UX Bit 5: Enables 64-bit user address space (Not MIPS32)
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* CP0_STATUS_SX Bit 6: Enables 64-bit supervisor address space (Not MIPS32)
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* CP0_STATUS_KX Bit 7: Enables 64-bit kernel address space (Not MIPS32)
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* CP0_STATUS_IMPL Bits 16-17: Interrupt Mask
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* CP0_STATUS_IMPL Bits 16-17: Implementation dependent
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* CP0_STATUS_TS Bit 21: TLB detected match on multiple entries
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* CP0_STATUS_PX Bit 23: Enables 64-bit operations (Not MIPS32)
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* CP0_STATUS_MX Bit 24: Enables MDMX™ (Not MIPS32)
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@ -196,7 +196,7 @@
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* Function: Cause of last general exception
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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* NOTES: The following bits are added in the PIC32:
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*/
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@ -208,14 +208,14 @@
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* Function: Program counter at last exception
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*/
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/* Register Number: 15 Sel: 0 Name: PRId
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* Function: Processor identification and revision
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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* NOTE: Slightly different bit interpretations of some fields:
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*/
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@ -240,7 +240,7 @@
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* Function: Configuration register
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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* 1. PIC32MX is always little-endian.
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* 2. Implementation specific bits defined.
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*/
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@ -265,13 +265,13 @@
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* Function: Configuration register 1
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 16 Sel: 2 Name: Config2
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* Function: Configuration register 2
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* Compliance Level: Optional.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*/
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#undef CP0_CONFIG2_TBS_SHIFT
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@ -281,7 +281,7 @@
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* Function: Configuration register 3
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* Compliance Level: Optional.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*/
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#define CP0_CONFIG3_SP (1 << 4) /* Bit 4: Support page bit */
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@ -332,7 +332,7 @@
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* Function: Program counter at last EJTAG debug exception
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* Compliance Level: Optional.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 25-29 Reserved
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* Compliance Level: Recommended/Optional.
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@ -341,13 +341,13 @@
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* Function: Program counter at last error
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* Compliance Level: Required.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*
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* Register Number: 31 Sel: 0 Name: DeSAVE
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* Function: EJTAG debug exception save register
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* Compliance Level: Optional.
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*
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* See arch/mips/src/mips32/mips32-cp0.h
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* See arch/mips/include/mips32/cp0.h
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*/
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/****************************************************************************
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@ -377,4 +377,4 @@ extern "C" {
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_CP0_H */
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#endif /* __ARCH_MIPS_INCLUDE_PIC32MX_CP0_H */
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178
arch/mips/src/mips32/up_irq.c
Normal file
178
arch/mips/src/mips32/up_irq.c
Normal file
@ -0,0 +1,178 @@
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/****************************************************************************
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* arch/mips/src/mips32/up_irq.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/types.h>
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#include <arch/mips32/cp0.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: cp0_getstatus
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*
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* Description:
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* Disable interrupts
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline irqstate_t cp0_getstatus(void)
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{
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register irqstate_t status;
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t mfc0 %0,$12\n" /* Get CP0 status register */
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"\t.set pop\n"
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: "=r" (status)
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:
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: "memory"
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);
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return status;
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}
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/****************************************************************************
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* Name: cp0_putstatus
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*
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* Description:
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* Disable interrupts
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static inline void cp0_putstatus(irqstate_t status)
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{
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__asm__ __volatile__
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(
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"\t.set push\n"
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"\t.set noat\n"
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"\t.set noreorder\n"
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"\tmtc0 %0,$12\n" /* Set the status to the provided value */
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"\tnop\n" /* MTC0 status hazard: */
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"\tnop\n" /* Recommended spacing: 3 */
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"\tnop\n"
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"\tnop\n" /* Plus one for good measure */
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"\t.set pop\n"
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:
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: "r" (status)
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: "memory"
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);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: irqsave
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*
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* Description:
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* Save the current interrupt state and disable interrupts.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Interrupt state prior to disabling interrupts.
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*
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****************************************************************************/
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irqstate_t irqsave(void)
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{
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register irqstate_t status;
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register irqstate_t ret;
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status = cp0_getstatus(); /* Get CP0 status */
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ret = status; /* Save the status */
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status &= ~CP0_STATUS_IM_MASK; /* Clear all interrupt mask bits */
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status |= CP0_STATUS_IM_SWINTS; /* Keep S/W interrupts enabled */
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cp0_putstatus(status); /* Disable interrupts */
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return ret; /* Return status before interrtupts disabled */
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}
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/****************************************************************************
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* Name: irqrestore
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*
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* Description:
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* Restore the previous interrutp state (i.e., the one previously returned
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* by irqsave())
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*
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* Input Parameters:
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* state - The interrupt state to be restored.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void irqrestore(irqstate_t irqstate)
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{
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register irqstate_t status;
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status = cp0_getstatus(); /* Get CP0 status */
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status &= ~CP0_STATUS_IM_MASK; /* Clear all interrupt mask bits */
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irqstate &= CP0_STATUS_IM_MASK; /* Retain interrupt mask bits only */
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status |= irqstate; /* Set new interrupt mask bits */
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status |= CP0_STATUS_IM_SWINTS; /* Make sure that S/W interrupts enabled */
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cp0_putstatus(status); /* Restore interrupt state */
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}
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@ -40,7 +40,7 @@ HEAD_ASRC =
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# Common MIPS files
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CMN_ASRCS =
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CMN_CSRCS = up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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CMN_CSRCS = up_irq.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
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# Required PIC32MX files
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