Merged in alinjerpelea/nuttx (pull request #884)
arch: arm: cxd56xx: add support for USB and SDIO
* arch: arm: cxd56xx: add support for USB connectivity
Add basic support for USB connectivity
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
* arch: arm: cxd56xx: add SDHCI support
We add SDHCI driver for the cxd56xx
Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Alin Jerpelea
Gregory Nutt
parent
900c32c021
commit
215a146f2e
65
arch/arm/include/cxd56xx/usbdev.h
Normal file
65
arch/arm/include/cxd56xx/usbdev.h
Normal file
@ -0,0 +1,65 @@
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/****************************************************************************
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* arch/arm/include/cxd56xx/usbdev.h
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
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* the names of its contributors may be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
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#define __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* BOARDIOC_USBDEV_SETNOTIFYSIG signal value ************************************************/
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#define USBDEV_STATE_DETACH 0
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#define USBDEV_STATE_ATTACH 1
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/*
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* The BOARDIOC_USBDEV_SETNOTIFYSIG signal output the VBUS connection state
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* and supply current value to the signal handler argument (sival_int).
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*
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* Please use the following macros.
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*
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* - USBDEV_CONNECTED : Get VBUS connection state.
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* - USBDEV_POWER_CURRENT : Get VBUS supply current.
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*/
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#define USBDEV_CONNECTED(x) (0xffff & ((x)>>16))
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#define USBDEV_POWER_CURRENT(x) (0xffff & (x))
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#endif /* __ARCH_ARM_INCLUDE_CXD56XX_USBDEV_H */
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@ -68,4 +68,51 @@ config CXD56_UART2
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---help---
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UART interface with hardware flow control in the application subsystem.
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config CXD56_USBDEV
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bool "USB"
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default n
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---help---
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Enables USB
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menuconfig CXD56_SDIO
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bool "SDIO SD Card"
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default n
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select ARCH_HAVE_SDIO
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select SDIO_BLOCKSETUP
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select SCHED_WORKQUEUE
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select SCHED_HPWORK
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if CXD56_SDIO
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config CXD56_SDIO_DMA
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bool "Support DMA data transfers"
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default y
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select SDIO_DMA
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---help---
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Support DMA data transfers.
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Enable SD card DMA data transfers. This is marginally optional.
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For most usages, SD accesses will cause data overruns if used without
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DMA.
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config CXD56_SDIO_WIDTH_D1_ONLY
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bool "Use D1 only"
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default n
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---help---
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Select 1-bit transfer mode. Default: 4-bit transfer mode.
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config CXD56_SDIO_DISABLE_CD_WP
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bool "Disable the CD and WP pin for SDIO"
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default y
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---help---
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Disable the CD and WP pin for Embedded SDIO.If the CD pin is not disable,
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the SDIO initialization will be failed.
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config CXD56_SDIO_ENABLE_MULTIFUNCTION
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bool "Enable SDIO multi-function"
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default n
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---help---
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Support multi-function with SDIO interfaced peripheral other than SD Card.
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endif # SDIO Configuration
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endmenu
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@ -97,3 +97,7 @@ CHIP_CSRCS += cxd56_icc.c
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ifeq ($(CONFIG_CXD56_GPIO_IRQ),y)
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CHIP_CSRCS += cxd56_gpioint.c
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endif
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ifeq ($(CONFIG_USBDEV),y)
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CHIP_CSRCS += cxd56_usbdev.c
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endif
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4583
arch/arm/src/cxd56xx/cxd56_sdhci.c
Normal file
4583
arch/arm/src/cxd56xx/cxd56_sdhci.c
Normal file
File diff suppressed because it is too large
Load Diff
463
arch/arm/src/cxd56xx/cxd56_sdhci.h
Normal file
463
arch/arm/src/cxd56xx/cxd56_sdhci.h
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@ -0,0 +1,463 @@
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/****************************************************************************
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* arch/arm/src/cxd56xx/cxd56_sdhci.h
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*
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* Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Copyright 2018 Sony Semiconductor Solutions Corporation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H
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#define __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register Offsets *********************************************************/
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#define CXD56_SDHCI_DSADDR_OFFSET (0x0000) /* DMA System Address Register */
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#define CXD56_SDHCI_BLKATTR_OFFSET (0x0004) /* Block Attributes Register */
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#define CXD56_SDHCI_CMDARG_OFFSET (0x0008) /* Command Argument Register */
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#define CXD56_SDHCI_XFERTYP_OFFSET (0x000c) /* Transfer Type Register */
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#define CXD56_SDHCI_CMDRSP0_OFFSET (0x0010) /* Command Response 0 */
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#define CXD56_SDHCI_CMDRSP1_OFFSET (0x0014) /* Command Response 1 */
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#define CXD56_SDHCI_CMDRSP2_OFFSET (0x0018) /* Command Response 2 */
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#define CXD56_SDHCI_CMDRSP3_OFFSET (0x001c) /* Command Response 3 */
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#define CXD56_SDHCI_DATPORT_OFFSET (0x0020) /* Buffer Data Port Register */
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#define CXD56_SDHCI_PRSSTAT_OFFSET (0x0024) /* Present State Register */
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#define CXD56_SDHCI_PROCTL_OFFSET (0x0028) /* Protocol Control Register */
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#define CXD56_SDHCI_SYSCTL_OFFSET (0x002c) /* System Control Register */
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#define CXD56_SDHCI_IRQSTAT_OFFSET (0x0030) /* Interrupt Status Register */
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#define CXD56_SDHCI_IRQSTATEN_OFFSET (0x0034) /* Interrupt Status Enable Register */
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#define CXD56_SDHCI_IRQSIGEN_OFFSET (0x0038) /* Interrupt Signal Enable Register */
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#define CXD56_SDHCI_AC12ERR_OFFSET (0x003c) /* Auto CMD12 Error Status Register */
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#define CXD56_SDHCI_HTCAPBLT_OFFSET (0x0040) /* Host Controller Capabilities */
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#define CXD56_SDHCI_FEVT_OFFSET (0x0050) /* Force Event Register */
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#define CXD56_SDHCI_ADMAES_OFFSET (0x0054) /* ADMA Error Status Register */
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#define CXD56_SDHCI_ADSADDR_OFFSET (0x0058) /* ADMA System Address Register */
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#define CXD56_SDHCI_HOSTVER_OFFSET (0x00fc) /* Host Controller Version */
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#define CXD56_SDHCI_VENDSPEC_OFFSET (0x0110) /* Vender Specific Control */
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#define CXD56_SDHCI_OTHERIOLL_OFFSET (0x021C) /* IO Pin Control */
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#define CXD56_SDHCI_USERDEF1CTL_OFFSET (0x0270) /* User Define1 Control Register */
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#define CXD56_SDHCI_USERDEF2CTL_OFFSET (0x0274) /* User Define2 Control Register */
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/* Register Addresses *******************************************************/
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#define CXD56_SDHCI_BASE CXD56_SDIO_BASE
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#define CXD56_SDHCI_DSADDR (CXD56_SDHCI_BASE+CXD56_SDHCI_DSADDR_OFFSET)
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#define CXD56_SDHCI_BLKATTR (CXD56_SDHCI_BASE+CXD56_SDHCI_BLKATTR_OFFSET)
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#define CXD56_SDHCI_CMDARG (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDARG_OFFSET)
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#define CXD56_SDHCI_XFERTYP (CXD56_SDHCI_BASE+CXD56_SDHCI_XFERTYP_OFFSET)
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#define CXD56_SDHCI_CMDRSP0 (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP0_OFFSET)
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#define CXD56_SDHCI_CMDRSP1 (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP1_OFFSET)
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#define CXD56_SDHCI_CMDRSP2 (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP2_OFFSET)
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#define CXD56_SDHCI_CMDRSP3 (CXD56_SDHCI_BASE+CXD56_SDHCI_CMDRSP3_OFFSET)
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#define CXD56_SDHCI_DATPORT (CXD56_SDHCI_BASE+CXD56_SDHCI_DATPORT_OFFSET)
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#define CXD56_SDHCI_PRSSTAT (CXD56_SDHCI_BASE+CXD56_SDHCI_PRSSTAT_OFFSET)
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#define CXD56_SDHCI_PROCTL (CXD56_SDHCI_BASE+CXD56_SDHCI_PROCTL_OFFSET)
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#define CXD56_SDHCI_SYSCTL (CXD56_SDHCI_BASE+CXD56_SDHCI_SYSCTL_OFFSET)
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#define CXD56_SDHCI_IRQSTAT (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSTAT_OFFSET)
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#define CXD56_SDHCI_IRQSTATEN (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSTATEN_OFFSET)
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#define CXD56_SDHCI_IRQSIGEN (CXD56_SDHCI_BASE+CXD56_SDHCI_IRQSIGEN_OFFSET)
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#define CXD56_SDHCI_AC12ERR (CXD56_SDHCI_BASE+CXD56_SDHCI_AC12ERR_OFFSET)
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#define CXD56_SDHCI_HTCAPBLT (CXD56_SDHCI_BASE+CXD56_SDHCI_HTCAPBLT_OFFSET)
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#define CXD56_SDHCI_FEVT (CXD56_SDHCI_BASE+CXD56_SDHCI_FEVT_OFFSET)
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#define CXD56_SDHCI_ADMAES (CXD56_SDHCI_BASE+CXD56_SDHCI_ADMAES_OFFSET)
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#define CXD56_SDHCI_ADSADDR (CXD56_SDHCI_BASE+CXD56_SDHCI_ADSADDR_OFFSET)
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#define CXD56_SDHCI_HOSTVER (CXD56_SDHCI_BASE+CXD56_SDHCI_HOSTVER_OFFSET)
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#define CXD56_SDHCI_VENDSPEC (CXD56_SDHCI_BASE+CXD56_SDHCI_VENDSPEC_OFFSET)
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#define CXD56_SDHCI_OTHERIOLL (CXD56_SDHCI_BASE+CXD56_SDHCI_OTHERIOLL_OFFSET)
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#define CXD56_SDHCI_USERDEF1CTL (CXD56_SDHCI_BASE+CXD56_SDHCI_USERDEF1CTL_OFFSET)
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#define CXD56_SDHCI_USERDEF2CTL (CXD56_SDHCI_BASE+CXD56_SDHCI_USERDEF2CTL_OFFSET)
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/* Register Bit Definitions *************************************************/
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/* DMA System Address Register */
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#define SDHCI_DSADDR_SHIFT (1) /* Bits 1-31: DMA System Address */
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#define SDHCI_DSADDR_MASK (0xfffffffe)
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/* Bits 0-1: Reserved */
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/* Block Attributes Register */
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#define SDHCI_BLKATTR_SIZE_SHIFT (0) /* Bits 0-12: Transfer Block Size */
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#define SDHCI_BLKATTR_SIZE_MASK (0x1fff << SDHCI_BLKATTR_SIZE_SHIFT)
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/* Bits 13-15: Reserved */
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#define SDHCI_BLKATTR_CNT_SHIFT (16) /* Bits 16-31: Blocks Count For Current Transfer */
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#define SDHCI_BLKATTR_CNT_MASK (0xffff << SDHCI_BLKATTR_CNT_SHIFT)
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/* Command Argument Register (32-bit cmd/arg data) */
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/* Transfer Type Register */
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#define SDHCI_XFERTYP_DMAEN (1 << 0) /* Bit 0: DMA Enable */
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#define SDHCI_XFERTYP_BCEN (1 << 1) /* Bit 1: Block Count Enable */
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#define SDHCI_XFERTYP_AC12EN (1 << 2) /* Bit 2: Auto CMD12 Enable */
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/* Bit 3: Reserved */
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#define SDHCI_XFERTYP_DTDSEL (1 << 4) /* Bit 4: Data Transfer Direction Select */
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#define SDHCI_XFERTYP_MSBSEL (1 << 5) /* Bit 5: Multi/Single Block Select */
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/* Bits 6-15: Reserved */
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#define SDHCI_XFERTYP_RSPTYP_SHIFT (16) /* Bits 16-17: Response Type Select */
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#define SDHCI_XFERTYP_RSPTYP_MASK (3 << SDHCI_XFERTYP_RSPTYP_SHIFT)
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# define SDHCI_XFERTYP_RSPTYP_NONE (0 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* No response */
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# define SDHCI_XFERTYP_RSPTYP_LEN136 (1 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 136 */
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# define SDHCI_XFERTYP_RSPTYP_LEN48 (2 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48 */
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# define SDHCI_XFERTYP_RSPTYP_LEN48BSY (3 << SDHCI_XFERTYP_RSPTYP_SHIFT) /* Response length 48, check busy */
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/* Bit 18: Reserved */
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#define SDHCI_XFERTYP_CCCEN (1 << 19) /* Bit 19: Command CRC Check Enable */
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#define SDHCI_XFERTYP_CICEN (1 << 20) /* Bit 20: Command Index Check Enable */
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#define SDHCI_XFERTYP_DPSEL (1 << 21) /* Bit 21: Data Present Select */
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#define SDHCI_XFERTYP_CMDTYP_SHIFT (22) /* Bits 22-23: Command Type */
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#define SDHCI_XFERTYP_CMDTYP_MASK (3 << SDHCI_XFERTYP_CMDTYP_SHIFT)
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# define SDHCI_XFERTYP_CMDTYP_NORMAL (0 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Normal other commands */
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# define SDHCI_XFERTYP_CMDTYP_SUSPEND (1 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Suspend CMD52 for writing bus suspend in CCCR */
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# define SDHCI_XFERTYP_CMDTYP_RESUME (2 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Resume CMD52 for writing function select in CCCR */
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# define SDHCI_XFERTYP_CMDTYP_ABORT (3 << SDHCI_XFERTYP_CMDTYP_SHIFT) /* Abort CMD12, CMD52 for writing I/O abort in CCCR */
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#define SDHCI_XFERTYP_CMDINX_SHIFT (24) /* Bits 24-29: Command Index */
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#define SDHCI_XFERTYP_CMDINX_MASK (63 << SDHCI_XFERTYP_CMDINX_SHIFT)
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/* Bits 30-31: Reserved */
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/* Command Response 0-3 (32-bit response data) */
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/* Buffer Data Port Register (32-bit data content) */
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/* Present State Register */
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#define SDHCI_PRSSTAT_CIHB (1 << 0) /* Bit 0: Command Inhibit (CMD) */
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#define SDHCI_PRSSTAT_CDIHB (1 << 1) /* Bit 1: Command Inhibit (DAT) */
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#define SDHCI_PRSSTAT_DLA (1 << 2) /* Bit 2: Data Line Active */
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#define SDHCI_PRSSTAT_SDSTB (1 << 3) /* Bit 3: SD Clock Stable */
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#define SDHCI_PRSSTAT_IPGOFF (1 << 4) /* Bit 4: Bus Clock */
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#define SDHCI_PRSSTAT_HCKOFF (1 << 5) /* Bit 5: System Clock */
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#define SDHCI_PRSSTAT_PEROFF (1 << 6) /* Bit 6: SDHC clock */
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#define SDHCI_PRSSTAT_SDOFF (1 << 7) /* Bit 7: SD Clock Gated Off Internally */
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#define SDHCI_PRSSTAT_WTA (1 << 8) /* Bit 8: Write Transfer Active */
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#define SDHCI_PRSSTAT_RTA (1 << 9) /* Bit 9: Read Transfer Active */
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#define SDHCI_PRSSTAT_BWEN (1 << 10) /* Bit 10: Buffer Write Enable */
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#define SDHCI_PRSSTAT_BREN (1 << 11) /* Bit 11: Buffer Read Enable */
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/* Bits 12-15: Reserved */
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#define SDHCI_PRSSTAT_CINS (1 << 16) /* Bit 16: Card Inserted */
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#define SDHCI_PRSSTAT_CSTS (1 << 17) /* Bit 17: Card State Stable */
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#define SDHCI_PRSSTAT_SDCD (1 << 18) /* Bit 18: Card Detect Pin Level */
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#define SDHCI_PRSSTAT_SDWPN (1 << 19) /* Bit 19: Write Protect Switch Pin Level*/
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#define SDHCI_PRSSTAT_DLSL_SHIFT (20) /* Bits 20-23: DAT Line Signal Level */
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#define SDHCI_PRSSTAT_DLSL_MASK (0xf << SDHCI_PRSSTAT_DLSL_SHIFT)
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# define SDHCI_PRSSTAT_DLSL_DAT0 (0x1 << SDHCI_PRSSTAT_DLSL_SHIFT)
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# define SDHCI_PRSSTAT_DLSL_DAT1 (0x2 << SDHCI_PRSSTAT_DLSL_SHIFT)
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# define SDHCI_PRSSTAT_DLSL_DAT2 (0x4 << SDHCI_PRSSTAT_DLSL_SHIFT)
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# define SDHCI_PRSSTAT_DLSL_DAT3 (0x8 << SDHCI_PRSSTAT_DLSL_SHIFT)
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#define SDHCI_PRSSTAT_CLSL (1 << 24) /* Bit 23: CMD Line Signal Level */
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/* Protocol Control Register */
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#define SDHCI_PROCTL_LCTL (1 << 0) /* Bit 0: LED Control */
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#define SDHCI_PROCTL_DTW_SHIFT (1) /* Bits 1-2: Data Transfer Width */
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#define SDHCI_PROCTL_DTW_MASK (1 << SDHCI_PROCTL_DTW_SHIFT)
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||||
# define SDHCI_PROCTL_DTW_1BIT (0 << SDHCI_PROCTL_DTW_SHIFT) /* 1-bit mode */
|
||||
# define SDHCI_PROCTL_DTW_4BIT (1 << SDHCI_PROCTL_DTW_SHIFT) /* 4-bit mode */
|
||||
#define SDHCI_PROCTL_DMAS_SHIFT (3) /* Bits 8-9: DMA Select */
|
||||
#define SDHCI_PROCTL_DMAS_MASK (3 << SDHCI_PROCTL_DMAS_SHIFT)
|
||||
# define SDHCI_PROCTL_DMAS_NODMA (0 << SDHCI_PROCTL_DMAS_SHIFT) /* No DMA or simple DMA is selected */
|
||||
# define SDHCI_PROCTL_DMAS_ADMA2 (2 << SDHCI_PROCTL_DMAS_SHIFT) /* ADMA2 is selected */
|
||||
#define SDHCI_PROCTL_CDTL (1 << 6) /* Bit 6: Card Detect Test Level */
|
||||
#define SDHCI_PROCTL_CDSS (1 << 7) /* Bit 7: Card Detect Signal Selection */
|
||||
/* Bits 10-15: Reserved */
|
||||
#define SDHCI_PROCTL_SABGREQ (1 << 16) /* Bit 16: Stop At Block Gap Request */
|
||||
#define SDHCI_PROCTL_CREQ (1 << 17) /* Bit 17: Continue Request */
|
||||
#define SDHCI_PROCTL_RWCTL (1 << 18) /* Bit 18: Read Wait Control */
|
||||
#define SDHCI_PROCTL_IABG (1 << 19) /* Bit 19: Interrupt At Block Gap */
|
||||
/* Bits 20-23: Reserved */
|
||||
#define SDHCI_PROCTL_WECINT (1 << 24) /* Bit 24: Wakeup Event Enable On Card Interrupt */
|
||||
#define SDHCI_PROCTL_WECINS (1 << 25) /* Bit 25: Wakeup Event Enable On SD Card Insertion */
|
||||
#define SDHCI_PROCTL_WECRM (1 << 26) /* Bit 26: Wakeup Event Enable On SD Card Removal */
|
||||
/* Bits 27-31: Reserved */
|
||||
/* System Control Register */
|
||||
|
||||
#define SDHCI_SYSCTL_ICLKEN (1 << 0) /* Bit 0: Internal Clock Enable */
|
||||
#define SDHCI_SYSCTL_ICLKSTA (1 << 1) /* Bit 1: Internal Clock Stable */
|
||||
#define SDHCI_SYSCTL_SDCLKEN (1 << 2) /* Bit 2: SD Clock Enable */
|
||||
#define SDHCI_SYSCTL_GENSEL (1 << 5) /* Bit 5: Clock Generetor Select */
|
||||
#define SDHCI_SYSCTL_SDCLKFSUP_SHIFT (6) /* Bits 6-7: Divisor */
|
||||
#define SDHCI_SYSCTL_SDCLKFSUP_MASK (3 << SDHCI_SYSCTL_SDCLKFSUP_SHIFT)
|
||||
#define SDHCI_SYSCTL_SDCLKFS_SHIFT (8) /* Bits 8-15: SDCLK Frequency Select */
|
||||
#define SDHCI_SYSCTL_SDCLKFS_MASK (0xff << SDHCI_SYSCTL_SDCLKFS_SHIFT)
|
||||
#define SDHCI_SYSCTL_DTOCV_SHIFT (16) /* Bits 16-19: Data Timeout Counter Value */
|
||||
#define SDHCI_SYSCTL_DTOCV_MASK (0xf << SDHCI_SYSCTL_DTOCV_SHIFT)
|
||||
# define SDHCI_SYSCTL_DTOCV_MUL(n) (((n)-213) << SDHCI_SYSCTL_DTOCV_SHIFT) /* SDCLK x n, n=213..227 */
|
||||
/* Bits 20-23: Reserved */
|
||||
#define SDHCI_SYSCTL_RSTA (1 << 24) /* Bit 24: Software Reset For ALL */
|
||||
#define SDHCI_SYSCTL_RSTC (1 << 25) /* Bit 25: Software Reset For CMD Line */
|
||||
#define SDHCI_SYSCTL_RSTD (1 << 26) /* Bit 26: Software Reset For DAT Line */
|
||||
#define SDHCI_SYSCTL_INITA (1 << 27) /* Bit 27: Initialization Active */
|
||||
/* Bits 28-31: Reserved */
|
||||
/* Interrupt Status Register, Interrupt Status Enable Register, and Interrupt Signal Enable Register
|
||||
* Common interrupt bit definitions
|
||||
*/
|
||||
|
||||
#define SDHCI_INT_CC (1 << 0) /* Bit 0: Command Complete */
|
||||
#define SDHCI_INT_TC (1 << 1) /* Bit 1: Transfer Complete */
|
||||
#define SDHCI_INT_BGE (1 << 2) /* Bit 2: Block Gap Event */
|
||||
#define SDHCI_INT_DINT (1 << 3) /* Bit 3: DMA Interrupt */
|
||||
#define SDHCI_INT_BWR (1 << 4) /* Bit 4: Buffer Write Ready */
|
||||
#define SDHCI_INT_BRR (1 << 5) /* Bit 5: Buffer Read Ready */
|
||||
#define SDHCI_INT_CINS (1 << 6) /* Bit 6: Card Insertion */
|
||||
#define SDHCI_INT_CRM (1 << 7) /* Bit 7: Card Removal */
|
||||
#define SDHCI_INT_CINT (1 << 8) /* Bit 8: Card Interrupt */
|
||||
/* Bits 9-15: Reserved */
|
||||
#define SDHCI_INT_CTOE (1 << 16) /* Bit 16: Command Timeout Error */
|
||||
#define SDHCI_INT_CCE (1 << 17) /* Bit 17: Command CRC Error */
|
||||
#define SDHCI_INT_CEBE (1 << 18) /* Bit 18: Command End Bit Error */
|
||||
#define SDHCI_INT_CIE (1 << 19) /* Bit 19: Command Index Error */
|
||||
#define SDHCI_INT_DTOE (1 << 20) /* Bit 20: Data Timeout Error */
|
||||
#define SDHCI_INT_DCE (1 << 21) /* Bit 21: Data CRC Error */
|
||||
#define SDHCI_INT_DEBE (1 << 22) /* Bit 22: Data End Bit Error */
|
||||
/* Bit 23: Reserved */
|
||||
#define SDHCI_INT_AC12E (1 << 24) /* Bit 24: Auto CMD12 Error */
|
||||
/* Bits 25-27: Reserved */
|
||||
#define SDHCI_INT_DMAE (1 << 28) /* Bit 28: DMA Error */
|
||||
/* Bits 29-31: Reserved */
|
||||
#define SDHCI_INT_ALL 0x117f01ff
|
||||
|
||||
/* Auto CMD12 Error Status Register */
|
||||
|
||||
#define SDHCI_AC12ERR_NE (1 << 0) /* Bit 0: Auto CMD12 Not Executed */
|
||||
#define SDHCI_AC12ERR_TOE (1 << 1) /* Bit 1: Auto CMD12 Timeout Error */
|
||||
#define SDHCI_AC12ERR_EBE (1 << 2) /* Bit 2: Auto CMD12 End Bit Error */
|
||||
#define SDHCI_AC12ERR_CE (1 << 3) /* Bit 3: Auto CMD12 CRC Error */
|
||||
#define SDHCI_AC12ERR_IE (1 << 4) /* Bit 4: Auto CMD12 Index Error */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define SDHCI_AC12ERR_CNI (1 << 7) /* Bit 7: Command Not Issued By Auto CMD12 Error */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Host Controller Capabilities */
|
||||
/* Bits 0-15: Reserved */
|
||||
#define SDHCI_HTCAPBLT_MBL_SHIFT (16) /* Bits 16-18: Max Block Length */
|
||||
#define SDHCI_HTCAPBLT_MBL_MASK (7 << SDHCI_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDHCI_HTCAPBLT_MBL_512BYTES (0 << SDHCI_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDHCI_HTCAPBLT_MBL_1KB (1 << SDHCI_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDHCI_HTCAPBLT_MBL_2KB (2 << SDHCI_HTCAPBLT_MBL_SHIFT)
|
||||
# define SDHCI_HTCAPBLT_MBL_4KB (3 << SDHCI_HTCAPBLT_MBL_SHIFT)
|
||||
/* Bit 19: Reserved */
|
||||
#define SDHCI_HTCAPBLT_ADMAS (1 << 20) /* Bit 20: ADMA Support */
|
||||
#define SDHCI_HTCAPBLT_HSS (1 << 21) /* Bit 21: High Speed Support */
|
||||
#define SDHCI_HTCAPBLT_DMAS (1 << 22) /* Bit 22: DMA Support */
|
||||
#define SDHCI_HTCAPBLT_SRS (1 << 23) /* Bit 23: Suspend/Resume Support */
|
||||
#define SDHCI_HTCAPBLT_VS33 (1 << 24) /* Bit 24: Voltage Support 3.3 V */
|
||||
#define SDHCI_HTCAPBLT_VS30 (1 << 25) /* Bit 25: Voltage Support 3.0 V */
|
||||
#define SDHCI_HTCAPBLT_VS18 (1 << 26) /* Bit 26: Voltage Support 1.8 */
|
||||
/* Bits 27-31: Reserved */
|
||||
/* Force Event Register */
|
||||
|
||||
#define SDHCI_FEVT_AC12NE (1 << 0) /* Bit 0: Force Event Auto Command 12 Not Executed */
|
||||
#define SDHCI_FEVT_AC12TOE (1 << 1) /* Bit 1: Force Event Auto Command 12 Time Out Error */
|
||||
#define SDHCI_FEVT_AC12CE (1 << 2) /* Bit 2: Force Event Auto Command 12 CRC Error */
|
||||
#define SDHCI_FEVT_AC12EBE (1 << 3) /* Bit 3: Force Event Auto Command 12 End Bit Error */
|
||||
#define SDHCI_FEVT_AC12IE (1 << 4) /* Bit 4: Force Event Auto Command 12 Index Error */
|
||||
/* Bits 5-6: Reserved */
|
||||
#define SDHCI_FEVT_CNIBAC12E (1 << 7) /* Bit 7: Force Event Command Not Executed By Auto Command 12 Error */
|
||||
/* Bits 8-15: Reserved */
|
||||
#define SDHCI_FEVT_CTOE (1 << 16) /* Bit 16: Force Event Command Time Out Error */
|
||||
#define SDHCI_FEVT_CCE (1 << 17) /* Bit 17: Force Event Command CRC Error */
|
||||
#define SDHCI_FEVT_CEBE (1 << 18) /* Bit 18: Force Event Command End Bit Error */
|
||||
#define SDHCI_FEVT_CIE (1 << 19) /* Bit 19: Force Event Command Index Error */
|
||||
#define SDHCI_FEVT_DTOE (1 << 20) /* Bit 20: Force Event Data Time Out Error */
|
||||
#define SDHCI_FEVT_DCE (1 << 21) /* Bit 21: Force Event Data CRC Error */
|
||||
#define SDHCI_FEVT_DEBE (1 << 22) /* Bit 22: Force Event Data End Bit Error */
|
||||
/* Bit 23: Reserved */
|
||||
#define SDHCI_FEVT_AC12E (1 << 24) /* Bit 24: Force Event Auto Command 12 Error */
|
||||
/* Bits 25-27: Reserved */
|
||||
#define SDHCI_FEVT_DMAE (1 << 28) /* Bit 28: Force Event DMA Error */
|
||||
/* Bits 29-30: Reserved */
|
||||
#define SDHCI_FEVT_CINT (1 << 31) /* Bit 31: Force Event Card Interrupt */
|
||||
|
||||
/* ADMA Error Status Register */
|
||||
|
||||
#define SDHCI_ADMAES_SHIFT (0) /* Bits 0-1: ADMA Error State (when ADMA Error is occurred) */
|
||||
#define SDHCI_ADMAES_MASK (3 << SDHCI_ADMAES_ADMAES_SHIFT)
|
||||
# define SDHCI_ADMAES_STOP (0 << SDHCI_ADMAES_ADMAES_SHIFT) /* Stop DMA */
|
||||
# define SDHCI_ADMAES_FDS (1 << SDHCI_ADMAES_ADMAES_SHIFT) /* Fetch descriptor */
|
||||
# define SDHCI_ADMAES_CADR (2 << SDHCI_ADMAES_ADMAES_SHIFT) /* Change address */
|
||||
# define SDHCI_ADMAES_TFR (3 << SDHCI_ADMAES_ADMAES_SHIFT) /* Transfer data */
|
||||
#define SDHCI_ADMAES_LME (1 << 2) /* Bit 2: ADMA Length Mismatch Error */
|
||||
#define SDHCI_ADMAES_DCE (1 << 3) /* Bit 3: ADMA Descriptor Error */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* ADMA System Address Register */
|
||||
|
||||
#define SDHCI_ADSADDR_SHIFT (1) /* Bits 1-31: ADMA System Address */
|
||||
#define SDHCI_ADSADDR_MASK (0xfffffffe)
|
||||
/* Bits 0-1: Reserved */
|
||||
|
||||
/* Vendor Specific Register */
|
||||
|
||||
#define SDHCI_VENDOR_EXTDMAEN (1 << 0) /* Bit 0: External DMA Request Enable */
|
||||
#define SDHCI_VENDOR_EXBLKNU (1 << 1) /* Bit 1: Exact block number block read enable for SDIO CMD53 */
|
||||
/* Bits 2-15: Reserved */
|
||||
#define SDHCI_VENDOR_INTSTVAL_SHIFT (16) /* Bits 16-23: Internal State Value */
|
||||
#define SDHCI_VENDOR_INTSTVAL_MASK (0xff << SDHCI_VENDOR_INTSTVAL_SHIFT)
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* User Define1 Control Register */
|
||||
|
||||
#define SDHCI_UDEF1_SDCLKI_SEL (1 << 0)
|
||||
#define SDHCI_UDEF1_SDCLKI_SEL_EXT (1 << 0)
|
||||
#define SDHCI_UDEF1_SDCLKI_SEL_INT (0 << 0)
|
||||
#define SDHCI_UDEF1_SDCLK_SEL (1 << 1)
|
||||
#define SDHCI_UDEF1_SDCLK_SEL_EXT (1 << 1)
|
||||
#define SDHCI_UDEF1_SDCLK_SEL_INT (0 << 1)
|
||||
#define SDHCI_UDEF1_TAP_SEL_SHIFT (4)
|
||||
#define SDHCI_UDEF1_TAP_SEL_MASK (0x1f << SDHCI_UDEF1_TAP_SEL_SHIFT)
|
||||
#define SDHCI_UDEF1_TAP_SEL (1 << 12)
|
||||
#define SDHCI_UDEF1_TAP_SEL_SW (1 << 12)
|
||||
#define SDHCI_UDEF1_TAP_SEL_HW (0 << 12)
|
||||
#define SDHCI_UDEF1_DAT_DLY_BUF (1 << 24)
|
||||
#define SDHCI_UDEF1_DAT_DLY_BUF_ON (1 << 24)
|
||||
#define SDHCI_UDEF1_DAT_DLY_BUF_OFF (0 << 24)
|
||||
|
||||
/* User Define2 Control Register */
|
||||
|
||||
#define SDHCI_UDEF2_CLK_DLY_SHIFT (0)
|
||||
#define SDHCI_UDEF2_CLK_DLY_MASK (0x7 << SDHCI_UDEF2_CLK_DLY_SHIFT)
|
||||
#define SDHCI_UDEF2_CMD_EDGE_DET_ON (1 << 4)
|
||||
#define SDHCI_UDEF2_CMD_EDGE_DET_OFF (0 << 4)
|
||||
#define SDHCI_UDEF2_DAT_DIR_ACT_HI (0x0 << 8)
|
||||
#define SDHCI_UDEF2_DAT_DIR_ACT_LOW (0x7 << 8)
|
||||
#define SDHCI_UDEF2_TTCLK_DIV1 (1 << 16)
|
||||
#define SDHCI_UDEF2_TTCLK_DIV2 (0 << 16)
|
||||
#define SDHCI_UDEF2_CLKI_SEL (1 << 20)
|
||||
#define SDHCI_UDEF2_CLKI_SEL_EXT (1 << 20)
|
||||
#define SDHCI_UDEF2_CLKI_SEL_INT (0 << 20)
|
||||
#define SDHCI_UDEF2_CMD_SEL (1 << 24)
|
||||
#define SDHCI_UDEF2_CMD_SEL_CLKI (1 << 24)
|
||||
#define SDHCI_UDEF2_CMD_SEL_INT (0 << 24)
|
||||
#define SDHCI_UDEF2_FORCE_1p8V_EN (1 << 31)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
struct sdio_dev_s;
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd56_sdhci_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct sdio_dev_s *cxd56_sdhci_initialize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd56_sdhci_finalize
|
||||
*
|
||||
* Description:
|
||||
* Finalize SDIO for operation.
|
||||
*
|
||||
* Input Parameters:
|
||||
* slotno - Not used.
|
||||
*
|
||||
* Returned Values:
|
||||
* A reference to an SDIO interface structure. NULL is returned on failures.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct sdio_dev_s *cxd56_sdhci_finalize(int slotno);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd56_sdhci_mediachange
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic -- posssible from an interrupt handler --
|
||||
* in order to signal to the driver that a card has been inserted or
|
||||
* removed from the slot
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
void cxd56_sdhci_mediachange(FAR struct sdio_dev_s *dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sdio_wrprotect
|
||||
*
|
||||
* Description:
|
||||
* Called by board-specific logic to report if the card in the slot is
|
||||
* mechanically write protected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - An instance of the SDIO driver device state structure.
|
||||
* wrprotect - true is a card is writeprotected.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
void cxd56_sdhci_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_SDHCI_H */
|
||||
3497
arch/arm/src/cxd56xx/cxd56_usbdev.c
Normal file
3497
arch/arm/src/cxd56xx/cxd56_usbdev.c
Normal file
File diff suppressed because it is too large
Load Diff
292
arch/arm/src/cxd56xx/cxd56_usbdev.h
Normal file
292
arch/arm/src/cxd56xx/cxd56_usbdev.h
Normal file
@ -0,0 +1,292 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/cxd56xx/cxd56_usbdev.h
|
||||
*
|
||||
* Copyright (C) 2008-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Copyright 2018 Sony Semiconductor Solutions Corporation
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name of Sony Semiconductor Solutions Corporation nor
|
||||
* the names of its contributors may be used to endorse or promote
|
||||
* products derived from this software without specific prior written
|
||||
* permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
|
||||
#define __ARCH_ARM_SRC_CXD56XX_CXD56_USB_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
/* Common Register Offsets */
|
||||
|
||||
#define CXD56_USB_IN_EP_CONTROL(x) (CXD56_USBDEV_BASE + 0x0000 + ((x) * 0x20))
|
||||
#define CXD56_USB_IN_EP_STATUS(x) (CXD56_USBDEV_BASE + 0x0004 + ((x) * 0x20))
|
||||
#define CXD56_USB_IN_EP_BUFSIZE(x) (CXD56_USBDEV_BASE + 0x0008 + ((x) * 0x20))
|
||||
#define CXD56_USB_IN_EP_MAXPKTSIZE(x) (CXD56_USBDEV_BASE + 0x000c + ((x) * 0x20))
|
||||
#define CXD56_USB_IN_EP_DATADESC(x) (CXD56_USBDEV_BASE + 0x0014 + ((x) * 0x20))
|
||||
|
||||
#define CXD56_USB_OUT_EP_CONTROL(x) (CXD56_USBDEV_BASE + 0x0200 + ((x) * 0x20))
|
||||
#define CXD56_USB_OUT_EP_STATUS(x) (CXD56_USBDEV_BASE + 0x0204 + ((x) * 0x20))
|
||||
#define CXD56_USB_OUT_EP_BUFSIZE(x) (CXD56_USBDEV_BASE + 0x020c + ((x) * 0x20))
|
||||
#define CXD56_USB_OUT_EP_SETUP(x) (CXD56_USBDEV_BASE + 0x0210 + ((x) * 0x20))
|
||||
#define CXD56_USB_OUT_EP_DATADESC(x) (CXD56_USBDEV_BASE + 0x0214 + ((x) * 0x20))
|
||||
|
||||
#define CXD56_USB_DEV_CONFIG (CXD56_USBDEV_BASE + 0x0400)
|
||||
#define CXD56_USB_DEV_CONTROL (CXD56_USBDEV_BASE + 0x0404)
|
||||
#define CXD56_USB_DEV_STATUS (CXD56_USBDEV_BASE + 0x0408)
|
||||
#define CXD56_USB_DEV_INTR (CXD56_USBDEV_BASE + 0x040c)
|
||||
#define CXD56_USB_DEV_INTR_MASK (CXD56_USBDEV_BASE + 0x0410)
|
||||
#define CXD56_USB_DEV_EP_INTR (CXD56_USBDEV_BASE + 0x0414)
|
||||
#define CXD56_USB_DEV_EP_INTR_MASK (CXD56_USBDEV_BASE + 0x0418)
|
||||
|
||||
#define CXD56_USB_DEV_UDC_EP0 (CXD56_USBDEV_BASE + 0x0504)
|
||||
#define CXD56_USB_DEV_UDC_EP1 (CXD56_USBDEV_BASE + 0x0508)
|
||||
#define CXD56_USB_DEV_UDC_EP2 (CXD56_USBDEV_BASE + 0x050c)
|
||||
#define CXD56_USB_DEV_UDC_EP3 (CXD56_USBDEV_BASE + 0x0510)
|
||||
#define CXD56_USB_DEV_UDC_EP4 (CXD56_USBDEV_BASE + 0x0514)
|
||||
#define CXD56_USB_DEV_UDC_EP5 (CXD56_USBDEV_BASE + 0x0518)
|
||||
#define CXD56_USB_DEV_UDC_EP6 (CXD56_USBDEV_BASE + 0x051c)
|
||||
#define CXD56_USB_DEV_UDC_EP(x) (CXD56_USB_DEV_UDC_EP0 + ((x) * 4))
|
||||
|
||||
#define CXD56_USB_SYS_INTR (CXD56_USBDEV_BASE + 0x0800)
|
||||
#define CXD56_USB_SYS_INTR_MASK (CXD56_USBDEV_BASE + 0x0804)
|
||||
#define CXD56_USB_BUSY (CXD56_USBDEV_BASE + 0x0808)
|
||||
#define CXD56_USB_VBUS_CTRL (CXD56_USBDEV_BASE + 0x080c)
|
||||
#define CXD56_USB_RESET (CXD56_USBDEV_BASE + 0x0810)
|
||||
|
||||
#define CXD56_USB_SUSPEND_MASK (CXD56_USBDEV_BASE + 0x081c)
|
||||
|
||||
#define CXD56_USB_PJ_DEMAND (CXD56_USBDEV_BASE + 0x0830)
|
||||
|
||||
#define CXD56_USB_PHY_CONFIG0 (CXD56_USBDEV_BASE + 0x083c)
|
||||
#define CXD56_USB_PHY_CONFIG1 (CXD56_USBDEV_BASE + 0x0840)
|
||||
#define CXD56_USB_PHY_CONFIG2 (CXD56_USBDEV_BASE + 0x0844)
|
||||
|
||||
/* EP types */
|
||||
|
||||
#define USB_EP_CONTROL 0
|
||||
#define USB_EP_ISOCHRONOUS 1
|
||||
#define USB_EP_BULK 2
|
||||
#define USB_EP_INTERRUPT 3
|
||||
|
||||
/* EP control bits */
|
||||
|
||||
#define USB_MRXFLUSH (1<<12)
|
||||
#define USB_CLOSEDESC (1<<11)
|
||||
#define USB_SENDNULL (1<<10)
|
||||
#define USB_RRDY (1<<9)
|
||||
#define USB_CNAK (1<<8)
|
||||
#define USB_SNAK (1<<7)
|
||||
#define USB_NAK (1<<6)
|
||||
#define USB_ET(x) ((x)<<4)
|
||||
#define USB_P (1<<3)
|
||||
#define USB_SN (1<<2)
|
||||
#define USB_F (1<<1)
|
||||
#define USB_STALL (1<<0)
|
||||
|
||||
/* USB device configuration */
|
||||
|
||||
#define USB_CONFIG_DDR (1<<19)
|
||||
#define USB_CONFIG_SET_DESC (1<<18)
|
||||
#define USB_CONFIG_CSR_PRG (1<<17)
|
||||
#define USB_CONFIG_HALT_STATUS (1<<16)
|
||||
#define USB_CONFIG_HS_TIMEOUT_CALIB(x) (((x)&7)<<13)
|
||||
#define USB_CONFIG_FS_TIMEOUT_CALIB(x) (((x)&7)<<10)
|
||||
#define USB_CONFIG_PHY_ERROR_DETECT (1<<9)
|
||||
#define USB_CONFIG_STATUS_1 (1<<8)
|
||||
#define USB_CONFIG_STATUS (1<<7)
|
||||
#define USB_CONFIG_DIR (1<<6)
|
||||
#define USB_CONFIG_PI (1<<5)
|
||||
#define USB_CONFIG_SS (1<<4)
|
||||
#define USB_CONFIG_SP (1<<3)
|
||||
#define USB_CONFIG_RWKP (1<<2)
|
||||
#define USB_CONFIG_SPD(x) (((x)&3))
|
||||
#define USB_CONFIG_HS 0
|
||||
#define USB_CONFIG_FS 1
|
||||
#define USB_CONFIG_SPD_MASK 3
|
||||
|
||||
/* USB device control */
|
||||
|
||||
#define USB_CTRL_THLEN(x) (((x)&0xff)<<24)
|
||||
#define USB_CTRL_BRLEN(x) (((x)&0xff)<<16)
|
||||
#define USB_CTRL_SRXFLUSH (1<<14)
|
||||
#define USB_CTRL_CSR_DONE (1<<13)
|
||||
#define USB_CTRL_DEVNAK (1<<12)
|
||||
#define USB_CTRL_SCALE (1<<11)
|
||||
#define USB_CTRL_SD (1<<10)
|
||||
#define USB_CTRL_MODE (1<<9)
|
||||
#define USB_CTRL_BREN (1<<8)
|
||||
#define USB_CTRL_THE (1<<7)
|
||||
#define USB_CTRL_BF (1<<6)
|
||||
#define USB_CTRL_BE (1<<5)
|
||||
#define USB_CTRL_DU (1<<4)
|
||||
#define USB_CTRL_TDE (1<<3)
|
||||
#define USB_CTRL_RDE (1<<2)
|
||||
#define USB_CTRL_RES (1<<0)
|
||||
|
||||
/* USB device status bits */
|
||||
|
||||
#define USB_STATUS_RMTWKP_STATE (1<<17)
|
||||
#define USB_STATUS_PHYERROR (1<<16)
|
||||
#define USB_STATUS_RXFIFOEMPTY (1<<15)
|
||||
#define USB_STATUS_SPD_SHIFT 13
|
||||
#define USB_STATUS_SPD_MASK (3<<USB_STATUS_SPD_SHIFT)
|
||||
#define USB_STATUS_SPD(x) (((x) & USB_STATUS_SPD_MASK) >> USB_STATUS_SPD_SHIFT)
|
||||
#define USB_STATUS_SUSP (1<<12)
|
||||
#define USB_STATUS_ALT(x) (((x)>>8)&0xf)
|
||||
#define USB_STATUS_INTF(x) (((x)>>4)&0xf)
|
||||
#define USB_STATUS_CFG(x) (((x)>>0)&0xf)
|
||||
|
||||
/* USB device interrupt bits */
|
||||
|
||||
#define USB_INT_RMTWKP_STATE (1<<7)
|
||||
#define USB_INT_ENUM (1<<6)
|
||||
#define USB_INT_SOF (1<<5)
|
||||
#define USB_INT_US (1<<4)
|
||||
#define USB_INT_UR (1<<3)
|
||||
#define USB_INT_ES (1<<2)
|
||||
#define USB_INT_SI (1<<1)
|
||||
#define USB_INT_SC (1<<0)
|
||||
|
||||
/* USB system interrupt bits */
|
||||
|
||||
#define USB_INT_VBUS_DISC (1<<3)
|
||||
#define USB_INT_VBUS_CONN (1<<2)
|
||||
#define USB_INT_RESUME (1<<1)
|
||||
#define USB_INT_READY (1<<0)
|
||||
|
||||
/* USB endpoint interrupt bits */
|
||||
|
||||
#define USB_INT_CDC_CLEAR (1<<28) /* */
|
||||
#define USB_INT_XFERDONE (1<<27) /* Tfansfer Done/Transmit FIFO Empty */
|
||||
#define USB_INT_RSS (1<<26) /* Recieved Set Stall Indication */
|
||||
#define USB_INT_RCS (1<<25) /* Received Clear Stall Indication */
|
||||
#define USB_INT_TXEMPTY (1<<24) /* Transmit FIFO Empty */
|
||||
#define USB_INT_ISO_IN_DONE (1<<23) /* Isochronous IN transaction for the current microframe is complete */
|
||||
#define USB_INT_RX_PKT_SIZE(x) (((x)>>11)&0xfff) /* Receive Packet Size */
|
||||
#define USB_INT_TDC (1<<10) /* Transmit DMA Completion */
|
||||
#define USB_INT_HE (1<<9) /* Error response on the host bus */
|
||||
#define USB_INT_MRXFIFOEMPTY (1<<8) /* Receive Address FIFO Empty Status */
|
||||
#define USB_INT_BNA (1<<7) /* Buffer Not Available */
|
||||
#define USB_INT_IN (1<<6) /* IN token has been received */
|
||||
#define USB_INT_OUT(x) ((x) & (3 << 4)) /* OUT packet has been received. */
|
||||
#define USB_INT_OUT_DATA (1 << 4)
|
||||
#define USB_INT_OUT_SETUP (2 << 4)
|
||||
|
||||
/* PHY Configuration 0 bits */
|
||||
|
||||
#define PHY_STAGSELECT (1u<<31)
|
||||
#define PHY_SHORTCKT_PROT (1u<<30)
|
||||
#define PHY_HSFALLCNTRL (1u<<29)
|
||||
#define PHY_HSRXOFFSET(x) (((x)&3)<<27)
|
||||
#define PHY_HSRXEQUALIZE (1u<<26)
|
||||
#define PHY_INSQUETUNE(x) (((x)&3)<<24)
|
||||
#define PHY_ZHSDRV(x) (((x)&3)<<22)
|
||||
#define PHY_IHSTX(x) (((x)&0xf)<<18)
|
||||
#define PHY_INHSRFRED (1u<<17)
|
||||
#define PHY_INFSRFCNTL (1u<<16)
|
||||
#define PHY_INHSIPLUSENABLE (1u<<15)
|
||||
#define PHY_INHSIPLUS (1u<<14)
|
||||
#define PHY_INHSIMINUS (1u<<13)
|
||||
#define PHY_INHSDRVSLEW (1u<<12)
|
||||
#define PHY_INLFSFBCAP (1u<<11)
|
||||
#define PHY_INTRCC1MA (1u<<10)
|
||||
#define PHY_INCURRENTENABLE (1u<<9)
|
||||
#define PHY_INAFETRIM(x) ((x)&0x1ff)
|
||||
|
||||
/* PHY Configuration 1 bits */
|
||||
|
||||
#define PHY_STRB_BYPASS (1u<<31)
|
||||
#define PHY_STRB (1u<<30)
|
||||
#define PHY_DITHER_DISABLE_RECT (1u<<29)
|
||||
#define PHY_DITHER_DISABLE_TRI (1u<<28)
|
||||
#define PHY_FRAC_CONTROL (1u<<27)
|
||||
#define PHY_PLLENABLE (1u<<26)
|
||||
#define PHY_FRAC_INPUT(x) (((x)&0xffff)<<10)
|
||||
#define PHY_ODF(x) (((x)&0x7)<<7)
|
||||
#define PHY_NDIV(x) ((x)&0x3f)
|
||||
|
||||
/* DMA descriptor status bits */
|
||||
|
||||
#define DESC_BS_SHIFT 30
|
||||
#define DESC_BS_MASK (3 << DESC_BS_SHIFT)
|
||||
#define DESC_BS_HOST_READY (0 << DESC_BS_SHIFT)
|
||||
#define DESC_BS_DMA_BUSY (1 << DESC_BS_SHIFT)
|
||||
#define DESC_BS_DMA_DONE (2 << DESC_BS_SHIFT)
|
||||
#define DESC_BS_HOST_BUSY (3 << DESC_BS_SHIFT)
|
||||
#define IS_BS_HOST_READY(desc) (((desc)->status & DESC_BS_MASK) == DESC_BS_HOST_READY)
|
||||
#define IS_BS_DMA_BUSY(desc) (((desc)->status & DESC_BS_MASK) == DESC_BS_DMA_BUSY)
|
||||
#define IS_BS_DMA_DONE(desc) (((desc)->status & DESC_BS_MASK) == DESC_BS_DMA_DONE)
|
||||
#define IS_BS_HOST_BUSY(desc) (((desc)->status & DESC_BS_MASK) == DESC_BS_HOST_BUSY)
|
||||
|
||||
/* There is same definitions for TX/RX */
|
||||
|
||||
#define DESC_STS_SHIFT 28
|
||||
#define DESC_STS_MASK (3 << DESC_STS_SHIFT)
|
||||
#define DESC_STS_SUCCESS (0 << DESC_STS_SHIFT)
|
||||
#define DESC_STS_DESERR (1 << DESC_STS_SHIFT)
|
||||
#define DESC_STS_BUFERR (3 << DESC_STS_SHIFT)
|
||||
#define IS_STS_SUCCESS(desc) (((desc)->status & DESC_STS_MASK) == DESC_STS_SUCCESS)
|
||||
#define IS_STS_DESERR(desc) (((desc)->status & DESC_STS_MASK) == DESC_STS_DESERR)
|
||||
#define IS_STS_BUFERR(desc) (((desc)->status & DESC_STS_MASK) == DESC_STS_BUFERR)
|
||||
|
||||
#define DESC_LAST (1 << 27)
|
||||
|
||||
#define DESC_SIZE_MASK (0xffff)
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd56_usbdev_setsigno
|
||||
*
|
||||
* Description:
|
||||
* cxd56xx usb device driver attach / detach event signal
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int cxd56_usbdev_setsigno(int signo);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cxd56_usbdev_procfs_register
|
||||
*
|
||||
* Description:
|
||||
* Register the usbdev procfs file system entry
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS_REGISTER
|
||||
int cxd56_usbdev_procfs_register(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_USBDEV_H */
|
||||
Loading…
Reference in New Issue
Block a user