Corrections for LP17xx UARTs and Nucleus 2G

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4331 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lpc17xx/lpc17_serial.c

@@ -314,7 +314,7 @@ static uart_dev_t g_uart3port =
 #  elif defined(CONFIG_UART1_SERIAL_CONSOLE)
 #    define CONSOLE_DEV     g_uart1port     /* UART1=console */
 #    define TTYS0_DEV       g_uart1port     /* UART1=ttyS0 */
-#    ifdef CONFIG_LPC17_UART
+#    ifdef CONFIG_LPC17_UART0
 #      define TTYS1_DEV     g_uart0port     /* UART1=ttyS0;UART0=ttyS1 */
 #      ifdef CONFIG_LPC17_UART2
 #        define TTYS2_DEV   g_uart2port     /* UART1=ttyS0;UART0=ttyS1;UART2=ttyS2 */
@@ -353,7 +353,7 @@ static uart_dev_t g_uart3port =
 #  elif defined(CONFIG_UART2_SERIAL_CONSOLE)
 #    define CONSOLE_DEV     g_uart2port     /* UART2=console */
 #    define TTYS0_DEV       g_uart2port     /* UART2=ttyS0 */
-#    ifdef CONFIG_LPC17_UART
+#    ifdef CONFIG_LPC17_UART2
 #      define TTYS1_DEV     g_uart0port     /* UART2=ttyS0;UART0=ttyS1 */
 #      ifdef CONFIG_LPC17_UART1
 #        define TTYS2_DEV   g_uart1port     /* UART2=ttyS0;UART0=ttyS1;UART1=ttyS2 */
@@ -392,7 +392,7 @@ static uart_dev_t g_uart3port =
 #  elif defined(CONFIG_UART3_SERIAL_CONSOLE)
 #    define CONSOLE_DEV     g_uart3port    /* UART3=console */
 #    define TTYS0_DEV       g_uart3port    /* UART3=ttyS0 */
-#    ifdef CONFIG_LPC17_UART
+#    ifdef CONFIG_LPC17_UART0
 #      define TTYS1_DEV     g_uart0port    /* UART3=ttyS0;UART0=ttyS1 */
 #      ifdef CONFIG_LPC17_UART1
 #        define TTYS2_DEV   g_uart1port    /* UART3=ttyS0;UART0=ttyS1;UART1=ttyS2 */

configs/nucleus2g/include/board.h

@@ -2,8 +2,8 @@
  * configs/nucleus2g/include/board.h
  * include/arch/board/board.h
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -167,8 +167,8 @@
 
 /* UART3 -- Not connected */
 
-#define GPIO_UART3_TXD             GPIO_UART3_TXD_1
-#define GPIO_UART3_RXD             GPIO_UART3_RXD_1
+#define GPIO_UART3_TXD             GPIO_UART3_TXD_3
+#define GPIO_UART3_RXD             GPIO_UART3_RXD_3
 
 /* Either SPI or SSP0 can drive the MMC/SD slot (SSP0 alternate pin settings are
  * not connected)
@@ -183,6 +183,26 @@
 
 #define GPIO_SSP1_SCK              GPIO_SSP1_SCK_1
 
+/* Can bus config */
+
+/* CAN1 GPIO                        PIN  SIGNAL NAME
+ * -------------------------------- ---- --------------
+ * P0[0]/RD1/TXD3/SDA1               46  RD1
+ * P0[1]/TD1/RXD3/SCL1               47  TD1
+ */
+
+#define GPIO_CAN1_RD  GPIO_CAN1_RD_1
+#define GPIO_CAN1_TD  GPIO_CAN1_TD_1
+
+/* Suppy default CAN BAUD (can be overridden in the .config file) */
+
+#ifndef CONFIG_CAN1_BAUD
+#  define CONFIG_CAN1_BAUD 1000000
+#endif
+#ifndef CONFIG_CAN2_BAUD
+#  define CONFIG_CAN2_BAUD 1000000
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/

configs/nucleus2g/src/Makefile

@@ -38,7 +38,7 @@
 CFLAGS		+= -I$(TOPDIR)/sched
 
 ASRCS		= 
-CSRCS		= up_boot.c up_leds.c up_ssp.c
+CSRCS		= up_boot.c up_leds.c up_ssp.c up_outputs.c
 ifeq ($(CONFIG_NSH_ARCHINIT),y)
 CSRCS		+= up_nsh.c
 endif

configs/nucleus2g/src/nucleus2g_internal.h

@@ -2,8 +2,8 @@
  * configs/nucleus2g/src/nucleus2g_internal.h
  * arch/arm/src/board/nucleus2g_internal.n
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions

configs/nucleus2g/src/up_boot.c

@@ -2,8 +2,8 @@
  * configs/nucleus2g/src/up_boot.c
  * arch/arm/src/board/up_boot.c
  *
- *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *   Copyright (C) 2010, 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions

configs/nucleus2g/src/up_outputs.c

@@ -0,0 +1,129 @@
+/****************************************************************************
+ * configs/nucleus2g/src/up_outputs.c
+ * arch/arm/src/board/up_outputs.c
+ *
+ *   Copyright (C) 2012 Hal Glenn. All rights reserved.
+ *   Author: Hal Glenn <hglenn@2g-eng.com>
+ *
+ * This file is part of NuttX:
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "lpc17_internal.h"
+
+#include "nucleus2g_internal.h"
+
+#ifdef CONFIG_ARCH_BOARD_NUCLEUS2G_BMS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+ 
+/****************************************************************************
+ * Name: nucleus_bms_relay 1-4
+ *
+ * Description:
+ *   Once booted these functions control the 4 isolated FET outputs from the
+ *   master BMS controller
+ *
+ ***************************************************************************/
+ 
+void nucleus_bms_relay1(enum output_state state)
+{
+  bool value   = (state == (enum output_state)RELAY_OPEN);
+  lpc17_gpiowrite(NUCLEUS_BMS_RELAY1, value);
+}
+
+void nucleus_bms_relay2(enum output_state state)
+{
+  bool value   = (state == (enum output_state)RELAY_OPEN);
+  lpc17_gpiowrite(NUCLEUS_BMS_RELAY2, value);
+}
+
+void nucleus_bms_relay3(enum output_state state)
+{
+  bool value   = (state == (enum output_state)RELAY_OPEN);
+  lpc17_gpiowrite(NUCLEUS_BMS_RELAY3, value);
+}
+
+void nucleus_bms_relay4(enum output_state state)
+{
+  bool value   = (state == (enum output_state)RELAY_OPEN);
+  lpc17_gpiowrite(NUCLEUS_BMS_RELAY4, value);
+}
+
+/***************************************************************************
+ * Name: up_relayinit
+ *
+ * Description:
+ *  This function is called on boot to init the GPIO for relay control
+ *
+ ***************************************************************************/
+
+void up_relayinit(void)
+{
+  lpc17_configgpio(NUCLEUS_BMS_RELAY1);
+  lpc17_configgpio(NUCLEUS_BMS_RELAY2);
+  lpc17_configgpio(NUCLEUS_BMS_RELAY3);
+  lpc17_configgpio(NUCLEUS_BMS_RELAY4);
+}
+
+#endif /* CONFIG_ARCH_BOARD_NUCLEUS2G_BMS */
+

configs/nucleus2g/tools/olimex-tiny.cfg

@@ -0,0 +1,61 @@
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+#interface
+interface ft2232
+ft2232_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ft2232_layout "olimex-jtag"
+ft2232_vid_pid 0x15ba 0x002a
+
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+	set  _CHIPNAME $CHIPNAME
+} else {
+	set  _CHIPNAME lpc1768
+}
+
+if { [info exists ENDIAN] } {
+	set  _ENDIAN $ENDIAN
+} else {
+	set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+
+# REVISIT is there any good reason to have this reset-init event handler??
+# Normally they should set up (board-specific) clocking then probe the flash...
+$_TARGETNAME configure -event reset-init {
+	# Force NVIC.VTOR to point to flash at 0 ...
+	# WHY?  This is it's reset value; we run right after reset!!
+	mwb 0xE000ED08 0x00
+}
+
+# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
+# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 80000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 500