XMC4xxx: Clean up problems associated with USIC initialization. USIC still does not work in UART mode.

This commit is contained in:
Gregory Nutt 2017-03-21 10:55:52 -06:00
parent 1e9bc166d4
commit 21a626878a
4 changed files with 26 additions and 18 deletions

View File

@ -161,6 +161,7 @@ uint32_t xmc4_get_coreclock(void)
uint32_t xmc4_get_periphclock(void)
{
uint32_t periphclock;
uint32_t regval;
/* Get the CPU clock frequency. Unless it is divided down, this also the
* peripheral clock frequency.
@ -170,12 +171,12 @@ uint32_t xmc4_get_periphclock(void)
/* Get the peripheral clock divider */
periphclock = getreg32(XMC4_SCU_PBCLKCR);
if ((periphclock & SCU_PBCLKCR_PBDIV) != 0)
regval = getreg32(XMC4_SCU_PBCLKCR);
if ((regval & SCU_PBCLKCR_PBDIV) != 0)
{
/* The peripheral clock is fCPU/2 */
periphclock <<= 1;
periphclock >>= 1;
}
return periphclock;

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@ -234,7 +234,7 @@ static inline void xmc4_gpio_hwsel(uintptr_t portbase, unsigned int pin,
****************************************************************************/
static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
bool value)
bool enable)
{
uint32_t regval;
uint32_t mask;
@ -243,16 +243,21 @@ static inline void xmc4_gpio_pdisc(uintptr_t portbase, unsigned int pin,
regval = xmc4_gpio_getreg(portbase, XMC4_PORT_PDISC_OFFSET);
/* Set/clear the enable/disable (or analg) value for this field */
/* Set or clear the pin field in the PDISC register.
*
* Disable = set
* Analog = set
* Enable = clear
*/
mask = PORT_PIN(pin);
if (value)
if (enable)
{
regval |= mask;
regval &= ~mask;
}
else
{
regval &= ~mask;
regval |= mask;
}
xmc4_gpio_putreg(portbase, XMC4_PORT_PDISC_OFFSET, regval);

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@ -121,12 +121,12 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_CGAT0_USIC0, XMC4_SCU_CGATCLR0);
/* De-assert peripheral reset USIC0 */
/* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
}
#else
/* De-assert peripheral reset USIC0 */
/* Set bit in PRCLR0 to de-assert USIC0 peripheral reset */
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRCLR0);
#endif
@ -143,12 +143,12 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_CGAT1_USIC1, XMC4_SCU_CGATCLR1);
/* De-assert peripheral reset USIC1 */
/* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
}
#else
/* De-assert peripheral reset USIC1 */
/* Set bit in PRCLR1 to de-assert USIC1 peripheral reset */
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRCLR1);
#endif
@ -165,12 +165,12 @@ int xmc4_enable_usic(enum usic_e usic)
putreg32(SCU_CGAT1_USIC2, XMC4_SCU_CGATCLR1);
/* De-assert peripheral reset USIC2 */
/* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
}
#else
/* De-assert peripheral reset USIC2 */
/* Set bit in PRCLR1 to de-assert USIC2 peripheral reset */
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRCLR1);
#endif
@ -203,7 +203,7 @@ int xmc4_disable_usic(enum usic_e usic)
switch (usic)
{
case USIC0:
/* Assert peripheral reset USIC0 */
/* Set bit in PRSET0 to assert USIC0 peripheral reset */
putreg32(SCU_PR0_USIC0RS, XMC4_SCU_PRSET0);
@ -216,7 +216,7 @@ int xmc4_disable_usic(enum usic_e usic)
#if XMC4_NUSIC > 1
case USIC1:
/* Assert peripheral reset USIC0 */
/* Set bit in PRSET1 to assert USIC1 peripheral reset */
putreg32(SCU_PR1_USIC1RS, XMC4_SCU_PRSET1);
@ -229,7 +229,7 @@ int xmc4_disable_usic(enum usic_e usic)
#if XMC4_NUSIC > 2
case USIC2:
/* Assert peripheral reset USIC0 */
/* Set bit in PRSET1 to assert USIC2 peripheral reset */
putreg32(SCU_PR1_USIC2RS, XMC4_SCU_PRSET1);

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@ -14,11 +14,13 @@ Serial Console
The RX and TX pins is available:
RX - P1.4, Connector X2, pin 17
TX - P1.5, Connector X2, pin 17
TX - P1.5, Connector X2, pin 16
GND - Available on pins 1-4 of either connector X1 or X2
VDD3.3 - Available on pins 37-38 of either connector X1 or X2
VDD5 - Available on pins 39-40 of either connector X1 or X2
A TTL to RS-232 convertor or a USB TTL-to-USB serial adaptor is required.
LEDs
====