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Beginnings of support for the STM32F3Discovery board

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5616 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-02-06 22:30:57 +00:00
parent bc69dc2c5a
commit 21a6a31fad
9 changed files with 852 additions and 31 deletions
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288
arch/arm/include/stm32/chip.h
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@ -67,6 +67,7 @@
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
@ -97,6 +98,7 @@
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
@ -130,6 +132,7 @@
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
@ -161,6 +164,7 @@
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
@ -189,33 +193,34 @@
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F103RBT6)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */
# define STM32_NDMA 1 /* DMA1 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* General timers TIM2,3,4 */
# define STM32_NBTIM 0 /* Two basic timers TIM6 and TIM7 */
# define STM32_NDMA 1 /* DMA1 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 1 /* bxCAN1 */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 51 /* GPIOA-E */
# define STM32_NADC 2 /* ADC1-2 */
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F103 High Density Family ***************************************************/
/* STM32F103RC, STM32F103RD, and STM32F103RE are all provided in 64 pin packages and
@ -230,6 +235,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
@ -263,6 +269,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and TIM8 */
@ -296,6 +303,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
@ -326,6 +334,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
@ -355,6 +364,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timers TIM1 */
@ -385,6 +395,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -408,6 +419,220 @@
# define STM32_NRNG 1 /* Random number generator (RNG) */
# define STM32_NDCMI 1 /* Digital camera interface (DCMI) */
/* STM23 F3 Family ******************************************************************/
/* Part Numbering: STM32Fssscfxxx
*
* Where
* sss = 302 or 303
* c = C (48pins) R (68 pins) V (100 pins)
* f = B (128KB FLASH), C (256KB FLASH)
* xxx = Package, temperature range, options (ignored here)
*/
#elif defined(CONFIG_ARCH_CHIP_STM32F302CB) || defined(CONFIG_ARCH_CHIP_STM32F302CC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F302RB) || defined(CONFIG_ARCH_CHIP_STM32F302RC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 52 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F302VB) || defined(CONFIG_ARCH_CHIP_STM32F302VC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1 (no TIM8) */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 1 /* (1) Basic timers: TIM6 (no TIM7) */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 0 /* (0) No I2S */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
# define STM32_NADC 2 /* (2) 12-bit ADC1-2 */
# define STM32_NDAC 1 /* (1) 12-bit DAC1 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303CB) || defined(CONFIG_ARCH_CHIP_STM32F303CC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 3 /* (3) No UART1-3, no UARTs */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303RB) || defined(CONFIG_ARCH_CHIP_STM32F303RC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 52 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F303VB) || defined(CONFIG_ARCH_CHIP_STM32F303VC)
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* (2) Advanced 16-bit timers with DMA: TIM1 and TIM8 */
# define STM32_NGTIM 6 /* (2) 16-bit general timers with DMA: TIM3 and TIM4
* (1) 32-bit general timers with DMA: TIM2
* (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
# define STM32_NGTIMNDMA 0 /* All timers have DMA */
# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
# define STM32_NDMA 2 /* (2) DMA1 (7 channels) and DMA2 (5 channels) */
# define STM32_NSPI 3 /* (3) SPI1-3 */
# define STM32_NI2S 2 /* (2) I2S1-2 (multiplexed with SPI2-3) */
# define STM32_NUSART 5 /* (5) USART1-3, UART4-5 */
# define STM32_NI2C 2 /* (2) I2C1-2 */
# define STM32_NCAN 1 /* (1) CAN1 */
# define STM32_NSDIO 0 /* (0) No SDIO */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
/* STM23 F4 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
@ -417,6 +642,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -448,6 +674,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -479,6 +706,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -510,6 +738,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -541,6 +770,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -572,6 +802,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -603,6 +834,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -634,6 +866,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */
@ -665,6 +898,7 @@
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 2 /* Two advanced timers TIM1 and 8 */

2
arch/arm/include/stm32/irq.h
View File

@ -81,6 +81,8 @@
# include <arch/stm32/stm32f10xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F20XX)
# include <arch/stm32/stm32f20xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F30XX)
# include <arch/stm32/stm32f30xxx_irq.h>
#elif defined(CONFIG_STM32_STM32F40XX)
# include <arch/stm32/stm32f40xxx_irq.h>
#else

193
arch/arm/include/stm32/stm32f30xxx_irq.h Normal file
View File

@ -0,0 +1,193 @@
/****************************************************************************************************
* arch/arm/include/stm32s/stm32f30xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************************************/
/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
#ifndef __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H
#define __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H
/****************************************************************************************************
* Included Files
****************************************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************************************
* Definitions
****************************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can be found
* in nuttx/arch/arm/include/stm32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_INTERRUPTS+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_INTERRUPTS+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_INTERRUPTS+2) /* 2: Tamper interrupt, or */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_INTERRUPTS+2) /* 2: Time stamp interrupt */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_INTERRUPTS+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_INTERRUPTS+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_INTERRUPTS+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_INTERRUPTS+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_INTERRUPTS+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_INTERRUPTS+8) /* 8: EXTI Line 2 interrupt, or */
#define STM32_IRQ_TSC (STM32_IRQ_INTERRUPTS+8) /* 8: TSC interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_INTERRUPTS+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_INTERRUPTS+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1CH1 (STM32_IRQ_INTERRUPTS+11) /* 11: DMA1 channel 1 global interrupt */
#define STM32_IRQ_DMA1CH2 (STM32_IRQ_INTERRUPTS+12) /* 12: DMA1 channel 2 global interrupt */
#define STM32_IRQ_DMA1CH3 (STM32_IRQ_INTERRUPTS+13) /* 13: DMA1 channel 3 global interrupt */
#define STM32_IRQ_DMA1CH4 (STM32_IRQ_INTERRUPTS+14) /* 14: DMA1 channel 4 global interrupt */
#define STM32_IRQ_DMA1CH5 (STM32_IRQ_INTERRUPTS+15) /* 15: DMA1 channel 5 global interrupt */
#define STM32_IRQ_DMA1CH6 (STM32_IRQ_INTERRUPTS+16) /* 16: DMA1 channel 6 global interrupt */
#define STM32_IRQ_DMA1CH7 (STM32_IRQ_INTERRUPTS+17) /* 17: DMA1 channel 7 global interrupt */
#define STM32_IRQ_ADC12 (STM32_IRQ_INTERRUPTS+18) /* 18: ADC1/ADC2 global interrupt */
#define STM32_IRQ_USBHP_1 (STM32_IRQ_INTERRUPTS+19) /* 19: USB High Priority interrupts (not remapped) */
#define STM32_IRQ_CAN1TX (STM32_IRQ_INTERRUPTS+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_USBLP_1 (STM32_IRQ_INTERRUPTS+20) /* 20: USB Low Priority interrupt (not remapped) */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_INTERRUPTS+20) /* 20: CAN1 RX0 interrupts*/
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_INTERRUPTS+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_INTERRUPTS+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_INTERRUPTS+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_INTERRUPTS+24) /* 24: TIM1 Break interrupt, or */
#define STM32_IRQ_TIM15 (STM32_IRQ_INTERRUPTS+24) /* 24: TIM15 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_INTERRUPTS+25) /* 25: TIM1 Update interrupt, or */
#define STM32_IRQ_TIM16 (STM32_IRQ_INTERRUPTS+25) /* 25: TIM16 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_INTERRUPTS+26) /* 26: TIM1 Trigger and Commutation interrupts, or */
#define STM32_IRQ_TIM17 (STM32_IRQ_INTERRUPTS+26) /* 26: TIM17 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_INTERRUPTS+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_INTERRUPTS+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_INTERRUPTS+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_INTERRUPTS+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_INTERRUPTS+31) /* 31: I2C1 event interrupt, or */
#define STM32_IRQ_EXTI23 (STM32_IRQ_INTERRUPTS+31) /* 31: EXTI Line23 interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_INTERRUPTS+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_INTERRUPTS+33) /* 33: I2C2 event interrupt, or */
#define STM32_IRQ_EXTI24 (STM32_IRQ_INTERRUPTS+33) /* 33: EXTI Line24 interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_INTERRUPTS+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_INTERRUPTS+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_INTERRUPTS+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_INTERRUPTS+37) /* 37: USART1 global interrupt, or */
#define STM32_IRQ_EXTI25 (STM32_IRQ_INTERRUPTS+37) /* 37: EXTI Line 25 interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_INTERRUPTS+38) /* 38: USART2 global interrupt, or */
#define STM32_IRQ_EXTI26 (STM32_IRQ_INTERRUPTS+38) /* 38: EXTI Line 26 interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_INTERRUPTS+39) /* 39: USART3 global interrupt, or */
#define STM32_IRQ_EXTI28 (STM32_IRQ_INTERRUPTS+39) /* 39: EXTI Line 28 interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_INTERRUPTS+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_INTERRUPTS+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_USBWKUP_1 (STM32_IRQ_INTERRUPTS+42) /* 42: USB wakeup from suspend through EXTI line interrupt */
#define STM32_IRQ_EXT18 (STM32_IRQ_INTERRUPTS+42) /* 42: EXTI Line 18 interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_INTERRUPTS+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_INTERRUPTS+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_INTERRUPTS+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM8CC (STM32_IRQ_INTERRUPTS+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_ADC3 (STM32_IRQ_INTERRUPTS+47) /* 47: ADC3 global interrupt */
#define STM32_IRQ_RESERVED48 (STM32_IRQ_INTERRUPTS+48) /* 48: Reserved */
#define STM32_IRQ_RESERVED49 (STM32_IRQ_INTERRUPTS+49) /* 49: Reserved */
#define STM32_IRQ_RESERVED50 (STM32_IRQ_INTERRUPTS+50) /* 50: Reserved */
#define STM32_IRQ_SPI3 (STM32_IRQ_INTERRUPTS+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_INTERRUPTS+52) /* 52: UART4 global interrupt, or */
#define STM32_IRQ_EXTI34 (STM32_IRQ_INTERRUPTS+52) /* 52: EXTI Line 34 interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_INTERRUPTS+53) /* 53: UART5 global interrupt, or */
#define STM32_IRQ_EXTI35 (STM32_IRQ_INTERRUPTS+53) /* 53: EXTI Line 35 interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_INTERRUPTS+54) /* 54: TIM6 global interrupt, or */
#define STM32_IRQ_DAC (STM32_IRQ_INTERRUPTS+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_INTERRUPTS+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2CH1 (STM32_IRQ_INTERRUPTS+56) /* 56: DMA2 channel 1 global interrupt */
#define STM32_IRQ_DMA2CH2 (STM32_IRQ_INTERRUPTS+57) /* 57: DMA2 channel 2 global interrupt */
#define STM32_IRQ_DMA2CH3 (STM32_IRQ_INTERRUPTS+58) /* 58: DMA2 channel 3 global interrupt */
#define STM32_IRQ_DMA2CH4 (STM32_IRQ_INTERRUPTS+59) /* 59: DMA2 channel 4 global interrupt */
#define STM32_IRQ_DMA2CH5 (STM32_IRQ_INTERRUPTS+60) /* 60: DMA2 channel 5 global interrupt */
#define STM32_IRQ_ADC4 (STM32_IRQ_INTERRUPTS+61) /* 61: ADC4 global interrupt */
#define STM32_IRQ_RESERVED62 (STM32_IRQ_INTERRUPTS+62) /* 62: Reserved */
#define STM32_IRQ_RESERVED63 (STM32_IRQ_INTERRUPTS+63) /* 63: Reserved */
#define STM32_IRQ_COMP123 (STM32_IRQ_INTERRUPTS+64) /* 64: COMP1 & COMP2 & COMP3 interrupts, or */
#define STM32_IRQ_EXTI2129 (STM32_IRQ_INTERRUPTS+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */
#define STM32_IRQ_COMP456 (STM32_IRQ_INTERRUPTS+65) /* 65: COMP4 & COMP5 & COMP6 interrupts, or */
#define STM32_IRQ_EXTI3012 (STM32_IRQ_INTERRUPTS+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
#define STM32_IRQ_COMP7 (STM32_IRQ_INTERRUPTS+66) /* 66: COMP7 interrupt, or */
#define STM32_IRQ_EXTI35 (STM32_IRQ_INTERRUPTS+66) /* 66: EXTI Line 33 interrupt */
#define STM32_IRQ_RESERVED67 (STM32_IRQ_INTERRUPTS+67) /* 67: Reserved */
#define STM32_IRQ_RESERVED68 (STM32_IRQ_INTERRUPTS+68) /* 68: Reserved */
#define STM32_IRQ_RESERVED69 (STM32_IRQ_INTERRUPTS+69) /* 69: Reserved */
#define STM32_IRQ_RESERVED70 (STM32_IRQ_INTERRUPTS+70) /* 70: Reserved */
#define STM32_IRQ_RESERVED71 (STM32_IRQ_INTERRUPTS+71) /* 71: Reserved */
#define STM32_IRQ_RESERVED72 (STM32_IRQ_INTERRUPTS+72) /* 72: Reserved */
#define STM32_IRQ_RESERVED73 (STM32_IRQ_INTERRUPTS+73) /* 73: Reserved */
#define STM32_IRQ_USBHP_2 (STM32_IRQ_INTERRUPTS+74) /* 74: USB High priority interrupt (remapped) */
#define STM32_IRQ_USBLP_2 (STM32_IRQ_INTERRUPTS+75) /* 75: USB Low priority interrupt remapped) */
#define STM32_IRQ_USBWKUP_2 (STM32_IRQ_INTERRUPTS+76) /* 76: USB wakeup from suspend remapped) */
#define STM32_IRQ_RESERVED77 (STM32_IRQ_INTERRUPTS+77) /* 77: Reserved */
#define STM32_IRQ_RESERVED78 (STM32_IRQ_INTERRUPTS+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32_IRQ_INTERRUPTS+79) /* 79: Reserved */
#define STM32_IRQ_RESERVED80 (STM32_IRQ_INTERRUPTS+80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_INTERRUPTS+81) /* 81: FPU global interrupt */
#define NR_IRQS (STM32_IRQ_INTERRUPTS+82)
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/****************************************************************************************************
* Public Data
****************************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C" {
#else
#define EXTERN extern
#endif
/****************************************************************************************************
* Public Functions
****************************************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */

80
arch/arm/src/stm32/Kconfig
View File

@ -128,6 +128,66 @@ config ARCH_CHIP_STM32F207IG
select ARCH_CORTEXM3
select STM32_STM32F20XX
config ARCH_CHIP_STM32F302CB
bool "STM32F302CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F302CC
bool "STM32F302CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F302RB
bool "STM32F302RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F302RC
bool "STM32F302RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F302VB
bool "STM32F302VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F302VC
bool "STM32F302VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303CB
bool "STM32F303CB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303CC
bool "STM32F303CC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303RB
bool "STM32F303RB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303RC
bool "STM32F303RC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303VB
bool "STM32F303VB"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F303VC
bool "STM32F303VC"
select ARCH_CORTEXM4
select STM32_STM32F30XX
config ARCH_CHIP_STM32F405RG
bool "STM32F405RG"
select ARCH_CORTEXM4
@ -190,6 +250,9 @@ config STM32_CONNECTIVITYLINE
config STM32_STM32F20XX
bool
config STM32_STM32F30XX
bool
config STM32_STM32F40XX
bool
@ -220,6 +283,12 @@ config STM32_ADC3
select STM32_ADC
depends on !STM32_VALUELINE
config STM32_ADC4
bool "ADC4"
default n
select STM32_ADC
depends on STM32_STM32F30XX
config STM32_BKP
bool "BKP"
default n
@ -441,17 +510,17 @@ config STM32_TIM14
config STM32_TIM15
bool "TIM15"
default n
depends on STM32_VALUELINE
depends on STM32_VALUELINE || STM32_STM32F30XX
config STM32_TIM16
bool "TIM16"
default n
depends on STM32_VALUELINE
depends on STM32_VALUELINE || STM32_STM32F30XX
config STM32_TIM17
bool "TIM17"
default n
depends on STM32_VALUELINE
depends on STM32_VALUELINE || STM32_STM32F30XX
config STM32_USART1
bool "USART1"
@ -468,18 +537,21 @@ config STM32_USART2
config STM32_USART3
bool "USART3"
default n
depends on !STM32_STM32F30XX
select ARCH_HAVE_USART3
select STM32_USART
config STM32_UART4
bool "UART4"
default n
depends on !STM32_STM32F30XX
select ARCH_HAVE_UART4
select STM32_USART
config STM32_UART5
bool "UART5"
default n
depends on !STM32_STM32F30XX
select ARCH_HAVE_UART5
select STM32_USART
@ -493,7 +565,7 @@ config STM32_USART6
config STM32_USB
bool "USB Device"
default n
depends on STM32_STM32F10XX && !STM32_VALUELINE
depends on (STM32_STM32F10XX && !STM32_VALUELINE) || STM32_STM32F30XX
select USBDEV
config STM32_WWDG

10
arch/arm/src/stm32/chip.h
View File

@ -49,6 +49,7 @@
/* Include the chip pin configuration file */
/* STM32 F1 Family ******************************************************************/
#if defined(CONFIG_STM32_STM32F10XX)
/* STM32F100 Value Line */
@ -89,10 +90,17 @@
# endif
/* STM32 F2 Family ******************************************************************/
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_pinmap.h"
/* STM32 F3 Family ******************************************************************/
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_pinmap.h"
/* STM32 F4 Family ******************************************************************/
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_pinmap.h"
#else
@ -108,6 +116,8 @@
# include "chip/stm32f10xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_vectors.h"
# elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_vectors.h"
# else

2
arch/arm/src/stm32/chip/stm32_memorymap.h
View File

@ -47,6 +47,8 @@
# include "chip/stm32f10xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/stm32f20xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/stm32f30xxx_memorymap.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/stm32f40xxx_memorymap.h"
#else

155
arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h Normal file
View File

@ -0,0 +1,155 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H
#define __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* STM32F40XXX Address Blocks *******************************************************/
#define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define STM32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
/* 0x60000000-0xdfffffff: Reserved */
#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define STM32_REGION_MASK 0xf0000000
#define STM32_IS_SRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
/* Code Base Addresses **************************************************************/
#define STM32_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */
/* 0x00100000-0x07ffffff: Reserved */
#define STM32_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */
/* 0x08100000-0x0fffffff: Reserved */
#define STM32_CCMRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb CCM data RAM */
/* 0x10010000-0x1ffeffff: Reserved */
#define STM32_SYSMEM_BASE 0x1fffd800 /* 0x1fff0000-0x1fff7a0f: System memory */
/* 0x1fff7a10-0x1fff7fff: Reserved */
#define STM32_OPTION_BASE 0x1ffff800 /* 0x1fffc000-0x1fffc007: Option bytes */
/* 0x1fffc008-0x1fffffff: Reserved */
/* Peripheral Base Addresses ********************************************************/
#define STM32_APB1_BASE 0x40000000 /* 0x40000000-0x40009fff: APB1 */
/* 0x4000a000-0x4000ffff: Reserved */
#define STM32_APB2_BASE 0x40010000 /* 0x40010000-0x40006bff: APB2 */
/* 0x40016c00-0x4001ffff: Reserved */
#define STM32_AHB1_BASE 0x40020000 /* 0x40020000-0x400243ff: APB1 */
/* 0x40024400-0x4007ffff: Reserved */
#define STM32_AHB2_BASE 0x48000000 /* 0x48000000-0x480017ff: AHB2 */
/* 0x48001800-0x4fffFfff: Reserved */
#define STM32_AHB3_BASE 0x50000000 /* 0x50000000-0x500007ff: AHB3 */
/* APB1 Base Addresses **************************************************************/
#define STM32_TIM2_BASE 0x40000000 /* 0x40000000-0x400003ff TIM2 */
#define STM32_TIM3_BASE 0x40000400 /* 0x40000400-0x400007ff TIM3 */
#define STM32_TIM4_BASE 0x40000800 /* 0x40000800-0x40000bff TIM4 */
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */
#define STM32_I2S2_BASE 0x40003800 /* 0x40003800-0x40003bff I2S2 */
#define STM32_SPI3_BASE 0x40003c00 /* 0x40003c00-0x40003fff SPI3, or */
#define STM32_I2S3_BASE 0x40003c00 /* 0x40003c00-0x40003fff I2S3 */
#define STM32_I2S3EXT_BASE 0x40004000 /* 0x40004000-0x400043ff I2S3ext */
#define STM32_USART2_BASE 0x40004400 /* 0x40004400-0x400047ff USART2 */
#define STM32_USART3_BASE 0x40004800 /* 0x40004800-0x40004bff USART3 */
#define STM32_UART4_BASE 0x40004c00 /* 0x40004c00-0x40004fff UART4 */
#define STM32_UART5_BASE 0x40005000 /* 0x40005000-0x400053ff UART5 */
#define STM32_I2C1_BASE 0x40005400 /* 0x40005400-0x400057ff I2C1 */
#define STM32_I2C2_BASE 0x40005800 /* 0x40005800-0x40005bff I2C2 */
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
#define STM32_USBSRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */
/* APB2 Base Addresses **************************************************************/
#define STM32_SYSCFG_BASE 0x40010000 /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */
#define STM32_EXTI_BASE 0x40010400 /* 0x40010400-0x400107FF EXTI */
#define STM32_TIM1_BASE 0x40012c00 /* 0x40012c00-0x40012fff TIM1 */
#define STM32_SPI1_BASE 0x40013000 /* 0x40013000-0x400133ff SPI1 */
#define STM32_TIM8_BASE 0x40013400 /* 0x40013400-0x400137ff TIM8 */
#define STM32_USART1_BASE 0x40013800 /* 0x40013800-0x40013bff USART1 */
#define STM32_TIM15_BASE 0x40014000 /* 0x40014000-0x400143ff TIM15 */
#define STM32_TIM16_BASE 0x40014400 /* 0x40014400-0x400147ff TIM16 */
#define STM32_TIM17_BASE 0x40014800 /* 0x40014800-0x40014bff TIM17 */
/* AHB1 Base Addresses **************************************************************/
#define STM32_DMA1_BASE 0x40020000 /* 0x40020000-0x400203ff: DMA1 */
#define STM32_DMA2_BASE 0x40020400 /* 0x40020400-0x400207ff: DMA2 */
#define STM32_RCC_BASE 0x40021000 /* 0x40021000-0x400213ff: Reset and Clock control RCC */
#define STM32_FLASHIF_BASE 0x40022000 /* 0x40022000-0x400223ff: Flash memory interface */
#define STM32_CRC_BASE 0x40023000 /* 0x40023000-0x400233ff: CRC */
#define STM32_TSC_BASE 0x40024000 /* 0x40024000-0x400243ff: TSC */
/* AHB2 Base Addresses **************************************************************/
#define STM32_GPIOA_BASE 0x48000000 /* 0x48000000-0x480003ff: GPIO Port A */
#define STM32_GPIOB_BASE 0x48000400 /* 0x48000400-0x480007ff: GPIO Port B */
#define STM32_GPIOC_BASE 0x48000800 /* 0x48000800-0x48000bff: GPIO Port C */
#define STM32_GPIOD_BASE 0X40000C00 /* 0x48000c00-0x48000fff: GPIO Port D */
#define STM32_GPIOE_BASE 0x48001000 /* 0x48001000-0x480013ff: GPIO Port E */
#define STM32_GPIOF_BASE 0x48001400 /* 0x48001400-0x480017ff: GPIO Port F */
/* AHB3 Base Addresses **************************************************************/
#define STM32_ADC1_BASE 0x50000000 /* 0x5000004c-0x5000004c: Master ADC1 */
#define STM32_ADC2_BASE 0x50000100 /* 0x5000014c-0x500001ff: Slave ADC2 */
#define STM32_ADC12_BASE 0x50000300 /* 0x50000300-0x50000308: ADC12 Common */
#define STM32_ADC3_BASE 0x50000400 /* 0x5000044c-0x5000044c: Master ADC3 */
#define STM32_ADC4_BASE 0x50000500 /* 0x5000054c-0x500005ff: Slave ADC4 */
#define STM32_ADC34_BASE 0x50000700 /* 0x50000700-0x50000708: ADC34 Common */
/* Cortex-M4 Base Addresses *********************************************************/
/* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
* address range
*/
#define STM32_SCS_BASE 0xe000e000
#define STM32_DEBUGMCU_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F30XXX_MEMORYMAP_H */

149
arch/arm/src/stm32/chip/stm32f30xxx_vectors.h Normal file
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@ -0,0 +1,149 @@
/************************************************************************************
* arch/arm/src/stm32/chip/stm32f30xxx_vectors.h
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Pre-processor definitions
************************************************************************************/
/* This file is included by stm32_vectors.S. It provides the macro VECTOR that
* supplies each STM32F30xxx vector in terms of a (lower-case) ISR label and an
* (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f30xxx_irq.h.
* stm32_vectors.S will defined the VECTOR in different ways in order to generate
* the interrupt vectors and handlers in their final form.
*/
/* If the common ARMv7-M vector handling is used, then all it needs is the following
* definition that provides the number of supported vectors.
*/
#ifdef CONFIG_ARMV7M_CMNVECTOR
/* Reserve 82 interrupt table entries for I/O interrupts. */
# define ARMV7M_PERIPHERAL_INTERRUPTS 82
#else
VECTOR(stm32_wwdg, STM32_IRQ_WWDG) /* 0: Window Watchdog interrupt */
VECTOR(stm32_pvd, STM32_IRQ_PVD) /* 1: PVD through EXTI Line detection interrupt */
VECTOR(stm32_tamper, STM32_IRQ_TAMPER) /* 2: Tamper or Time stamp interrupt */
VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP) /* 3: RTC global interrupt */
VECTOR(stm32_flash, STM32_IRQ_FLASH) /* 4: Flash global interrupt */
VECTOR(stm32_rcc, STM32_IRQ_RCC) /* 5: RCC global interrupt */
VECTOR(stm32_exti0, STM32_IRQ_EXTI0) /* 6: EXTI Line 0 interrupt */
VECTOR(stm32_exti1, STM32_IRQ_EXTI1) /* 7: EXTI Line 1 interrupt */
VECTOR(stm32_exti2, STM32_IRQ_EXTI2) /* 8: EXTI Line 2 or TSC interrupt */
VECTOR(stm32_exti3, STM32_IRQ_EXTI3) /* 9: EXTI Line 3 interrupt */
VECTOR(stm32_exti4, STM32_IRQ_EXTI4) /* 10: EXTI Line 4 interrupt */
VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1) /* 11: DMA1 channel 1 global interrupt */
VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2) /* 12: DMA1 channel 2 global interrupt */
VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3) /* 13: DMA1 channel 3 global interrupt */
VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4) /* 14: DMA1 channel 4 global interrupt */
VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5) /* 15: DMA1 channel 5 global interrupt */
VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6) /* 16: DMA1 channel 6 global interrupt */
VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7) /* 17: DMA1 channel 7 global interrupt */
VECTOR(stm32_adc12, STM32_IRQ_ADC12) /* 18: ADC1/ADC2 global interrupt */
VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX) /* 19: USB High Priority or CAN1 TX interrupts */
VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0) /* 20: USB Low Priority or CAN1 RX0 interrupts*/
VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1) /* 21: CAN1 RX1 interrupt */
VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE) /* 22: CAN1 SCE interrupt */
VECTOR(stm32_exti95, STM32_IRQ_EXTI95) /* 23: EXTI Line[9:5] interrupts */
VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK) /* 24: TIM1 Break or TIM15 global interrupt */
VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP) /* 25: TIM1 Update or TIM16 global interrupt */
VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */
VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC) /* 27: TIM1 Capture Compare interrupt */
VECTOR(stm32_tim2, STM32_IRQ_TIM2) /* 28: TIM2 global interrupt */
VECTOR(stm32_tim3, STM32_IRQ_TIM3) /* 29: TIM3 global interrupt */
VECTOR(stm32_tim4, STM32_IRQ_TIM4) /* 30: TIM4 global interrupt */
VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV) /* 31: I2C1 event or EXTI Line23 interrupt */
VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER) /* 32: I2C1 error interrupt */
VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV) /* 33: I2C2 event or EXTI Line24 interrupt */
VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER) /* 34: I2C2 error interrupt */
VECTOR(stm32_spi1, STM32_IRQ_SPI1) /* 35: SPI1 global interrupt */
VECTOR(stm32_spi2, STM32_IRQ_SPI2) /* 36: SPI2 global interrupt */
VECTOR(stm32_usart1, STM32_IRQ_USART1) /* 37: USART1 global or EXTI Line 25 interrupt */
VECTOR(stm32_usart2, STM32_IRQ_USART2) /* 38: USART2 global or EXTI Line 26 interrupt */
VECTOR(stm32_usart3, STM32_IRQ_USART3) /* 39: USART3 global or EXTI Line 28 interrupt */
VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510) /* 40: EXTI Line[15:10] interrupts */
VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM) /* 41: RTC alarm through EXTI line interrupt */
VECTOR(stm32_ext18, STM32_IRQ_EXT18) /* 42: USB wakeup or EXTI Line 18 interrupt */
VECTOR(stm32_tim8brk, STM32_IRQ_TIM8BRK) /* 43: TIM8 Break interrupt */
VECTOR(stm32_tim8up, STM32_IRQ_TIM8UP) /* 44: TIM8 Update interrupt */
VECTOR(stm32_tim8trgcom, STM32_IRQ_TIM8TRGCOM) /* 45: TIM8 Trigger and Commutation interrupts */
VECTOR(stm32_tim8cc, STM32_IRQ_TIM8CC) /* 46: TIM8 Capture Compare interrupt */
VECTOR(stm32_adc3, STM32_IRQ_ADC3) /* 47: ADC3 global interrupt */
UNUSED(STM32_IRQ_RESERVED48) /* 48: Reserved */
UNUSED(STM32_IRQ_RESERVED49) /* 49: Reserved */
UNUSED(STM32_IRQ_RESERVED50) /* 50: Reserved */
VECTOR(stm32_spi3, STM32_IRQ_SPI3) /* 51: SPI3 global interrupt */
VECTOR(stm32_uart4, STM32_IRQ_UART4) /* 52: UART4 global or EXTI Line 34 interrupt */
VECTOR(stm32_uart5, STM32_IRQ_UART5) /* 53: UART5 global or EXTI Line 35 interrupt */
VECTOR(stm32_tim6, STM32_IRQ_TIM6) /* 54: TIM6 global or DAC1/2 underrun interrupts */
VECTOR(stm32_tim7, STM32_IRQ_TIM7) /* 55: TIM7 global interrupt */
VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1) /* 56: DMA2 channel 1 global interrupt */
VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2) /* 57: DMA2 channel 2 global interrupt */
VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3) /* 58: DMA2 channel 3 global interrupt */
VECTOR(stm32_dma2ch4, STM32_IRQ_DMA2CH4) /* 59: DMA2 channel 4 global interrupt */
VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5) /* 60: DMA2 channel 5 global interrupt */
VECTOR(stm32_adc4, STM32_IRQ_ADC4) /* 61: ADC4 global interrupt */
UNUSED(STM32_IRQ_RESERVED62) /* 62: Reserved */
UNUSED(STM32_IRQ_RESERVED63) /* 63: Reserved */
VECTOR(stm32_comp123, STM32_IRQ_COMP123) /* 64: COMP1-3 or EXTI Lines 21-2 and 29 interrupts */
VECTOR(stm32_comp456, STM32_IRQ_COMP456) /* 65: COMP4-6 or EXTI Lines 30-2 interrupts */
VECTOR(stm32_comp7, STM32_IRQ_COMP7) /* 66: COMP7 or EXTI Line 33 interrupt */
UNUSED(STM32_IRQ_RESERVED67) /* 67: Reserved */
UNUSED(STM32_IRQ_RESERVED68) /* 68: Reserved */
UNUSED(STM32_IRQ_RESERVED69) /* 69: Reserved */
UNUSED(STM32_IRQ_RESERVED70) /* 70: Reserved */
UNUSED(STM32_IRQ_RESERVED71) /* 71: Reserved */
UNUSED(STM32_IRQ_RESERVED72) /* 72: Reserved */
UNUSED(STM32_IRQ_RESERVED73) /* 73: Reserved */
VECTOR(stm32_usbhp, STM32_IRQ_USBHP_2) /* 74: USB High priority interrupt */
VECTOR(stm32_usblp, STM32_IRQ_USBLP_2) /* 75: USB Low priority interrupt */
VECTOR(stm32_usbwkup, STM32_IRQ_USBWKUP_2) /* 76: USB wakeup from suspend through EXTI line interrupt*/
UNUSED(STM32_IRQ_RESERVED77) /* 77: Reserved */
UNUSED(STM32_IRQ_RESERVED78) /* 78: Reserved */
UNUSED(STM32_IRQ_RESERVED79) /* 79: Reserved */
UNUSED(STM32_IRQ_RESERVED80) /* 80: Reserved */
VECTOR(stm32_fpu, STM32_IRQ_FPU) /* 81: FPU global interrupt */
#endif /* CONFIG_ARMV7M_CMNVECTOR */

4
arch/arm/src/stm32/stm32_vectors.S
View File

@ -150,6 +150,8 @@ stm32_vectors:
# include "chip/chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/chip/stm32f40xxx_vectors.h"
#else
@ -186,6 +188,8 @@ handlers:
# include "chip/chip/stm32f10xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F20XX)
# include "chip/chip/stm32f20xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F30XX)
# include "chip/chip/stm32f30xxx_vectors.h"
#elif defined(CONFIG_STM32_STM32F40XX)
# include "chip/chip/stm32f40xxx_vectors.h"
#else