From 21dcc8cbc7892cb27242523c57e2747f12cdf711 Mon Sep 17 00:00:00 2001 From: Eetu Nevalainen Date: Mon, 3 Jul 2017 11:06:07 -0600 Subject: [PATCH] stm32f40xxx_rtcc ISR register and write protection fix --- arch/arm/src/stm32/stm32f40xxx_rtcc.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index a2af73794e..2d511d1325 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -600,6 +600,10 @@ static int stm32_rtc_alarm_handler(int irq, void *context, void *arg) uint32_t cr; int ret = OK; + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + isr = getreg32(STM32_RTC_ISR); /* Check for EXTI from Alarm A or B and handle according */ @@ -624,7 +628,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context, void *arg) } isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; - putreg32(isr, STM32_RTC_CR); + putreg32(isr, STM32_RTC_ISR); } } @@ -649,11 +653,14 @@ static int stm32_rtc_alarm_handler(int irq, void *context, void *arg) } isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; - putreg32(isr, STM32_RTC_CR); + putreg32(isr, STM32_RTC_ISR); } } #endif + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); return ret; } #endif