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stm32/qenco: fix compilation for STM32F1. GTIM_CCER_CCxNP bits are not present in F1

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raiden00pl 2021-08-09 21:34:39 +02:00 committed by Alan Carvalho de Assis
parent af6c311fd1
commit 21f59c874f
1 changed files with 8 additions and 0 deletions
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8
arch/arm/src/stm32/stm32_qencoder.c
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@ -824,7 +824,11 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
/* Select the Polarity=rising and set the CC1E Bit */
#ifdef HAVE_GTIM_CCXNP
ccer &= ~(GTIM_CCER_CC1P | GTIM_CCER_CC1NP);
#else
ccer &= ~(GTIM_CCER_CC1P);
#endif
ccer |= GTIM_CCER_CC1E;
/* Write to TIM CCMR1 and CCER registers */
@ -860,7 +864,11 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower)
/* Select the Polarity=rising and set the CC2E Bit */
#ifdef HAVE_GTIM_CCXNP
ccer &= ~(GTIM_CCER_CC2P | GTIM_CCER_CC2NP);
#else
ccer &= ~(GTIM_CCER_CC2P);
#endif
ccer |= GTIM_CCER_CC2E;
/* Write to TIM CCMR1 and CCER registers */