stm32u5: fix EXTICR2,3,4 register offsets
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@ -49,9 +49,9 @@
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#define STM32_EXTI_SECCFGR2_OFFSET 0x0034 /* Security Configuration 2 */
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#define STM32_EXTI_PRIVCFGR2_OFFSET 0x0038 /* Privilege Configuration 2 */
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#define STM32_EXTI_EXTICR1_OFFSET 0x0060 /* External Interrupt Selection 1 */
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#define STM32_EXTI_EXTICR2_OFFSET 0x0060 /* External Interrupt Selection 2 */
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#define STM32_EXTI_EXTICR3_OFFSET 0x0060 /* External Interrupt Selection 3 */
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#define STM32_EXTI_EXTICR4_OFFSET 0x0060 /* External Interrupt Selection 4 */
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#define STM32_EXTI_EXTICR2_OFFSET 0x0064 /* External Interrupt Selection 2 */
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#define STM32_EXTI_EXTICR3_OFFSET 0x0068 /* External Interrupt Selection 3 */
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#define STM32_EXTI_EXTICR4_OFFSET 0x006C /* External Interrupt Selection 4 */
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#define STM32_EXTI_LOCKR_OFFSET 0x0070 /* Lock */
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#define STM32_EXTI_IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 */
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#define STM32_EXTI_EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 */
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