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STM32 F100 High Density support and generic board configuration from Freddie Chopin

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5315 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-11-06 13:36:51 +00:00
parent 51793af904
commit 221b3b9f52
6 changed files with 808 additions and 345 deletions
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200
arch/arm/include/stm32/chip.h
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@ -59,12 +59,11 @@
/* STM32 F100 Value Line ************************************************************/
#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) \
|| defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -72,15 +71,110 @@
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
# define STM32_NBTIM 0 /* No basic timers */
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
// TODO: there are also 3 additional timers (15-17) that don't fit any existing category
# define STM32_NDMA 1 /* DMA1 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S (?) */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 64 /* GPIOA-D */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
// TODO: there are also 3 additional timers (15-17) that don't fit any existing category
# define STM32_NDMA 1 /* DMA1 */
# define STM32_NSPI 2 /* SPI1-2 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 3 /* USART1-3 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
/* STM32 F100 High-density value Line ************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \
|| defined(CONFIG_ARCH_CHIP_STM32F100RE)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
// TODO: there are also 6 additional timers (12-17) that don't fit any existing category
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 64 /* GPIOA-D */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
# define STM32_NCRC 1 /* CRC1 */
# define STM32_NETHERNET 0 /* No ethernet */
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \
|| defined(CONFIG_ARCH_CHIP_STM32F100VE)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
# define STM32_NATIM 1 /* One advanced timer TIM1 */
# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
// TODO: there are also 6 additional timers (12-17) that don't fit any existing category
# define STM32_NDMA 2 /* DMA1-2 */
# define STM32_NSPI 3 /* SPI1-3 */
# define STM32_NI2S 0 /* No I2S */
# define STM32_NUSART 5 /* USART1-5 */
# define STM32_NI2C 2 /* I2C1-2 */
# define STM32_NCAN 0 /* No CAN */
# define STM32_NSDIO 0 /* No SDIO */
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
# define STM32_NGPIO 80 /* GPIOA-E */
# define STM32_NADC 1 /* ADC1 */
# define STM32_NDAC 2 /* DAC 1-2 */
@ -96,9 +190,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -129,9 +223,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6) || defined(CONFIG_ARCH_CHIP_STM32F103VET6)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -162,9 +256,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -192,9 +286,9 @@
/* STM32 F105/F107 Connectivity Line *******************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F105VBT7)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -221,9 +315,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -251,9 +345,9 @@
/* STM32 F2 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F207IG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
@ -283,9 +377,9 @@
/* STM23 F4 Family ******************************************************************/
#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -314,9 +408,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -345,9 +439,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -376,9 +470,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -407,9 +501,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -438,9 +532,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -469,9 +563,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -500,9 +594,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
@ -531,9 +625,9 @@
#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */

373
arch/arm/src/stm32/Kconfig
View File

@ -34,6 +34,27 @@ config ARCH_CHIP_STM32F100RB
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100RC
bool "STM32F100RC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100RD
bool "STM32F100RD"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100RE
bool "STM32F100RE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100V8
bool "STM32F100V8"
select ARCH_CORTEXM3
@ -46,6 +67,27 @@ config ARCH_CHIP_STM32F100VB
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100VC
bool "STM32F100VC"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100VD
bool "STM32F100VD"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F100VE
bool "STM32F100VE"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103RET6
bool "STM32F103RET6"
select ARCH_CORTEXM3
@ -183,6 +225,7 @@ endchoice
config STM32_DFU
bool "DFU bootloader"
default n
depends on !STM32_VALUELINE
---help---
Configure and position code for use with the STMicro DFU bootloader. Do
not select this option if you will load code using JTAG/SWM.
@ -198,25 +241,13 @@ config STM32_ADC2
bool "ADC2"
default n
select STM32_ADC
depends on !STM32_VALUELINE
config STM32_ADC3
bool "ADC3"
default n
select STM32_ADC
config STM32_CRC
bool "CRC"
default n
config STM32_DMA1
bool "DMA1"
default n
select ARCH_DMA
config STM32_DMA2
bool "DMA2"
default n
select ARCH_DMA
depends on !STM32_VALUELINE
config STM32_BKP
bool "BKP"
@ -233,6 +264,7 @@ config STM32_CAN1
default n
select CAN
select STM32_CAN
depends on !STM32_VALUELINE
config STM32_CAN2
bool "CAN2"
@ -246,11 +278,31 @@ config STM32_CCMDATARAM
default n
depends on STM32_STM32F40XX
config STM32_CEC
bool "CEC"
default n
depends on STM32_VALUELINE
config STM32_CRC
bool "CRC"
default n
config STM32_CRYP
bool "CRYP"
default n
depends on STM32_STM32F20XX || STM32_STM32F40XX
config STM32_DMA1
bool "DMA1"
default n
select ARCH_DMA
config STM32_DMA2
bool "DMA2"
default n
select ARCH_DMA
depends on !STM32_VALUELINE || (STM32_VALUELINE && STM32_HIGHDENSITY)
config STM32_DAC1
bool "DAC1"
default n
@ -275,7 +327,7 @@ config STM32_ETHMAC
config STM32_FSMC
bool "FSMC"
default n
depends on !STM32_CONNECTIVITYLINE
depends on !STM32_CONNECTIVITYLINE && STM32_HIGHDENSITY
config STM32_HASH
bool "HASH"
@ -326,7 +378,7 @@ config STM32_RNG
config STM32_SDIO
bool "SDIO"
default n
depends on !STM32_CONNECTIVITYLINE
depends on !STM32_CONNECTIVITYLINE && !STM32_VALUELINE
config STM32_SPI1
bool "SPI1"
@ -343,7 +395,7 @@ config STM32_SPI2
config STM32_SPI3
bool "SPI3"
default n
depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_CONNECTIVITYLINE || STM32_STM32F20XX || STM32_STM32F40XX || (STM32_VALUELINE && STM32_HIGHDENSITY)
select SPI
select STM32_SPI
@ -383,6 +435,7 @@ config STM32_TIM7
config STM32_TIM8
bool "TIM8"
default n
depends on !STM32_VALUELINE
config STM32_TIM9
bool "TIM9"
@ -402,17 +455,32 @@ config STM32_TIM11
config STM32_TIM12
bool "TIM12"
default n
depends on STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
config STM32_TIM13
bool "TIM13"
default n
depends on STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
config STM32_TIM14
bool "TIM14"
default n
depends on STM32_STM32F20XX || STM32_STM32F40XX
depends on STM32_STM32F20XX || STM32_STM32F40XX || STM32_VALUELINE
config STM32_TIM15
bool "TIM15"
default n
depends on STM32_VALUELINE
config STM32_TIM16
bool "TIM16"
default n
depends on STM32_VALUELINE
config STM32_TIM17
bool "TIM17"
default n
depends on STM32_VALUELINE
config STM32_USART1
bool "USART1"
@ -448,7 +516,7 @@ config STM32_USART6
config STM32_USB
bool "USB Device"
default n
depends on STM32_STM32F10XX
depends on STM32_STM32F10XX && !STM32_VALUELINE
select USBDEV
config STM32_WWDG
@ -475,6 +543,52 @@ config STM32_CAN
menu "Alternate Pin Mapping"
choice
prompt "CAN1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_CAN1
default STM32_CAN1_NO_REMAP
config STM32_CAN1_NO_REMAP
bool "No pin remapping"
config STM32_CAN1_REMAP1
bool "CAN1 alternate pin remapping #1"
config STM32_CAN1_REMAP2
bool "CAN1 alternate pin remapping #2"
endchoice
config STM32_CAN2_REMAP
bool "CAN2 Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_CAN2
config STM32_CEC_REMAP
bool "CEC Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_CEC
config STM32_ETH_REMAP
bool "Ethernet Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC
config STM32_I2C1_REMAP
bool "I2C1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_I2C1
config STM32_SPI1_REMAP
bool "SPI1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI1
config STM32_SPI3_REMAP
bool "SPI3 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI3 && !STM32_VALUELINE
choice
prompt "TIM1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_TIM1
@ -531,6 +645,51 @@ config STM32_TIM4_REMAP
default n
depends on STM32_STM32F10XX && STM32_TIM4
config STM32_TIM9_REMAP
bool "TIM9 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM9
config STM32_TIM10_REMAP
bool "TIM10 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM10
config STM32_TIM11_REMAP
bool "TIM11 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM11
config STM32_TIM12_REMAP
bool "TIM12 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM12
config STM32_TIM13_REMAP
bool "TIM13 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM13
config STM32_TIM14_REMAP
bool "TIM14 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM14
config STM32_TIM15_REMAP
bool "TIM15 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM15
config STM32_TIM16_REMAP
bool "TIM16 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM16
config STM32_TIM17_REMAP
bool "TIM17 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_TIM17
config STM32_USART1_REMAP
bool "USART1 Alternate Pin Mapping"
default n
@ -557,47 +716,6 @@ config STM32_USART3_PARTIAL_REMAP
endchoice
config STM32_SPI1_REMAP
bool "SPI1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI1
config STM32_SPI3_REMAP
bool "SPI3 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_SPI3
config STM32_I2C1_REMAP
bool "I2C1 Alternate Pin Mapping"
default n
depends on STM32_STM32F10XX && STM32_I2C1
choice
prompt "CAN1 Alternate Pin Mappings"
depends on STM32_STM32F10XX && STM32_CAN1
default STM32_CAN1_NO_REMAP
config STM32_CAN1_NO_REMAP
bool "No pin remapping"
config STM32_CAN1_REMAP1
bool "CAN1 alternate pin remapping #1"
config STM32_CAN1_REMAP2
bool "CAN1 alternate pin remapping #2"
endchoice
config STM32_CAN2_REMAP
bool "CAN2 Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_CAN2
config STM32_ETH_REMAP
bool "Ethernet Alternate Pin Mapping"
default n
depends on STM32_CONNECTIVITYLINE && STM32_ETHMAC
endmenu
choice
@ -666,6 +784,7 @@ config STM32_TIM1_PWM
config STM32_TIM1_CHANNEL
int "TIM1 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM1_PWM
---help---
If TIM1 is enabled for PWM usage, you also need specifies the timer output
@ -676,7 +795,7 @@ config STM32_TIM2_PWM
default n
depends on STM32_TIM2
---help---
Reserve timer 1 for use by PWM
Reserve timer 2 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM2
@ -686,6 +805,7 @@ config STM32_TIM2_PWM
config STM32_TIM2_CHANNEL
int "TIM2 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM2_PWM
---help---
If TIM2 is enabled for PWM usage, you also need specifies the timer output
@ -696,7 +816,7 @@ config STM32_TIM3_PWM
default n
depends on STM32_TIM3
---help---
Reserve timer 1 for use by PWM
Reserve timer 3 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM3
@ -706,6 +826,7 @@ config STM32_TIM3_PWM
config STM32_TIM3_CHANNEL
int "TIM3 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM3_PWM
---help---
If TIM3 is enabled for PWM usage, you also need specifies the timer output
@ -716,7 +837,7 @@ config STM32_TIM4_PWM
default n
depends on STM32_TIM4
---help---
Reserve timer 1 for use by PWM
Reserve timer 4 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM4
@ -726,6 +847,7 @@ config STM32_TIM4_PWM
config STM32_TIM4_CHANNEL
int "TIM4 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM4_PWM
---help---
If TIM4 is enabled for PWM usage, you also need specifies the timer output
@ -736,7 +858,7 @@ config STM32_TIM5_PWM
default n
depends on STM32_TIM5
---help---
Reserve timer 1 for use by PWM
Reserve timer 5 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM5
@ -746,6 +868,7 @@ config STM32_TIM5_PWM
config STM32_TIM5_CHANNEL
int "TIM5 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM5_PWM
---help---
If TIM5 is enabled for PWM usage, you also need specifies the timer output
@ -756,7 +879,7 @@ config STM32_TIM8_PWM
default n
depends on STM32_TIM8
---help---
Reserve timer 1 for use by PWM
Reserve timer 8 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM8
@ -766,6 +889,7 @@ config STM32_TIM8_PWM
config STM32_TIM8_CHANNEL
int "TIM8 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM8_PWM
---help---
If TIM8 is enabled for PWM usage, you also need specifies the timer output
@ -776,7 +900,7 @@ config STM32_TIM9_PWM
default n
depends on STM32_TIM9
---help---
Reserve timer 1 for use by PWM
Reserve timer 9 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM9
@ -786,6 +910,7 @@ config STM32_TIM9_PWM
config STM32_TIM9_CHANNEL
int "TIM9 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM9_PWM
---help---
If TIM9 is enabled for PWM usage, you also need specifies the timer output
@ -796,7 +921,7 @@ config STM32_TIM10_PWM
default n
depends on STM32_TIM10
---help---
Reserve timer 1 for use by PWM
Reserve timer 10 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM10
@ -806,6 +931,7 @@ config STM32_TIM10_PWM
config STM32_TIM10_CHANNEL
int "TIM10 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM10_PWM
---help---
If TIM10 is enabled for PWM usage, you also need specifies the timer output
@ -816,7 +942,7 @@ config STM32_TIM11_PWM
default n
depends on STM32_TIM11
---help---
Reserve timer 1 for use by PWM
Reserve timer 11 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM11
@ -826,6 +952,7 @@ config STM32_TIM11_PWM
config STM32_TIM11_CHANNEL
int "TIM11 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM11_PWM
---help---
If TIM11 is enabled for PWM usage, you also need specifies the timer output
@ -836,7 +963,7 @@ config STM32_TIM12_PWM
default n
depends on STM32_TIM12
---help---
Reserve timer 1 for use by PWM
Reserve timer 12 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM12
@ -846,6 +973,7 @@ config STM32_TIM12_PWM
config STM32_TIM12_CHANNEL
int "TIM12 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM12_PWM
---help---
If TIM12 is enabled for PWM usage, you also need specifies the timer output
@ -856,7 +984,7 @@ config STM32_TIM13_PWM
default n
depends on STM32_TIM13
---help---
Reserve timer 1 for use by PWM
Reserve timer 13 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM13
@ -866,6 +994,7 @@ config STM32_TIM13_PWM
config STM32_TIM13_CHANNEL
int "TIM13 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM13_PWM
---help---
If TIM13 is enabled for PWM usage, you also need specifies the timer output
@ -876,7 +1005,7 @@ config STM32_TIM14_PWM
default n
depends on STM32_TIM14
---help---
Reserve timer 1 for use by PWM
Reserve timer 14 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM14
@ -886,11 +1015,75 @@ config STM32_TIM14_PWM
config STM32_TIM14_CHANNEL
int "TIM14 PWM Output Channel"
default 1
range 1 4
depends on STM32_TIM14_PWM
---help---
If TIM14 is enabled for PWM usage, you also need specifies the timer output
channel {1,..,4}
config STM32_TIM15_PWM
bool "TIM15 PWM"
default n
depends on STM32_TIM15
---help---
Reserve timer 15 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM15
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM15_CHANNEL
int "TIM15 PWM Output Channel"
default 1
range 1 2
depends on STM32_TIM15_PWM
---help---
If TIM15 is enabled for PWM usage, you also need specifies the timer output
channel {1,2}
config STM32_TIM16_PWM
bool "TIM16 PWM"
default n
depends on STM32_TIM16
---help---
Reserve timer 16 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM16
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM16_CHANNEL
int "TIM16 PWM Output Channel"
default 1
range 1 1
depends on STM32_TIM16_PWM
---help---
If TIM16 is enabled for PWM usage, you also need specifies the timer output
channel {1}
config STM32_TIM17_PWM
bool "TIM17 PWM"
default n
depends on STM32_TIM17
---help---
Reserve timer 17 for use by PWM
Timer devices may be used for different purposes. One special purpose is
to generate modulated outputs for such things as motor control. If STM32_TIM17
is defined then THIS following may also be defined to indicate that
the timer is intended to be used for pulsed output modulation.
config STM32_TIM17_CHANNEL
int "TIM17 PWM Output Channel"
default 1
range 1 1
depends on STM32_TIM17_PWM
---help---
If TIM17 is enabled for PWM usage, you also need specifies the timer output
channel {1}
config STM32_TIM1_ADC
bool "TIM1 ADC"
default n
@ -1233,7 +1426,7 @@ config STM32_TIM2_DAC
default n
depends on STM32_TIM2 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 2 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM2 is
defined then the following may also be defined to indicate that the
@ -1264,7 +1457,7 @@ config STM32_TIM3_DAC
default n
depends on STM32_TIM3 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 3 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM3 is
defined then the following may also be defined to indicate that the
@ -1295,7 +1488,7 @@ config STM32_TIM4_DAC
default n
depends on STM32_TIM4 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 4 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM4 is
defined then the following may also be defined to indicate that the
@ -1326,7 +1519,7 @@ config STM32_TIM5_DAC
default n
depends on STM32_TIM5 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 5 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM5 is
defined then the following may also be defined to indicate that the
@ -1357,7 +1550,7 @@ config STM32_TIM6_DAC
default n
depends on STM32_TIM6 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 6 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM6 is
defined then the following may also be defined to indicate that the
@ -1388,7 +1581,7 @@ config STM32_TIM7_DAC
default n
depends on STM32_TIM7 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 7 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM7 is
defined then the following may also be defined to indicate that the
@ -1419,7 +1612,7 @@ config STM32_TIM8_DAC
default n
depends on STM32_TIM8 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 8 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM8 is
defined then the following may also be defined to indicate that the
@ -1450,7 +1643,7 @@ config STM32_TIM9_DAC
default n
depends on STM32_TIM9 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 9 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM9 is
defined then the following may also be defined to indicate that the
@ -1481,7 +1674,7 @@ config STM32_TIM10_DAC
default n
depends on STM32_TIM10 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 10 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM10 is
defined then the following may also be defined to indicate that the
@ -1512,7 +1705,7 @@ config STM32_TIM11_DAC
default n
depends on STM32_TIM11 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 11 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM11 is
defined then the following may also be defined to indicate that the
@ -1543,7 +1736,7 @@ config STM32_TIM12_DAC
default n
depends on STM32_TIM12 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 12 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM12 is
defined then the following may also be defined to indicate that the
@ -1574,7 +1767,7 @@ config STM32_TIM13_DAC
default n
depends on STM32_TIM13 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 13 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM13 is
defined then the following may also be defined to indicate that the
@ -1605,7 +1798,7 @@ config STM32_TIM14_DAC
default n
depends on STM32_TIM14 && STM32_DAC
---help---
Reserve timer 1 for use by DAC
Reserve timer 14 for use by DAC
Timer devices may be used for different purposes. If STM32_TIM14 is
defined then the following may also be defined to indicate that the
@ -1992,14 +2185,14 @@ config STM32_OTGFS_NPTXFIFO_SIZE
depends on USBHOST && STM32_OTGFS
---help---
Size of the non-periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGFS_PTXFIFO_SIZE
int "Periodic Tx FIFO size"
default 128
depends on USBHOST && STM32_OTGFS
---help---
Size of the periodic Tx FIFO in 32-bit words. Default 96 (384 bytes)
config STM32_OTGFS_DESCSIZE
int "Descriptor Size"
default 128
@ -2013,14 +2206,14 @@ config STM32_OTGFS_SOFINTR
depends on USBHOST && STM32_OTGFS
---help---
Enable SOF interrupts. Why would you ever want to do that?
config STM32_USBHOST_REGDEBUG
bool "Register-Level Debug"
default n
depends on USBHOST && STM32_OTGFS
---help---
Enable very low-level register access debug. Depends on DEBUG.
config STM32_USBHOST_PKTDUMP
bool "Packet Dump Debug"
default n

526
arch/arm/src/stm32/chip/stm32f100_pinmap.h
View File

@ -6,6 +6,8 @@
* Copyright (C) 2012 Michael Smith. All Rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Uros Platise <uros.platise@isotel.eu>
* Michael Smith
* Freddie Chopin <freddie_chopin@op.pl>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -49,219 +51,343 @@
* Pre-processor Definitions
************************************************************************************/
/* TIMERS */
/* Alternate Pin Functions: */
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN9)
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN9)
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN11)
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN11)
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN13)
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN13)
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN14)
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN14)
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN15)
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN8)
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN10)
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTE|GPIO_PIN12)
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
/* ADC */
#define GPIO_ADC1_IN0 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
#define GPIO_ADC1_IN1 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN1)
#define GPIO_ADC1_IN2 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
#define GPIO_ADC1_IN3 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
#define GPIO_ADC1_IN4 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN4)
#define GPIO_ADC1_IN5 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN5)
#define GPIO_ADC1_IN6 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN6)
#define GPIO_ADC1_IN7 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN7)
#define GPIO_ADC1_IN8 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN0)
#define GPIO_ADC1_IN9 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN1)
#define GPIO_ADC1_IN10 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN0)
#define GPIO_ADC1_IN11 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN1)
#define GPIO_ADC1_IN12 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN2)
#define GPIO_ADC1_IN13 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN3)
#define GPIO_ADC1_IN14 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN4)
#define GPIO_ADC1_IN15 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN5)
/* CEC */
#if defined(CONFIG_STM32_CEC_REMAP)
# define GPIO_CEC (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
#else
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
# define GPIO_TIM1_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN8)
# define GPIO_TIM1_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN8)
# define GPIO_TIM1_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
# define GPIO_TIM1_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
# define GPIO_TIM1_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
# define GPIO_TIM1_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN10)
# define GPIO_TIM1_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
# define GPIO_TIM1_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
# define GPIO_TIM1_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
# define GPIO_TIM1_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
# define GPIO_TIM1_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
# define GPIO_TIM1_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
# define GPIO_CEC (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN8)
#endif
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN3)
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN10)
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
#else
# define GPIO_TIM2_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
# define GPIO_TIM2_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
# define GPIO_TIM2_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
# define GPIO_TIM2_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
# define GPIO_TIM2_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
# define GPIO_TIM2_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
# define GPIO_TIM2_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
#endif
/* DAC
* Note from RM0041, 11.2: "Once the DAC channelx is enabled, the corresponding
* GPIO pin (PA4 or PA5) is automatically connected to the analog converter
* output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5
* pin should first be configured to analog (AIN)."
*/
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
#else
# define GPIO_TIM3_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
# define GPIO_TIM3_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
# define GPIO_TIM3_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
# define GPIO_TIM3_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
# define GPIO_TIM3_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
# define GPIO_TIM3_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
# define GPIO_TIM3_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
# define GPIO_TIM3_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
#endif
#define GPIO_DAC_OUT1 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT | GPIO_CNF_ANALOGIN | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN5)
#if defined(CONFIG_STM32_TIM4_REMAP)
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN12)
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN13)
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN13)
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN14)
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN14)
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN15)
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN15)
#else
# define GPIO_TIM4_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN6)
# define GPIO_TIM4_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_TIM4_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
# define GPIO_TIM4_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
# define GPIO_TIM4_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
# define GPIO_TIM4_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_TIM4_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
#endif
/* FSMC */
/* USART */
#if defined(CONFIG_STM32_USART1_REMAP)
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN7)
#else
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
#endif
#if defined(CONFIG_STM32_USART2_REMAP)
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN3)
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN4)
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN5)
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN6)
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
#else
# define GPIO_USART2_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
# define GPIO_USART2_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
# define GPIO_USART2_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
# define GPIO_USART2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
# define GPIO_USART2_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
#endif
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN8)
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN9)
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN10)
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN11)
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN12)
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
#else
# define GPIO_USART3_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
# define GPIO_USART3_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN11)
# define GPIO_USART3_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
# define GPIO_USART3_CTS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
#endif
/* SPI */
#if defined(CONFIG_STM32_SPI1_REMAP)
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
#else
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
# define GPIO_SPI1_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
# define GPIO_SPI1_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
#endif
#define GPIO_SPI2_NSS (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
#define GPIO_SPI2_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
#define GPIO_SPI2_MISO (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SPI2_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
/* TODO - VL devices in 100- and 144-pin packages have FSMC */
/* I2C */
#if defined(CONFIG_STM32_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_I2C1_SCL (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN9)
#else
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
# define GPIO_I2C1_SCL (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN6)
# define GPIO_I2C1_SDA (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN7)
#endif
#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
#define GPIO_I2C1_SMBA (GPIO_ALT | GPIO_CNF_INFLOAT | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN5)
#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
#define GPIO_I2C2_SCL (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
#define GPIO_I2C2_SDA (GPIO_ALT | GPIO_CNF_AFOD | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN11)
#define GPIO_I2C2_SMBA (GPIO_ALT | GPIO_CNF_INFLOAT | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN12)
/* SPI */
#if defined(CONFIG_STM32_SPI1_REMAP)
# define GPIO_SPI1_NSS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN15)
# define GPIO_SPI1_SCK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN3)
# define GPIO_SPI1_MISO (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN4)
# define GPIO_SPI1_MOSI (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN5)
#else
# define GPIO_SPI1_NSS (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN4)
# define GPIO_SPI1_SCK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN5)
# define GPIO_SPI1_MISO (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN6)
# define GPIO_SPI1_MOSI (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN7)
#endif
#define GPIO_SPI2_NSS (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN12)
#define GPIO_SPI2_SCK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN13)
#define GPIO_SPI2_MISO (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN14)
#define GPIO_SPI2_MOSI (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN15)
#define GPIO_SPI3_NSS (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN15)
#define GPIO_SPI3_SCK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN3)
#define GPIO_SPI3_MISO (GPIO_INPUT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN4)
#define GPIO_SPI3_MOSI (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN5)
/* TIMERS */
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN7)
# define GPIO_TIM1_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN9)
# define GPIO_TIM1_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN9)
# define GPIO_TIM1_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN11)
# define GPIO_TIM1_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN11)
# define GPIO_TIM1_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN13)
# define GPIO_TIM1_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN13)
# define GPIO_TIM1_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN14)
# define GPIO_TIM1_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN14)
# define GPIO_TIM1_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTE | GPIO_PIN15)
# define GPIO_TIM1_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN8)
# define GPIO_TIM1_CH2N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN10)
# define GPIO_TIM1_CH3N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTE | GPIO_PIN12)
#elif defined(CONFIG_STM32_TIM1_PARTIAL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN12)
# define GPIO_TIM1_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN8)
# define GPIO_TIM1_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN8)
# define GPIO_TIM1_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN9)
# define GPIO_TIM1_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN9)
# define GPIO_TIM1_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN10)
# define GPIO_TIM1_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN10)
# define GPIO_TIM1_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN11)
# define GPIO_TIM1_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN11)
# define GPIO_TIM1_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN6)
# define GPIO_TIM1_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN7)
# define GPIO_TIM1_CH2N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM1_CH3N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN1)
#else
# define GPIO_TIM1_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN12)
# define GPIO_TIM1_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN8)
# define GPIO_TIM1_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN8)
# define GPIO_TIM1_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN9)
# define GPIO_TIM1_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN9)
# define GPIO_TIM1_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN10)
# define GPIO_TIM1_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN10)
# define GPIO_TIM1_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN11)
# define GPIO_TIM1_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN11)
# define GPIO_TIM1_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN12)
# define GPIO_TIM1_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN13)
# define GPIO_TIM1_CH2N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN14)
# define GPIO_TIM1_CH3N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN15)
#endif
#if defined(CONFIG_STM32_TIM2_FULL_REMAP)
# define GPIO_TIM2_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN3)
# define GPIO_TIM2_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN3)
# define GPIO_TIM2_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN10)
# define GPIO_TIM2_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
# define GPIO_TIM2_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN11)
# define GPIO_TIM2_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN11)
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_1)
# define GPIO_TIM2_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN15)
# define GPIO_TIM2_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN3)
# define GPIO_TIM2_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN3)
# define GPIO_TIM2_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM2_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM2_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
# define GPIO_TIM2_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN3)
#elif defined(CONFIG_STM32_TIM2_PARTIAL_REMAP_2)
# define GPIO_TIM2_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN1)
# define GPIO_TIM2_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN1)
# define GPIO_TIM2_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN10)
# define GPIO_TIM2_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
# define GPIO_TIM2_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN11)
# define GPIO_TIM2_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN11)
#else
# define GPIO_TIM2_ETR (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN0)
# define GPIO_TIM2_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN1)
# define GPIO_TIM2_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN1)
# define GPIO_TIM2_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM2_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM2_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
# define GPIO_TIM2_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN3)
#endif
#if defined(CONFIG_STM32_TIM3_FULL_REMAP)
# define GPIO_TIM3_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN6)
# define GPIO_TIM3_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN6)
# define GPIO_TIM3_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN7)
# define GPIO_TIM3_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN7)
# define GPIO_TIM3_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN8)
# define GPIO_TIM3_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN8)
# define GPIO_TIM3_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN9)
# define GPIO_TIM3_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN9)
#elif defined(CONFIG_STM32_TIM3_PARTIAL_REMAP)
# define GPIO_TIM3_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN4)
# define GPIO_TIM3_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN4)
# define GPIO_TIM3_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN5)
# define GPIO_TIM3_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN5)
# define GPIO_TIM3_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM3_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM3_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN1)
# define GPIO_TIM3_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN1)
#else
# define GPIO_TIM3_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN6)
# define GPIO_TIM3_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN6)
# define GPIO_TIM3_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN7)
# define GPIO_TIM3_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN7)
# define GPIO_TIM3_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM3_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM3_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN1)
# define GPIO_TIM3_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN1)
#endif
#if defined(CONFIG_STM32_TIM4_REMAP)
# define GPIO_TIM4_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN12)
# define GPIO_TIM4_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN12)
# define GPIO_TIM4_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN13)
# define GPIO_TIM4_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN13)
# define GPIO_TIM4_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN14)
# define GPIO_TIM4_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN14)
# define GPIO_TIM4_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN15)
# define GPIO_TIM4_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN15)
#else
# define GPIO_TIM4_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN6)
# define GPIO_TIM4_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN6)
# define GPIO_TIM4_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN7)
# define GPIO_TIM4_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN7)
# define GPIO_TIM4_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN8)
# define GPIO_TIM4_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN8)
# define GPIO_TIM4_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN9)
# define GPIO_TIM4_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN9)
#endif
#define GPIO_TIM5_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM5_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN0)
#define GPIO_TIM5_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM5_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN1)
#define GPIO_TIM5_CH3IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM5_CH3OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN2)
#define GPIO_TIM5_CH4IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
#define GPIO_TIM5_CH4OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN3)
#if defined(CONFIG_STM32_TIM12_REMAP)
# define GPIO_TIM12_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN12)
# define GPIO_TIM12_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN12)
# define GPIO_TIM12_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN13)
# define GPIO_TIM12_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN13)
#else
# define GPIO_TIM12_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN4)
# define GPIO_TIM12_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN4)
# define GPIO_TIM12_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN5)
# define GPIO_TIM12_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_TIM13_REMAP)
# define GPIO_TIM13_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN0)
# define GPIO_TIM13_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN0)
#else
# define GPIO_TIM13_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN8)
# define GPIO_TIM13_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN8)
#endif
#if defined(CONFIG_STM32_TIM14_REMAP)
# define GPIO_TIM14_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN1)
# define GPIO_TIM14_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN1)
#else
# define GPIO_TIM14_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN9)
# define GPIO_TIM14_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN9)
#endif
#if defined(CONFIG_STM32_TIM15_REMAP)
# define GPIO_TIM15_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN14)
# define GPIO_TIM15_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN14)
# define GPIO_TIM15_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN15)
# define GPIO_TIM15_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN15)
#else
# define GPIO_TIM15_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM15_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN2)
# define GPIO_TIM15_CH2IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
# define GPIO_TIM15_CH2OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN3)
#endif
#define GPIO_TIM15_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM15_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN15)
#if defined(CONFIG_STM32_TIM16_REMAP)
# define GPIO_TIM16_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN6)
# define GPIO_TIM16_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN6)
#else
# define GPIO_TIM16_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN8)
# define GPIO_TIM16_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN8)
#endif
#define GPIO_TIM16_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN5)
#define GPIO_TIM16_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN6)
#if defined(CONFIG_STM32_TIM17_REMAP)
# define GPIO_TIM17_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN7)
# define GPIO_TIM17_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN7)
#else
# define GPIO_TIM17_CH1IN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN9)
# define GPIO_TIM17_CH1OUT (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN9)
#endif
#define GPIO_TIM17_BKIN (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM17_CH1N (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN7)
/* USART */
#if defined(CONFIG_STM32_USART1_REMAP)
# define GPIO_USART1_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN6)
# define GPIO_USART1_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN7)
#else
# define GPIO_USART1_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN9)
# define GPIO_USART1_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN10)
#endif
#if defined(CONFIG_STM32_USART2_REMAP)
# define GPIO_USART2_CTS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN3)
# define GPIO_USART2_RTS (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN4)
# define GPIO_USART2_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN5)
# define GPIO_USART2_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN6)
# define GPIO_USART2_CK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN7)
#else
# define GPIO_USART2_CTS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN0)
# define GPIO_USART2_RTS (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN1)
# define GPIO_USART2_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN2)
# define GPIO_USART2_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTA | GPIO_PIN3)
# define GPIO_USART2_CK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTA | GPIO_PIN4)
#endif
#if defined(CONFIG_STM32_USART3_FULL_REMAP)
# define GPIO_USART3_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN8)
# define GPIO_USART3_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN9)
# define GPIO_USART3_CK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN10)
# define GPIO_USART3_CTS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN11)
# define GPIO_USART3_RTS (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTD | GPIO_PIN12)
#elif defined(CONFIG_STM32_USART3_PARTIAL_REMAP)
# define GPIO_USART3_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN10)
# define GPIO_USART3_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN11)
# define GPIO_USART3_CK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN12)
# define GPIO_USART3_CTS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN13)
# define GPIO_USART3_RTS (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN14)
#else
# define GPIO_USART3_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN10)
# define GPIO_USART3_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN11)
# define GPIO_USART3_CK (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN12)
# define GPIO_USART3_CTS (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTB | GPIO_PIN13)
# define GPIO_USART3_RTS (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTB | GPIO_PIN14)
#endif
#define GPIO_UART4_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN10)
#define GPIO_UART4_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTC | GPIO_PIN11)
#define GPIO_UART5_TX (GPIO_ALT | GPIO_CNF_AFPP | GPIO_MODE_50MHz | GPIO_PORTC | GPIO_PIN12)
#define GPIO_UART5_RX (GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT | GPIO_PORTD | GPIO_PIN2)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H */

2
arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
View File

@ -222,7 +222,7 @@
#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)

2
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
View File

@ -222,7 +222,7 @@
#define GPIO_ETH_MII_TX_EN_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
#define GPIO_ETH_PPS_OUT_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
#define GPIO_ETH_PPS_OUT_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
#define GPIO_ETH_RMII_CRS_DV (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
#define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
#define GPIO_ETH_RMII_RXD0 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
#define GPIO_ETH_RMII_RXD1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)

50
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@ -228,6 +228,27 @@ static inline void rcc_enableapb1(void)
#endif
#endif
#ifdef CONFIG_STM32_TIM12
/* Timer 12 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM12EN;
#endif
#endif
#ifdef CONFIG_STM32_TIM13
/* Timer 13 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM13EN;
#endif
#endif
#ifdef CONFIG_STM32_TIM14
/* Timer 14 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM14EN;
#endif
#endif
#ifdef CONFIG_STM32_WWDG
/* Window Watchdog clock enable */
@ -319,6 +340,13 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_DACEN;
#endif
#ifdef CONFIG_STM32_CEC
/* CEC clock enable */
regval |= RCC_APB1ENR_CECEN;
#endif
putreg32(regval, STM32_RCC_APB1ENR);
}
@ -408,6 +436,28 @@ static inline void rcc_enableapb2(void)
regval |= RCC_APB2ENR_ADC3EN;
#endif
#ifdef CONFIG_STM32_TIM15
/* TIM15 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM15EN;
#endif
#endif
#ifdef CONFIG_STM32_TIM16
/* TIM16 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM16EN;
#endif
#endif
#ifdef CONFIG_STM32_TIM17
/* TIM17 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM17EN;
#endif
#endif
putreg32(regval, STM32_RCC_APB2ENR);
}