SAMV7 USB: USB must be enabled before PMC 480MHz clock is enabled
This commit is contained in:
Gregory Nutt
parent
f3d1c19965
commit
2264c1fa64
@ -224,30 +224,26 @@ static inline void sam_pmcsetup(void)
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putreg32(BOARD_CKGR_PLLAR, SAM_PMC_CKGR_PLLAR);
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sam_pmcwait(PMC_INT_LOCKA);
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#ifdef CONFIG_USBDEV
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#ifdef CONFIG_SAMV7_USBDEVHS
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/* UTMI configuration: Enable port0, select 12/16 MHz MAINOSC crystal source */
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#if 0 /* REVISIT: Does this apply only to OHCI? */
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putreg32(UTMI_OHCIICR_RES0, SAM_UTMI_OHCIICR);
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#endif
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#if BOARD_MAINOSC_FREQUENCY == 12000000
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putreg32(UTMI_CKTRIM_FREQ_XTAL12, SAM_UTMI_CKTRIM);
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#elif BOARD_MAINOSC_FREQUENCY == 12000000
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#elif BOARD_MAINOSC_FREQUENCY == 16000000
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putreg32(UTMI_CKTRIM_FREQ_XTAL16, SAM_UTMI_CKTRIM);
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#else
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# error ERROR: Unrecognized MAINSOSC frequency
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#endif
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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/* Enable UTMI Clocking. The USBHS can work in two modes:
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*
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* - Normal mode where High speed, Full speed and Low speed are available.
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* - Low-power mode where only Full speed and Low speed are available.
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*
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* Only the normal mode is supported by this logic.
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* Only the Low-power mode is mode is supported by this logic.
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*/
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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/* UTMI Low-power mode, Full/Low Speed mode
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*
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* Enable the 48MHz FS Clock.
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@ -255,15 +251,6 @@ static inline void sam_pmcsetup(void)
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putreg32(PMC_USBCLK, SAM_PMC_SCER);
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#else
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/* UTMI normal mode, High/Full/Low Speed
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*
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* Disable the 48MHz USB FS Clock. It is not used in this configuration
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*/
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putreg32(PMC_USBCLK, SAM_PMC_SCDR);
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#endif
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/* Select the UTMI PLL as the USB PLL clock input (480MHz) with divider
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* to get to 48MHz. UPLL output frequency is determined only by the
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* 12/16MHz crystal selection above.
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@ -271,7 +258,6 @@ static inline void sam_pmcsetup(void)
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regval = PMC_USB_USBS_UPLL;
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#ifdef CONFIG_SAMV7_USBDEVHS_LOWPOWER
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if ((getreg32(SAM_PMC_MCKR) & PMC_MCKR_PLLADIV2) != 0)
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{
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/* Divider = 480 Mhz / 2 / 48 Mhz = 5 */
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@ -284,7 +270,6 @@ static inline void sam_pmcsetup(void)
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regval |= PMC_USB_USBDIV(9);
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}
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#endif
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putreg32(regval, SAM_PMC_USB);
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@ -296,7 +281,9 @@ static inline void sam_pmcsetup(void)
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/* Wait for LOCKU */
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sam_pmcwait(PMC_INT_LOCKU);
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#endif
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#endif /* CONFIG_SAMV7_USBDEVHS_LOWPOWER */
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#endif /* CONFIG_SAMV7_USBDEVHS */
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/* Switch to the fast clock and wait for MCKRDY */
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@ -405,3 +392,50 @@ void sam_clockconfig(void)
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sam_enabledefaultmaster();
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}
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/****************************************************************************
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* Name: sam_usbclock
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*
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* Description:
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* Enable USBHS clocking.
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*
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****************************************************************************/
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#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
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void sam_usbclock(void)
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{
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uint32_t regval;
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/* Enable UTMI Clocking. The USBHS can work in two modes:
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*
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* - Normal mode where High speed, Full speed and Low speed are available.
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* - Low-power mode where only Full speed and Low speed are available.
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*
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* Only the normal mode is supported by this logic.
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*/
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/* UTMI normal mode, High/Full/Low Speed
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*
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* Disable the 48MHz USB FS Clock. It is not used in this configuration
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*/
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putreg32(PMC_USBCLK, SAM_PMC_SCDR);
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/* Select the UTMI PLL as the USB PLL clock input (480MHz) with a divider
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* of 1. UPLL output frequency is determined only by the 12/16MHz crystal
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* selection set in sam_clockconfig().
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*/
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putreg32(PMC_USB_USBS_UPLL, SAM_PMC_USB);
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/* Enable the UTMI PLL with the maximum start-up time */
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regval = PMC_CKGR_UCKR_UPLLEN | PMC_CKGR_UCKR_UPLLCOUNT_MAX;
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putreg32(regval, SAM_PMC_CKGR_UCKR);
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/* Wait for LOCKU */
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sam_pmcwait(PMC_INT_LOCKU);
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}
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#endif /* CONFIG_SAMV7_USBDEVHS && !CONFIG_SAMV7_USBDEVHS_LOWPOWER */
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@ -85,6 +85,20 @@ extern "C"
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void sam_clockconfig(void);
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/****************************************************************************
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* Name: sam_usbclock
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*
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* Description:
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* Enable USBHS clocking.
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*
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****************************************************************************/
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#if defined(CONFIG_SAMV7_USBDEVHS) && !defined(CONFIG_SAMV7_USBDEVHS_LOWPOWER)
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void sam_usbclock(void);
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#else
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# define sam_usbclock()
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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@ -74,6 +74,7 @@
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#include "sam_periphclks.h"
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#include "chip/sam_usbhs.h"
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#include "sam_clockconfig.h"
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#include "sam_usbdev.h"
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#if defined(CONFIG_USBDEV) && defined(CONFIG_SAMV7_USBDEVHS)
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@ -2832,14 +2833,14 @@ static int sam_usbhs_interrupt(int irq, void *context)
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sam_putreg(USBHS_DEVINT_SUSPD | USBHS_DEVINT_WAKEUP, SAM_USBHS_DEVICR);
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/* Inform board logic that USB is suspended */
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sam_suspend(priv);
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/* Re-freeze the clock */
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regval |= USBHS_CTRL_FRZCLK;
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sam_putreg(regval, SAM_USBHS_CTRL);
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/* Inform board logic that USB is suspended */
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sam_suspend(priv);
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}
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/* SOF interrupt */
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@ -4325,6 +4326,10 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
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regval &= ~USBHS_CTRL_USBE;
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sam_putreg(regval, SAM_USBHS_CTRL);
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/* Configure USBHS pins. Nothing needs to be done: HDM and HDP are the
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* primary pin functions and there are not alternatives.
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*/
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/* Enable clocking to the USBHS peripheral.
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*
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* The clock for the USBHS bus interface is generated by the Power
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@ -4346,7 +4351,7 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
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* 3. Enable the UPLL 480 MHz.
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* 4. Wait for the UPLL 480 MHz to be considered as locked by the PMC.
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*
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* Steps 1,3, and 4 were performed in sam_clockconfig.c.
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* Steps 3 and 4 are performed in sam_usbclock.c.
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*/
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/* Enable the USBHS peripheral clock (PMC_PCER) */
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@ -4366,6 +4371,10 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
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regval &= ~USBHS_CTRL_FRZCLK;
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sam_putreg(regval, SAM_USBHS_CTRL);
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/* Enable the UPLL */
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sam_usbclock();
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/* Select High Speed or force Full Speed */
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regval = sam_getreg(SAM_USBHS_DEVCTRL);
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