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The Nucleo-F401RE has no on-board cystal and, hence, must use the on-chip HSI oscillator for the PLL include clock

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This commit is contained in:
Gregory Nutt 2014-05-06 10:01:02 -06:00
parent f2ac4d6403
commit 22733f9a79
5 changed files with 134 additions and 82 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
ChangeLog
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@ -7294,3 +7294,6 @@
Bob Doiron (2014-5-5).
* binfmt/symtab_findorderedbyname.c: Fix an error in the symbol search
function. Noted by Pelle Windestam (2014-5-6).
* arch/arm/src/stm32/stm32f40xxx_rcc.c and configs/nucleo-f401re/include/board.h:
The Nucleo-F401RE has no on-board crystals and, hence, needs to run
with the PLL input from the on-chip HSI clock (2014-5-6).

38
arch/arm/src/stm32/stm32f40xxx_rcc.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32f40xxx_rcc.c
*
* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
* Copyright (C) 2011-2012, 2014 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -51,6 +51,10 @@
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
/* Same for HSI */
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
/****************************************************************************
* Private Data
****************************************************************************/
@ -81,10 +85,10 @@ static inline void rcc_reset(void)
putreg32(0x00000000, STM32_RCC_CFGR);
/* Reset HSEON, CSSON and PLLON bits */
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
regval &= ~(RCC_CR_HSION|RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@ -597,6 +601,27 @@ static void stm32_stdclockconfig(void)
uint32_t regval;
volatile int32_t timeout;
#ifdef STM32_BOARD_USEHSI
/* Enable Internal High-Speed Clock (HSI) */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_HSION; /* Enable HSI */
putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */
for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the HSIRDY flag is the set in the CR */
if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
break;
}
}
#else /* if STM32_BOARD_USEHSE */
/* Enable External High-Speed Clock (HSE) */
regval = getreg32(STM32_RCC_CR);
@ -616,6 +641,7 @@ static void stm32_stdclockconfig(void)
break;
}
}
#endif
/* Check for a timeout. If this timeout occurs, then we are hosed. We
* have no real back-up plan, although the following logic makes it look
@ -664,8 +690,13 @@ static void stm32_stdclockconfig(void)
/* Set the PLL dividers and multiplers to configure the main PLL */
#ifdef STM32_BOARD_USEHSI
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ);
#else /* if STM32_BOARD_USEHSE */
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
#endif
putreg32(regval, STM32_RCC_PLLCFG);
/* Enable the main PLL */
@ -696,7 +727,6 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
{
}
#endif
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */

12
configs/nucleo-f401re/README.txt
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@ -73,10 +73,8 @@ GNU Toolchain Options
If you change the default toolchain, then you may also have to modify the PATH in
the setenv.h file if your make cannot find the tools.
NOTE: the CodeSourcery (for Windows), Atollic, devkitARM, and Raisonance toolchains are
Windows native toolchains. The CodeSourcey (for Linux) and NuttX buildroot
toolchains are Cygwin and/or Linux native toolchains. There are several limitations
to using a Windows based toolchain in a Cygwin environment. The three biggest are:
NOTE: There are several limitations to using a Windows based toolchain in a
Cygwin environment. The three biggest are:
1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
performed automatically in the Cygwin makefiles using the 'cygpath' utility
@ -101,12 +99,6 @@ GNU Toolchain Options
MKDEP = $(TOPDIR)/tools/mknulldeps.sh
The CodeSourcery Toolchain (2009q1)
-----------------------------------
The CodeSourcery toolchain (2009q1) does not work with default optimization
level of -Os (See Make.defs). It will work with -O0, -O1, or -O2, but not with
-Os.
The Atollic "Pro" and "Lite" Toolchain
--------------------------------------
One problem that I had with the Atollic toolchains is that the provide a gcc.exe

92
configs/nucleo-f401re/include/board.h
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@ -53,21 +53,21 @@
************************************************************************************/
/* Clocking *************************************************************************/
/* The NUCLEO401RE uses a 24MHz crystal connected to the HSE.
/* The NUCLEO401RE supports both HSE and LSE crystals (X2 and X3). However, as
* shipped, the X2 and X3 crystals are not populated. Therefore the Nucleo-F401RE
* will need to run off the 16MHz HSI clock.
*
* This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
* System Clock source : PLL (HSE)
* SYSCLK(Hz) : 168000000 Determined by PLL configuration
* HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
* System Clock source : PLL (HSI)
* SYSCLK(Hz) : 84000000 Determined by PLL configuration
* HCLK(Hz) : 84000000 (STM32_RCC_CFGR_HPRE)
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
* APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
* APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
* HSE Frequency(Hz) : 24000000 (STM32_BOARD_XTAL)
* PLLM : 24 (STM32_PLLCFG_PLLM)
* APB1 Prescaler : 2 (STM32_RCC_CFGR_PPRE1)
* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2)
* HSI Frequency(Hz) : 16000000 (nominal)
* PLLM : 16 (STM32_PLLCFG_PLLM)
* PLLN : 336 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
* PLLP : 4 (STM32_PLLCFG_PLLP)
* PLLQ : 7 (STM32_PLLCFG_PPQ)
* Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
* Flash Latency(WS) : 5
* Prefetch Buffer : OFF
* Instruction cache : ON
@ -78,49 +78,68 @@
/* HSI - 16 MHz RC factory-trimmed
* LSI - 32 KHz RC
* HSE - On-board crystal frequency is 24MHz
* HSE - not installed
* LSE - not installed
*/
#define STM32_BOARD_XTAL 24000000ul
#define STM32_HSI_FREQUENCY 16000000ul
#define STM32_LSI_FREQUENCY 32000
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
//#define STM32_LSE_FREQUENCY 32768
#define STM32_BOARD_USEHSI 1
/* Main PLL Configuration.
*
* PLL source is HSE
* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
* = (25,000,000 / 25) * 336
* Formulae:
*
* VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63
* VCO output frequency = VCO input frequency × PLLN, 192 <= PLLN <= 432
* PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8
* USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15
*
* We would like to have SYSYCLK=84MHz and we must have the USB clock= 48MHz.
* Some possible solutions include:
*
* PLLN=210 PLLM=5 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
* PLLN=210 PLLM=10 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
* PLLN=336 PLLM=8 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
* PLLN=336 PLLM=16 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
* PLLN=420 PLLM=10 PLLP=8 PLLQ=14 SYSCLK=84000000 OTGFS=48000000
* PLLN=420 PLLM=20 PLLP=4 PLLQ=7 SYSCLK=84000000 OTGFS=48000000
*
* We will configure like this
*
* PLL source is HSI
* PLL_VCO = (STM32_HSI_FREQUENCY / PLLM) * PLLN
* = (16,000,000 / 16) * 336
* = 336,000,000
* SYSCLK = PLL_VCO / PLLP
* = 336,000,000 / 2 = 168,000,000
* USB OTG FS, SDIO and RNG Clock
* = 336,000,000 / 4 = 84,000,000
* USB OTG FS and SDIO Clock
* = PLL_VCO / PLLQ
* = 48,000,000
* = 336,000,000 / 7 = 48,000,000
*
* REVISIT: Trimming of the HSI is not yet supported.
*/
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(24)
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(16)
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
#define STM32_SYSCLK_FREQUENCY 168000000ul
#define STM32_SYSCLK_FREQUENCY 84000000ul
/* AHB clock (HCLK) is SYSCLK (168MHz) */
/* AHB clock (HCLK) is SYSCLK (84MHz) */
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
/* APB1 clock (PCLK1) is HCLK/2 (42MHz) */
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
/* Timers driven from APB1 will be twice PCLK1 */
/* REVISIT */
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
@ -132,12 +151,13 @@
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
/* APB2 clock (PCLK2) is HCLK (84MHz) */
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/1)
/* Timers driven from APB2 will be twice PCLK2 */
/* REVISIT */
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
@ -149,6 +169,7 @@
* otherwise frequency is 2xAPBx.
* Note: TIM1,8 are on APB2, others on APB1
*/
/* REVISIT */
#define STM32_TIM18_FREQUENCY (2*STM32_PCLK2_FREQUENCY)
#define STM32_TIM27_FREQUENCY (2*STM32_PCLK1_FREQUENCY)
@ -160,12 +181,14 @@
*
* HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz
*/
/* REVISIT */
#define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT)
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
/* REVISIT */
#ifdef CONFIG_SDIO_DMA
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
@ -176,6 +199,7 @@
/* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz
* DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz
*/
/* REVISIT */
#ifdef CONFIG_SDIO_DMA
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
@ -183,7 +207,7 @@
# define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT)
#endif
/* DMA Channl/Stream Selections *****************************************************/
/* DMA Channel/Stream Selections ****************************************************/
/* Stream selections are arbitrary for now but might become important in the future
* is we set aside more DMA channels/streams.
*

49
configs/nucleo-f401re/nsh/defconfig
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@ -12,10 +12,6 @@ CONFIG_HOST_LINUX=y
# CONFIG_HOST_OSX is not set
# CONFIG_HOST_WINDOWS is not set
# CONFIG_HOST_OTHER is not set
# CONFIG_WINDOWS_NATIVE is not set
# CONFIG_WINDOWS_CYGWIN is not set
# CONFIG_WINDOWS_MSYS is not set
# CONFIG_WINDOWS_OTHER is not set
#
# Build Configuration
@ -113,16 +109,10 @@ CONFIG_ARCH_HAVE_MPU=y
#
# ARMV7M Configuration Options
#
# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set
# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL=y
# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set
# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set
# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
# CONFIG_SERIAL_TERMIOS is not set
#
@ -227,15 +217,37 @@ CONFIG_STM32_STM32F401=y
#
# STM32 Peripheral Support
#
# CONFIG_STM32_HAVE_CCM is not set
# CONFIG_STM32_HAVE_USBDEV is not set
CONFIG_STM32_HAVE_OTGFS=y
# CONFIG_STM32_HAVE_FSMC is not set
# CONFIG_STM32_HAVE_USART3 is not set
# CONFIG_STM32_HAVE_USART4 is not set
# CONFIG_STM32_HAVE_USART5 is not set
CONFIG_STM32_HAVE_USART6=y
# CONFIG_STM32_HAVE_USART7 is not set
# CONFIG_STM32_HAVE_USART8 is not set
CONFIG_STM32_HAVE_TIM1=y
CONFIG_STM32_HAVE_TIM5=y
# CONFIG_STM32_HAVE_TIM6 is not set
# CONFIG_STM32_HAVE_TIM7 is not set
# CONFIG_STM32_HAVE_TIM8 is not set
CONFIG_STM32_HAVE_TIM9=y
CONFIG_STM32_HAVE_TIM10=y
CONFIG_STM32_HAVE_TIM11=y
# CONFIG_STM32_HAVE_TIM12 is not set
# CONFIG_STM32_HAVE_TIM13 is not set
# CONFIG_STM32_HAVE_TIM14 is not set
# CONFIG_STM32_HAVE_TIM15 is not set
# CONFIG_STM32_HAVE_TIM16 is not set
# CONFIG_STM32_HAVE_TIM17 is not set
# CONFIG_STM32_HAVE_ADC2 is not set
# CONFIG_STM32_HAVE_ADC3 is not set
# CONFIG_STM32_HAVE_ADC4 is not set
# CONFIG_STM32_HAVE_CAN1 is not set
# CONFIG_STM32_HAVE_CAN2 is not set
# CONFIG_STM32_ADC1 is not set
# CONFIG_STM32_ADC2 is not set
# CONFIG_STM32_ADC3 is not set
# CONFIG_STM32_BKPSRAM is not set
# CONFIG_STM32_CAN1 is not set
# CONFIG_STM32_CAN2 is not set
# CONFIG_STM32_CCMDATARAM is not set
# CONFIG_STM32_CRC is not set
# CONFIG_STM32_CRYP is not set
@ -263,20 +275,11 @@ CONFIG_STM32_SYSCFG=y
# CONFIG_STM32_TIM3 is not set
# CONFIG_STM32_TIM4 is not set
# CONFIG_STM32_TIM5 is not set
# CONFIG_STM32_TIM6 is not set
# CONFIG_STM32_TIM7 is not set
# CONFIG_STM32_TIM8 is not set
# CONFIG_STM32_TIM9 is not set
# CONFIG_STM32_TIM10 is not set
# CONFIG_STM32_TIM11 is not set
# CONFIG_STM32_TIM12 is not set
# CONFIG_STM32_TIM13 is not set
# CONFIG_STM32_TIM14 is not set
# CONFIG_STM32_USART1 is not set
CONFIG_STM32_USART2=y
# CONFIG_STM32_USART3 is not set
# CONFIG_STM32_UART4 is not set
# CONFIG_STM32_UART5 is not set
# CONFIG_STM32_USART6 is not set
# CONFIG_STM32_IWDG is not set
# CONFIG_STM32_WWDG is not set