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A10: Re-write of interrupt management logic

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This commit is contained in:
Gregory Nutt 2013-12-09 07:47:15 -06:00
parent 0e54839bf7
commit 227cddccfa
2 changed files with 156 additions and 212 deletions
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279
arch/arm/src/a1x/a1x_irq.c
View File

@ -174,14 +174,6 @@ void up_irqinitialize(void)
current_regs = NULL;
#ifndef CONFIG_SUPPRESS_INTERRUPTS
/* Initialize logic to support a second level of interrupt decoding for
* PIO pins.
*/
#ifdef CONFIG_A1X_GPIO_IRQ
a1x_gpio_irqinitialize();
#endif
/* And finally, enable interrupts */
(void)irqenable();
@ -205,6 +197,14 @@ void up_irqinitialize(void)
uint32_t *arm_decodeirq(uint32_t *regs)
{
/* REVISIT: I think that if you want to have prioritized interrupts, you
* would have to get the highest priority pending interrupt from the VECTOR
* register. But, in that case, you would also need to clear the pending
* interrupt by reading the PEND register. However, won't that clear up
* to 32 pending interrupts?
*/
#if 0 /* Use PEND registers instead */
uint32_t regval;
/* During initialization, the BASE address register was set to zero.
@ -214,14 +214,92 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(A1X_INTC_VECTOR);
/* REVISIT: I am thinking that we need to read the PEND0-2 registers
* in order to clear the pending interrupt.
*/
#warning Missing logic
/* Dispatch the interrupt */
return arm_doirq((int)(regval >> 2), regs);
#else
uintptr_t regaddr;
uint32_t pending;
int startirq;
int lastirq;
int irq;
/* Check each PEND register for pending interrupts. Since the unused
* interrupts are disabled, we do not have to be concerned about which
* are MASKed.
*/
for (startirq = 0, regaddr = A1X_INTC_IRQ_PEND0;
startirq < A1X_IRQ_NINT;
startirq += 32, regaddr += 4)
{
/* Check this register for pending interrupts */
pending = getreg32(regaddr);
if (pending != 0)
{
/* The last interrupt in this register */
lastirq = startirq + 32;
if (lastirq > A1X_IRQ_NINT)
{
lastirq = A1X_IRQ_NINT;
}
for (irq = startirq; irq < lastirq && pending != 0; )
{
/* Check for pending interrupts in any of the lower 16-bits */
if ((pending & 0x0000ffff) == 0)
{
irq += 16;
pending >>= 16;
}
/* Check for pending interrupts in any of the lower 16-bits */
else if ((pending & 0x000000ff) == 0)
{
irq += 8;
pending >>= 8;
}
/* Check for pending interrupts in any of the lower 4-bits */
else if ((pending & 0x0000000f) == 0)
{
irq += 4;
pending >>= 4;
}
/* Check for pending interrupts in any of the lower 2-bits */
else if ((pending & 0x00000003) == 0)
{
irq += 2;
pending >>= 2;
}
/* Check for pending interrupts in any of the last bits */
else
{
if ((pending & 0x00000001) == 0)
{
/* Yes.. dispatch the interrupt */
regs = arm_doirq(irq, regs);
}
irq++;
pending >>= 1;
}
}
}
}
return regs;
#endif
}
/****************************************************************************
@ -235,71 +313,32 @@ uint32_t *arm_decodeirq(uint32_t *regs)
void up_disable_irq(int irq)
{
irqstate_t flags;
uintptr_t enabreg;
uintptr_t maskreg;
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (irq < A1X_IRQ_NINT)
{
DEBUGASSERT(irg < 96);
/* These operations must be atomic */
flags = irqsave();
/* Select the register set associated with this irq */
/* Make sure that the interrupt is disabled. */
if (irq < 32)
{
enabreg = A1X_INTC_EN0;
maskreg = A1X_INTC_MASK0;
bit = irq;
}
else if (irq < 64)
{
enabreg = A1X_INTC_EN1;
maskreg = A1X_INTC_MASK1;
bit = irq - 32;
}
else if (irq < 64)
{
enabreg = A1X_INTC_EN2;
maskreg = A1X_INTC_MASK2;
bit = irq - 64;
}
else
{
/* Will not happen */
return;
}
regaddr = A1X_INTC_EN(irq);
regval = getreg32(regaddr);
regval &= ~INTC_EN(irq);
putreg32(regval, regaddr);
/* Mask the interrupt by setting the bit in the mask register */
regval = getreg32(maskreg);
regval |= (1 << bit);
putreg32(regval, maskreg);
/* Make sure that the interrupt is enabled. The interrupt must still
* be enabled in order for interrupts to pend while masked.
*/
regval = getreg32(enabreg);
regval |= (1 << bit);
putreg32(regval, enabreg);
regaddr = A1X_INTC_MASK(irq);
regval = getreg32(regaddr);
regval |= INTC_MASK(irq);
putreg32(regval, regaddr);
a1x_dumpintc("disable", irq);
irqrestore(flags);
}
#ifdef CONFIG_A1X_GPIO_IRQ
else
{
/* Maybe it is a (derived) PIO IRQ */
a1x_gpio_irqdisable(irq);
}
#endif
}
/****************************************************************************
@ -313,10 +352,8 @@ void up_disable_irq(int irq)
void up_enable_irq(int irq)
{
irqstate_t flags;
uintptr_t enabreg;
uintptr_t maskreg;
uintptr_t regaddr;
uint32_t regval;
uint32_t bit;
if (irq < A1X_IRQ_NINT)
{
@ -324,73 +361,23 @@ void up_enable_irq(int irq)
flags = irqsave();
/* Select the register set associated with this irq */
if (irq < 32)
{
enabreg = A1X_INTC_EN0;
maskreg = A1X_INTC_MASK0;
bit = irq;
}
else if (irq < 64)
{
enabreg = A1X_INTC_EN1;
maskreg = A1X_INTC_MASK1;
bit = irq - 32;
}
else if (irq < 64)
{
enabreg = A1X_INTC_EN2;
maskreg = A1X_INTC_MASK2;
bit = irq - 64;
}
else
{
/* Will not happen */
return;
}
/* Make sure that the interrupt is enabled. */
regval = getreg32(enabreg);
regval |= (1 << bit);
putreg32(regval, enabreg);
regaddr = A1X_INTC_EN(irq);
regval = getreg32(regaddr);
regval |= INTC_EN(irq);
putreg32(regval, regaddr);
/* Un-mask the interrupt by clearing the bit in the mask register */
regval = getreg32(maskreg);
regval &= ~(1 << bit);
putreg32(regval, maskreg);
regaddr = A1X_INTC_MASK(irq);
regval = getreg32(regaddr);
regval &= ~INTC_MASK(irq);
putreg32(regval, regaddr);
a1x_dumpintc("enable", irq);
irqrestore(flags);
}
#ifdef CONFIG_A1X_GPIO_IRQ
else
{
/* Maybe it is a (derived) PIO IRQ */
a1x_gpio_irqenable(irq);
}
#endif
}
/****************************************************************************
* Name: up_ack_irq
*
* Description:
* Acknowledge the interrupt
*
****************************************************************************/
void up_ack_irq(int irq)
{
/* It is not clear to me how the interrupts are acknowledge. Perhaps it
* is simply by reading the IRQ pending register? If so, where is that
* done?
*/
#warning Missing logic
}
/****************************************************************************
@ -407,9 +394,9 @@ void up_maskack_irq(int irq)
up_disable_irq(irq);
/* Then acknowledge it */
up_ack_irq(irq);
/* There is no need to acknowledge the interrupt. The pending interrupt
* was cleared in arm_decodeirq() when the PEND register was read.
*/
}
/****************************************************************************
@ -429,7 +416,6 @@ int up_prioritize_irq(int irq, int priority)
irqstate_t flags;
uintptr_t regaddr;
uint32_t regval;
int offset;
DEBUGASSERT(irq < A1X_IRQ_NINT && (unsigned)priority <= INTC_PRIO_MAX);
if (irq < A1X_IRQ_NINT)
@ -438,45 +424,12 @@ int up_prioritize_irq(int irq, int priority)
flags = irqsave();
/* Select the register set associated with this irq */
if (irq < 16)
{
regaddr = A1X_INTC_PRIO0;
offset = irq;
}
else if (irq < 32)
{
regaddr = A1X_INTC_PRIO1;
offset = irq - 16;
}
else if (irq < 48)
{
regaddr = A1X_INTC_PRIO2;
offset = irq - 32;
}
else if (irq < 64)
{
regaddr = A1X_INTC_PRIO3;
offset = irq - 48;
}
else if (irq < 80)
{
regaddr = A1X_INTC_PRIO4;
offset = irq - 64;
}
else
{
/* Should not happen */
return -EINVAL;
}
/* Set the new priority */
regaddr = A1X_INTC_PRIO_OFFSET(irq);
regval = getreg32(regaddr);
regval &= ~INTC_PRIO_MASK(offset);
regval |= INTC_PRIO(offset, priority);
regval &= ~INTC_PRIO_MASK(irq);
regval |= INTC_PRIO(irq, priority);
putreg32(regval, regaddr);
a1x_dumpintc("prioritize", irq);

89
arch/arm/src/a1x/chip/a1x_intc.h
View File

@ -53,27 +53,43 @@
#define A1X_INTC_BASEADDR_OFFSET 0x0004 /* Interrupt Base Address */
#define A1X_INTC_PROTECT_OFFSET 0x0008 /* Interrupt Protection Register */
#define A1X_INTC_NMICTRL_OFFSET 0x000c /* Interrupt Control */
#define A1X_INTC_IRQ_PEND_OFFSET(n) (0x0010 + (((n) >> 3) & ~3))
#define A1X_INTC_IRQ_PEND0_OFFSET 0x0010 /* Interrupt IRQ Pending 0 Status */
#define A1X_INTC_IRQ_PEND1_OFFSET 0x0014 /* Interrupt IRQ Pending 1 Status */
#define A1X_INTC_IRQ_PEND2_OFFSET 0x0018 /* Interrupt IRQ Pending 2 Status */
#define A1X_INTC_FIQ_PEND_OFFSET(n) (0x0020 + (((n) >> 3) & ~3))
#define A1X_INTC_FIQ_PEND0_OFFSET 0x0020 /* Interrupt FIQ Pending 0 Status */
#define A1X_INTC_FIQ_PEND1_OFFSET 0x0024 /* Interrupt FIQ Pending 1 Status */
#define A1X_INTC_FIQ_PEND2_OFFSET 0x0028 /* Interrupt FIQ Pending 2 Status */
#define A1X_INTC_FIRQ_SEL_OFFSET(n) (0x0030 + (((n) >> 3) & ~3))
#define A1X_INTC_IRQ_SEL0_OFFSET 0x0030 /* Interrupt Select 0 */
#define A1X_INTC_IRQ_SEL1_OFFSET 0x0034 /* Interrupt Select 1 */
#define A1X_INTC_IRQ_SEL2_OFFSET 0x0038 /* Interrupt Select 2 */
#define A1X_INTC_EN_OFFSET(n) (0x0040 + (((n) >> 3) & ~3))
#define A1X_INTC_EN0_OFFSET 0x0040 /* Interrupt Enable 0 */
#define A1X_INTC_EN1_OFFSET 0x0044 /* Interrupt Enable 1 */
#define A1X_INTC_EN2_OFFSET 0x0048 /* Interrupt Enable 2 */
#define A1X_INTC_MASK_OFFSET(n) (0x0050 + (((n) >> 3) & ~3))
#define A1X_INTC_MASK0_OFFSET 0x0050 /* Interrupt Mask 0 */
#define A1X_INTC_MASK1_OFFSET 0x0054 /* Interrupt Mask 1 */
#define A1X_INTC_MASK2_OFFSET 0x0058 /* Interrupt Mask 2 */
#define A1X_INTC_RESP_OFFSET(n) (0x0060 + (((n) >> 3) & ~3))
#define A1X_INTC_RESP0_OFFSET 0x0060 /* Interrupt Response 0 */
#define A1X_INTC_RESP1_OFFSET 0x0064 /* Interrupt Response 1 */
#define A1X_INTC_RESP2_OFFSET 0x0068 /* Interrupt Response 2 */
#define A1X_INTC_FF_OFFSET(n) (0x0070 + (((n) >> 3) & ~3))
#define A1X_INTC_FF0_OFFSET 0x0070 /* Interrupt Fast Forcing 0 */
#define A1X_INTC_FF1_OFFSET 0x0074 /* Interrupt Fast Forcing 1 */
#define A1X_INTC_FF2_OFFSET 0x0078 /* Interrupt Fast Forcing 2 */
#define A1X_INTC_PRIO_OFFSET(n) (0x0080 + (((n) >> 2) & ~3))
#define A1X_INTC_PRIO0_OFFSET 0x0080 /* Interrupt Source Priority 0 */
#define A1X_INTC_PRIO1_OFFSET 0x0084 /* Interrupt Source Priority 1 */
#define A1X_INTC_PRIO2_OFFSET 0x0088 /* Interrupt Source Priority 2 */
@ -86,27 +102,43 @@
#define A1X_INTC_BASEADDR (A1X_INTC_VADDR+A1X_INTC_BASEADDR_OFFSET)
#define A1X_INTC_PROTECT (A1X_INTC_VADDR+A1X_INTC_PROTECT_OFFSET)
#define A1X_INTC_NMICTRL (A1X_INTC_VADDR+A1X_INTC_NMICTRL_OFFSET)
#define A1X_INTC_IRQ_PEND(n) (A1X_INTC_VADDR+A1X_INTC_IRQ_PEND_OFFSET(n))
#define A1X_INTC_IRQ_PEND0 (A1X_INTC_VADDR+A1X_INTC_IRQ_PEND0_OFFSET)
#define A1X_INTC_IRQ_PEND1 (A1X_INTC_VADDR+A1X_INTC_IRQ_PEND1_OFFSET)
#define A1X_INTC_IRQ_PEND2 (A1X_INTC_VADDR+A1X_INTC_IRQ_PEND2_OFFSET)
#define A1X_INTC_FIQ_PEND(n) (A1X_INTC_VADDR+A1X_INTC_FIQ_PEND_OFFSET(n))
#define A1X_INTC_FIQ_PEND0 (A1X_INTC_VADDR+A1X_INTC_FIQ_PEND0_OFFSET)
#define A1X_INTC_FIQ_PEND1 (A1X_INTC_VADDR+A1X_INTC_FIQ_PEND1_OFFSET)
#define A1X_INTC_FIQ_PEND2 (A1X_INTC_VADDR+A1X_INTC_FIQ_PEND2_OFFSET)
#define A1X_INTC_IRQ_SEL(n) (A1X_INTC_VADDR+A1X_INTC_IRQ_SEL_OFFSET(n))
#define A1X_INTC_IRQ_SEL0 (A1X_INTC_VADDR+A1X_INTC_IRQ_SEL0_OFFSET)
#define A1X_INTC_IRQ_SEL1 (A1X_INTC_VADDR+A1X_INTC_IRQ_SEL1_OFFSET)
#define A1X_INTC_IRQ_SEL2 (A1X_INTC_VADDR+A1X_INTC_IRQ_SEL2_OFFSET)
#define A1X_INTC_EN(n) (A1X_INTC_VADDR+A1X_INTC_EN_OFFSET(n))
#define A1X_INTC_EN0 (A1X_INTC_VADDR+A1X_INTC_EN0_OFFSET)
#define A1X_INTC_EN1 (A1X_INTC_VADDR+A1X_INTC_EN1_OFFSET)
#define A1X_INTC_EN2 (A1X_INTC_VADDR+A1X_INTC_EN2_OFFSET)
#define A1X_INTC_MASK(n) (A1X_INTC_VADDR+A1X_INTC_MASK_OFFSET(n))
#define A1X_INTC_MASK0 (A1X_INTC_VADDR+A1X_INTC_MASK0_OFFSET)
#define A1X_INTC_MASK1 (A1X_INTC_VADDR+A1X_INTC_MASK1_OFFSET)
#define A1X_INTC_MASK2 (A1X_INTC_VADDR+A1X_INTC_MASK2_OFFSET)
#define A1X_INTC_RESP(n) (A1X_INTC_VADDR+A1X_INTC_RESP_OFFSET(n))
#define A1X_INTC_RESP0 (A1X_INTC_VADDR+A1X_INTC_RESP0_OFFSET)
#define A1X_INTC_RESP1 (A1X_INTC_VADDR+A1X_INTC_RESP1_OFFSET)
#define A1X_INTC_RESP2 (A1X_INTC_VADDR+A1X_INTC_RESP2_OFFSET)
#define A1X_INTC_FF(n) (A1X_INTC_VADDR+A1X_INTC_FF_OFFSET(n))
#define A1X_INTC_FF0 (A1X_INTC_VADDR+A1X_INTC_FF0_OFFSET)
#define A1X_INTC_FF1 (A1X_INTC_VADDR+A1X_INTC_FF1_OFFSET)
#define A1X_INTC_FF2 (A1X_INTC_VADDR+A1X_INTC_FF2_OFFSET)
#define A1X_INTC_PRIO(n) (A1X_INTC_VADDR+A1X_INTC_PRIO_OFFSET(n))
#define A1X_INTC_PRIO0 (A1X_INTC_VADDR+A1X_INTC_PRIO0_OFFSET)
#define A1X_INTC_PRIO1 (A1X_INTC_VADDR+A1X_INTC_PRIO1_OFFSET)
#define A1X_INTC_PRIO2 (A1X_INTC_VADDR+A1X_INTC_PRIO2_OFFSET)
@ -136,80 +168,39 @@
/* Interrupt IRQ Pending 0-2 Status */
#define INTC_IRQ_PEND(n) (1 << (n)) /* n=0-31: Interrupt pending */
# define INTC_IRQ_PEND0(n) (1 << (n)) /* n=0-31: Interrupt pending */
# define INTC_IRQ_PEND1(n) (1 << ((n) - 32)) /* n=32-63: Interrupt pending */
# define INTC_IRQ_PEND2(n) (1 << ((n) - 64)) /* n=64-95: Interrupt pending */
#define INTC_IRQ_PEND(n) (1 << ((n) & 0x1f)) /* n=0-95: Interrupt pending */
/* Interrupt FIQ Pending 0-2 Status */
#define INTC_FIQ_PEND(n) (1 << (n)) /* n=0-31: Interrupt pending */
# define INTC_FIQ_PEND0(n) (1 << (n)) /* n=0-31: Interrupt pending */
# define INTC_FIQ_PEND1(n) (1 << ((n) - 32)) /* n=32-63: Interrupt pending */
# define INTC_FIQ_PEND2(n) (1 << ((n) - 64)) /* n=64-95: Interrupt pending */
#define INTC_FIQ_PEND(n) (1 << ((n) & 0x1f)) /* n=0-95: Interrupt pending */
/* Interrupt Select 0-2 */
#define INTC_IRQ_SEL(n) (1 << (n)) /* n=0-31: FIQ (vs IRQ) */
# define INTC_IRQ_SEL0(n) (1 << (n)) /* n=0-31: FIQ (vs IRQ) */
# define INTC_IRQ_SEL1(n) (1 << ((n) - 32)) /* n=32-63: FIQ (vs IRQ) */
# define INTC_IRQ_SEL2(n) (1 << ((n) - 64)) /* n=64-95: FIQ (vs IRQ) */
#define INTC_IRQ_SEL(n) (1 << ((n) & 0x1f)) /* n=0-95: FIQ (vs IRQ) */
/* Interrupt Enable 0-2 */
#define INTC_EN(n) (1 << (n)) /* n=0-31: Interrupt enable */
# define INTC_EN0(n) (1 << (n)) /* n=0-31: Interrupt enable */
# define INTC_EN1(n) (1 << ((n) - 32)) /* n=32-63: Interrupt enable */
# define INTC_EN2(n) (1 << ((n) - 64)) /* n=64-95: Interrupt enable */
#define INTC_EN(n) (1 << ((n) & 0x1f)) /* n=0-95: Interrupt enable */
/* Interrupt Mask 0-2 */
#define INTC_MASK(n) (1 << (n)) /* n=0-31: Interrupt mask */
# define INTC_MASK0(n) (1 << (n)) /* n=0-31: Interrupt mask */
# define INTC_MASK1(n) (1 << ((n) - 32)) /* n=32-63: Interrupt mask */
# define INTC_MASK2(n) (1 << ((n) - 64)) /* n=64-95: Interrupt mask */
#define INTC_MASK(n) (1 << ((n) & 0x1f)) /* n=0-95: Interrupt mask */
/* Interrupt Response 0-2 */
#define INTC_RESP(n) (1 << (n)) /* n=0-31: Interrupt level mask */
# define INTC_RESP0(n) (1 << (n)) /* n=0-31: Interrupt level mask */
# define INTC_RESP1(n) (1 << ((n) - 32)) /* n=32-63: Interrupt level mask */
# define INTC_RESP2(n) (1 << ((n) - 64)) /* n=64-95: Interrupt level mask */
#define INTC_RESP(n) (1 << ((n) & 0x1f)) /* n=0-95: Interrupt level mask */
/* Interrupt Fast Forcing 0-2 */
#define INTC_FF(n) (1 << (n)) /* n=0-31: Enable fast forcing feature */
# define INTC_FF0(n) (1 << (n)) /* n=0-31: Enable fast forcing feature */
# define INTC_FF1(n) (1 << ((n) - 32)) /* n=32-63: Enable fast forcing feature */
# define INTC_FF2(n) (1 << ((n) - 64)) /* n=64-95: Enable fast forcing feature */
#define INTC_FF(n) (1 << ((n) & 0x1f)) /* n=0-95: Enable fast forcing feature */
/* Interrupt Source Priority 0-4 */
#define INTC_PRIO_MIN 0
#define INTC_PRIO_MAX 3
#define INTC_PRIO_SHIFT(n) ((n) << 1) /* n=0-15: Priority level */
#define INTC_PRIO_SHIFT(n) (((n) & 15) << 1) /* n=0-95: Priority level */
#define INTC_PRIO_MASK(n) (3 << INTC_PRIO_SHIFT(n))
# define INTC_PRIO(n,p) ((uint32_t)(p) << INTC_PRIO_SHIFT(n))
#define INTC_PRIO0_SHIFT(n) ((n) << 1) /* n=0-15: Priority level */
#define INTC_PRIO0_MASK(n) (3 << INTC_PRIO0_SHIFT(n))
# define INTC_PRIO0(n,p) ((uint32_t)(p) << INTC_PRIO0_SHIFT(n))
#define INTC_PRIO1_SHIFT(n) (((n) - 16) << 1) /* n=16-31: Priority level */
#define INTC_PRIO1_MASK(n) (3 << INTC_PRIO1_SHIFT(n))
# define INTC_PRIO1(n,p) ((uint32_t)(p) << INTC_PRIO1_SHIFT(n))
#define INTC_PRIO2_SHIFT(n) (((n) - 32) << 1) /* n=32-47: Priority level */
#define INTC_PRIO2_MASK(n) (3 << INTC_PRIO2_SHIFT(n))
# define INTC_PRIO2(n,p) ((uint32_t)(p) << INTC_PRIO2_SHIFT(n))
#define INTC_PRIO3_SHIFT(n) (((n) - 48) << 1) /* n=48-63: Priority level */
#define INTC_PRIO3_MASK(n) (3 << INTC_PRIO3_SHIFT(n))
# define INTC_PRIO3(n,p) ((uint32_t)(p) << INTC_PRIO3_SHIFT(n))
#define INTC_PRIO4_SHIFT(n) (((n) - 64) << 1) /* n=64-79: Priority level */
#define INTC_PRIO4_MASK(n) (3 << INTC_PRIO4_SHIFT(n))
# define INTC_PRIO4(n,p) ((uint32_t)(p) << INTC_PRIO4_SHIFT(n))
#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_INTC_H */