arch/risc-v: Refine riscv_fpu.S
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Xiang Xiao
parent
6ce335fa84
commit
22ae2e0121
@ -1,5 +1,5 @@
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/************************************************************************************
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* arch/risc-v/src/rv64gc/riscv_fpu.S
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* arch/risc-v/src/common/riscv_fpu.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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@ -23,7 +23,12 @@
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************************************************************************************/
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#include <nuttx/config.h>
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#ifdef CONFIG_ARCH_RV32
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#include <arch/rv32im/irq.h>
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#else
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#include <arch/rv64gc/irq.h>
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#endif
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#ifdef CONFIG_ARCH_FPU
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@ -58,6 +63,14 @@
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# define FSTORE fsw
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#endif
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD lw
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# define REGSTORE sw
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#else
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# define REGLOAD ld
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# define REGSTORE sd
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -95,7 +108,7 @@ up_fpuconfig:
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* floating point registers.
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*
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* C Function Prototype:
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* void riscv_savefpu(uint64_t *regs);
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* void riscv_savefpu(uintptr_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area in which to save the floating point
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@ -109,7 +122,7 @@ up_fpuconfig:
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.type riscv_savefpu, function
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riscv_savefpu:
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ld t0, REG_INT_CTX(a0)
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REGLOAD t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_DIRTY
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@ -118,7 +131,7 @@ riscv_savefpu:
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and t0, t0, t1
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li t1, FS_CLEAN
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or t0, t0, t1
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sd t0, REG_INT_CTX(a0)
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REGSTORE t0, REG_INT_CTX(a0)
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/* Store all floating point registers */
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@ -156,7 +169,7 @@ riscv_savefpu:
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FSTORE f31, REG_F31(a0)
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frcsr t0
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sd t0, REG_FCSR(a0)
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REGSTORE t0, REG_FCSR(a0)
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1:
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ret
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@ -169,7 +182,7 @@ riscv_savefpu:
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* floating point registers.
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*
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* C Function Prototype:
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* void riscv_restorefpu(const uint64_t *regs);
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* void riscv_restorefpu(const uintptr_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area containing the floating point
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@ -184,7 +197,7 @@ riscv_savefpu:
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.type riscv_restorefpu, function
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riscv_restorefpu:
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ld t0, REG_INT_CTX(a0)
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REGLOAD t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_INITIAL
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@ -227,7 +240,7 @@ riscv_restorefpu:
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/* Store the floating point control and status register */
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ld t0, REG_FCSR(a0)
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REGLOAD t0, REG_FCSR(a0)
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fscsr t0
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1:
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@ -1,236 +0,0 @@
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/************************************************************************************
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* arch/risc-v/src/rv32im/riscv_fpu.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/rv32im/irq.h>
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#ifdef CONFIG_ARCH_FPU
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/************************************************************************************
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* Public Symbols
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************************************************************************************/
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.globl up_fpuconfig
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.globl riscv_savefpu
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.globl riscv_restorefpu
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.file "up_fpu.S"
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#define FS_MASK 0x6000
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#define FS_OFF 0x0000
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#define FS_INITIAL 0x2000
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#define FS_CLEAN 0x4000
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#define FS_DIRTY 0x6000
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#if defined(CONFIG_ARCH_DPFPU)
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# define FLOAD fld
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# define FSTORE fsd
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#elif defined(CONFIG_ARCH_QPFPU)
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# define FLOAD flq
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# define FSTORE fsq
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#else
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# define FLOAD flw
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# define FSTORE fsw
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: up_fpuconfig
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*
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* Description:
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* init fpu
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*
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* C Function Prototype:
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* void up_fpuconfig(void);
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* This function does not return anything explicitly.
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*
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************************************************************************************/
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.type up_fpuconfig, function
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up_fpuconfig:
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li a0, FS_INITIAL
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csrs mstatus, a0
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csrwi fcsr, 0
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ret
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/************************************************************************************
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* Name: riscv_savefpu
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*
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* Description:
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* Given the pointer to a register save area (in A0), save the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void riscv_savefpu(uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area in which to save the floating point
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* registers
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*
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* Returned Value:
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* None
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*
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************************************************************************************/
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.type riscv_savefpu, function
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riscv_savefpu:
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lw t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_DIRTY
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bne t2, t1, 1f
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li t1, ~FS_MASK
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and t0, t0, t1
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li t1, FS_CLEAN
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or t0, t0, t1
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sw t0, REG_INT_CTX(a0)
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/* Store all floating point registers */
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FSTORE f0, REG_F0(a0)
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FSTORE f1, REG_F1(a0)
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FSTORE f2, REG_F2(a0)
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FSTORE f3, REG_F3(a0)
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FSTORE f4, REG_F4(a0)
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FSTORE f5, REG_F5(a0)
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FSTORE f6, REG_F6(a0)
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FSTORE f7, REG_F7(a0)
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FSTORE f8, REG_F8(a0)
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FSTORE f9, REG_F9(a0)
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FSTORE f10, REG_F10(a0)
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FSTORE f11, REG_F11(a0)
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FSTORE f12, REG_F12(a0)
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FSTORE f13, REG_F13(a0)
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FSTORE f14, REG_F14(a0)
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FSTORE f15, REG_F15(a0)
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FSTORE f16, REG_F16(a0)
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FSTORE f17, REG_F17(a0)
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FSTORE f18, REG_F18(a0)
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FSTORE f19, REG_F19(a0)
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FSTORE f20, REG_F20(a0)
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FSTORE f21, REG_F21(a0)
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FSTORE f22, REG_F22(a0)
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FSTORE f23, REG_F23(a0)
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FSTORE f24, REG_F24(a0)
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FSTORE f25, REG_F25(a0)
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FSTORE f26, REG_F26(a0)
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FSTORE f27, REG_F27(a0)
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FSTORE f28, REG_F28(a0)
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FSTORE f29, REG_F29(a0)
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FSTORE f30, REG_F30(a0)
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FSTORE f31, REG_F31(a0)
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frcsr t0
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sw t0, REG_FCSR(a0)
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1:
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ret
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/************************************************************************************
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* Name: riscv_restorefpu
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*
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* Description:
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* Given the pointer to a register save area (in A0), restore the state of the
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* floating point registers.
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*
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* C Function Prototype:
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* void riscv_restorefpu(const uint32_t *regs);
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*
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* Input Parameters:
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* regs - A pointer to the register save area containing the floating point
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* registers.
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*
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* Returned Value:
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* This function does not return anything explicitly. However, it is called from
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* interrupt level assembly logic that assumes that r0 is preserved.
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*
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************************************************************************************/
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.type riscv_restorefpu, function
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riscv_restorefpu:
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lw t0, REG_INT_CTX(a0)
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li t1, FS_MASK
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and t2, t0, t1
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li t1, FS_INITIAL
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ble t2, t1, 1f
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/* Load all floating point registers */
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FLOAD f0, REG_F0(a0)
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FLOAD f1, REG_F1(a0)
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FLOAD f2, REG_F2(a0)
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FLOAD f3, REG_F3(a0)
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FLOAD f4, REG_F4(a0)
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FLOAD f5, REG_F5(a0)
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FLOAD f6, REG_F6(a0)
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FLOAD f7, REG_F7(a0)
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FLOAD f8, REG_F8(a0)
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FLOAD f9, REG_F9(a0)
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FLOAD f10, REG_F10(a0)
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FLOAD f11, REG_F11(a0)
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FLOAD f12, REG_F12(a0)
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FLOAD f13, REG_F13(a0)
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FLOAD f14, REG_F14(a0)
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FLOAD f15, REG_F15(a0)
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FLOAD f16, REG_F16(a0)
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FLOAD f17, REG_F17(a0)
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FLOAD f18, REG_F18(a0)
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FLOAD f19, REG_F19(a0)
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FLOAD f20, REG_F20(a0)
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FLOAD f21, REG_F21(a0)
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FLOAD f22, REG_F22(a0)
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FLOAD f23, REG_F23(a0)
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FLOAD f24, REG_F24(a0)
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FLOAD f25, REG_F25(a0)
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FLOAD f26, REG_F26(a0)
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FLOAD f27, REG_F27(a0)
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FLOAD f28, REG_F28(a0)
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FLOAD f29, REG_F29(a0)
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FLOAD f30, REG_F30(a0)
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FLOAD f31, REG_F31(a0)
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/* Store the floating point control and status register */
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lw t0, REG_FCSR(a0)
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fscsr t0
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1:
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ret
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#endif /* CONFIG_ARCH_FPU */
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