LPC17xx_40xx PWM multichannel support
USB no softconnect SocketCAN kconfig fixes
This commit is contained in:
Peter van der Perk
Xiang Xiao
parent
6ab76bfc7c
commit
22d41f6b9c
@ -172,6 +172,9 @@ config ARCH_FAMILY_LPC408X
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config LPC17_40_HAVE_SPIFI
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bool
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config LPC17_40_CAN
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bool
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menu "LPC17xx/LPC40xx Peripheral Support"
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config LPC17_40_MAINOSC
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@ -262,13 +265,13 @@ config LPC17_40_UART4
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config LPC17_40_CAN1
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bool "CAN1"
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select LPC17_40_CAN
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default n
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select CAN
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config LPC17_40_CAN2
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bool "CAN2"
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select LPC17_40_CAN
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default n
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select CAN
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config LPC17_40_SPI
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bool "SPI"
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@ -345,6 +348,7 @@ config LPC17_40_PWM0
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config LPC17_40_PWM1
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bool "PWM1"
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select ARCH_HAVE_PWM_MULTICHAN
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default n
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config LPC17_40_PWM1_PIN
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@ -356,6 +360,48 @@ config LPC17_40_PWM1_PIN
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If TIM1 is enabled for PWM usage, you also need specifies the timer output
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channel {1,..,4}
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config LPC17_40_PWM1_CHANNEL1
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bool "PWM1 Channel 1"
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default y
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 1, board has to define pin GPIO_PWM1p1
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config LPC17_40_PWM1_CHANNEL2
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bool "PWM1 Channel 2"
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default n
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 2, board has to define pin GPIO_PWM1p2
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config LPC17_40_PWM1_CHANNEL3
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bool "PWM1 Channel 3"
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default n
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 3, board has to define pin GPIO_PWM1p3
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config LPC17_40_PWM1_CHANNEL4
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bool "PWM1 Channel 4"
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default n
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 4, board has to define pin GPIO_PWM1p4
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config LPC17_40_PWM1_CHANNEL5
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bool "PWM1 Channel 5"
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default n
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 5, board has to define pin GPIO_PWM1p5
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config LPC17_40_PWM1_CHANNEL6
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bool "PWM1 Channel 6"
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default n
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depends on LPC17_40_PWM1
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---help---
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Enable PWM1 channel 6, board has to define pin GPIO_PWM1p6
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config LPC17_40_MCPWM
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bool "MCPWM"
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default n
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@ -649,7 +695,7 @@ config LPC17_40_ADC_NCHANNELS
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endmenu
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menu "CAN driver options"
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depends on LPC17_40_CAN1 || LPC17_40_CAN2
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depends on LPC17_40_CAN
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config LPC17_40_CAN1_BAUD
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int "CAN1 BAUD"
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@ -996,8 +1042,14 @@ config LPC17_40_USBDEV_NOVBUS
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---help---
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Define if the hardware implementation does not support the VBUS signal
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config LPC17_40_USBDEV_NOSOFTCONNECT
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bool "Disable Softconnect support"
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default n
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---help---
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Define if the hardware implementation does not support the Softconnect signal
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config LPC17_40_USBDEV_NOLED
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bool "Disable USB device LCD support"
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bool "Disable USB device LED support"
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default n
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---help---
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Define if the hardware implementation does not support the LED output
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@ -80,7 +80,7 @@ CHIP_CSRCS += lpc17_40_ethernet.c
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endif
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endif
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ifeq ($(CONFIG_CAN),y)
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ifeq ($(CONFIG_LPC17_40_CAN),y)
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CHIP_CSRCS += lpc17_40_can.c
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endif
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@ -95,6 +95,10 @@
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# error "Both chrdev CAN or SocketCAN have been enabled"
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#endif
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#if !defined(CHRDEV_CAN) && !defined(SOCKET_CAN)
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# error "No upper CAN driver enabled"
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#endif
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#if defined(CHRDEV_CAN)
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#define lpc17_40_can_s can_dev_s
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#endif
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@ -68,7 +68,7 @@
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/* Debug ********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
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# define pwm_dumpgpio(p,m) lpc17_40_dumpgpio(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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@ -85,7 +85,7 @@
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/* Debug ********************************************************************/
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#ifdef CONFIG_DEBUG_PWM_INFO
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# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
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# define pwm_dumpgpio(p,m) lpc17_40_dumpgpio(p,m)
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#else
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# define pwm_dumpgpio(p,m)
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#endif
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@ -96,16 +96,22 @@
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/* This structure represents the state of one PWM timer */
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struct lpc17_40_pwmchan_s
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{
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uint8_t channel; /* Timer output channel */
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uint32_t pincfg; /* Output pin configuration */
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};
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struct lpc17_40_pwmtimer_s
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{
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const struct pwm_ops_s *ops; /* PWM operations */
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uint8_t timid; /* Timer ID {0,...,7} */
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uint8_t channel; /* Timer output channel: {1,..4} */
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uint8_t timtype; /* See the TIMTYPE_* definitions */
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uint32_t base; /* The base address of the timer */
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uint32_t pincfg; /* Output pin configuration */
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uint32_t pclk; /* The frequency of the peripheral clock
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* that drives the timer module. */
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const struct pwm_ops_s *ops; /* PWM operations */
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struct lpc17_40_pwmchan_s *channels; /* Channels configuration */
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uint8_t timid; /* Timer ID {0,...,7} */
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uint8_t chan_num; /* Number of configured channels */
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uint8_t timtype; /* See the TIMTYPE_* definitions */
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uint32_t base; /* The base address of the timer */
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uint32_t pclk; /* The frequency of the peripheral clock
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* that drives the timer module. */
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};
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/****************************************************************************
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@ -160,16 +166,60 @@ static const struct pwm_ops_s g_pwmops =
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};
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#ifdef CONFIG_LPC17_40_PWM1
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static struct lpc17_40_pwmchan_s g_pwm1channels[] =
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{
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/* PWM1 has 6 channels */
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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{
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.channel = 1,
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.pincfg = GPIO_PWM1p1,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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{
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.channel = 2,
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.pincfg = GPIO_PWM1p2,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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{
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.channel = 3,
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.pincfg = GPIO_PWM1p3,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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{
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.channel = 4,
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.pincfg = GPIO_PWM1p5,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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{
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.channel = 5,
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.pincfg = GPIO_PWM1p5,
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},
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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{
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.channel = 6,
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.pincfg = GPIO_PWM1p6,
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},
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#endif
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};
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static struct lpc17_40_pwmtimer_s g_pwm1dev =
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{
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.ops = &g_pwmops,
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.timid = 1,
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.channel = CONFIG_LPC17_40_PWM1_PIN,
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.chan_num = LPC17_40_PWM1_NCHANNELS,
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.channels = g_pwm1channels,
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.timtype = TIMTYPE_TIM1,
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.base = LPC17_40_PWM1_BASE,
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.pincfg = GPIO_PWM1p1_1,
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.pclk = (0x1 << 12),
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};
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#endif
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/****************************************************************************
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@ -236,27 +286,25 @@ static void pwm_dumpregs(struct lpc17_40_pwmtimer_s *priv,
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const char *msg)
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{
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pwminfo("%s:\n", msg);
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pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
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pwminfo(" IR: %04x TCR: %04x TC: %04x PR: %04x PC: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_IR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_TCR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_TC_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_PR_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_PC_OFFSET));
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pwminfo(" MCR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MCR_OFFSET));
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#ifdef CONFIG_PWM_MULTICHAN
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pwminfo(" 0: %08x 1: %08x 2: %08x 3: %08x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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#if defined(CONFIG_LPC17_40_PWM1)
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if (priv->timtype == TIMTYPE_ADVANCED)
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{
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pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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else
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pwminfo(" 4: %08x 5: %08x 6: %08x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR4_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR5_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR6_OFFSET));
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#endif
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{
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pwminfo(" DCR: %04x DMAR: %04x\n",
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pwm_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
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pwm_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
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}
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}
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#endif
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@ -279,19 +327,116 @@ static int pwm_timer(struct lpc17_40_pwmtimer_s *priv,
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const struct pwm_info_s *info)
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{
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irqstate_t flags;
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uint32_t i;
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int ret = OK;
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uint32_t lerval = LER0_EN;
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uint32_t pcrval = 0;
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uint32_t mr0_freq;
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flags = enter_critical_section();
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putreg32(info->frequency, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */
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putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */
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mr0_freq = 1.f / info->frequency * LPC17_40_PWM_CLOCK / 10;
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putreg32(mr0_freq, LPC17_40_PWM1_MR0); /* Set PWMMR0 = number of counts */
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#ifndef CONFIG_PWM_MULTICHAN
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putreg32(info->duty, LPC17_40_PWM1_MR1); /* Set PWM cycle */
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#else
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for (i = 0; i < CONFIG_PWM_NCHANNELS; i++)
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{
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switch (priv->channels[i].channel)
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{
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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case 1:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR1); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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case 2:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR2); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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case 3:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR3); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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case 4:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR4); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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case 5:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR5); /* Set PWM cycle */
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break;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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case 6:
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putreg32(ub16mulub16(info->channels[i].duty, mr0_freq),
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LPC17_40_PWM1_MR6); /* Set PWM cycle */
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break;
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#endif
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default:
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{
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pwmerr("ERROR: Channel %d does not exist\n",
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priv->channels[i].channel);
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ret = -EINVAL;
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}
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}
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}
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
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pcrval |= PWMENA1;
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lerval |= LER1_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
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pcrval |= PWMENA2;
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lerval |= LER2_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
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pcrval |= PWMENA3;
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lerval |= LER3_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
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pcrval |= PWMENA4;
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lerval |= LER4_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
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pcrval |= PWMENA5;
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lerval |= LER5_EN;
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#endif
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#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
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pcrval |= PWMENA6;
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lerval |= LER6_EN;
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#endif
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putreg32(lerval, LPC17_40_PWM1_LER); /* Load Shadow register contents */
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putreg32(pcrval, LPC17_40_PWM1_PCR); /* Enable PWM outputs */
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putreg32(LER0_EN | LER3_EN, LPC17_40_PWM1_LER); /* Load Shadow register contents */
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putreg32(PWMENA1, LPC17_40_PWM1_PCR); /* Enable PWM outputs */
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putreg32(TCR_CNT_EN | TCR_PWM_EN, LPC17_40_PWM1_TCR); /* Enable PWM Timer */
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leave_critical_section(flags);
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pwm_dumpregs(priv, "After starting");
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return OK;
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return ret;
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}
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#ifdef XXXXX
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@ -416,6 +561,7 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev)
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(struct lpc17_40_pwmtimer_s *)dev;
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irqstate_t flags;
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uint32_t regval;
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int i;
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flags = enter_critical_section();
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@ -428,14 +574,17 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev)
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/* Select clock for the pwm peripheral */
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regval = getreg32(LPC17_40_SYSCON_PCLKSEL0);
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regval &= ~(0x3 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */
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regval |= (0x1 << 12); /* PCLK_MC peripheral clk = CCLK = 12.5 MHz */
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regval &= ~SYSCON_PCLKSEL0_PWM1_MASK; /* PCLK_MC peripheral clk = CCLK = LPC17_40_CCLK */
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regval |= (SYSCON_PCLKSEL_CCLK << SYSCON_PCLKSEL0_PWM1_SHIFT); /* PCLK_MC peripheral clk = CCLK = LPC17_40_CCLK */
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putreg32(regval, LPC17_40_SYSCON_PCLKSEL0);
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priv->pclk = (0x1 << 12);
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/* Configure the output pin */
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lpc17_40_configgpio(GPIO_PWM1p1_1);
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for (i = 0; i < priv->chan_num; i++)
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{
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lpc17_40_configgpio(priv->channels[i].pincfg);
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}
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putreg32(1, LPC17_40_PWM1_PR); /* Prescaler count frequency: Fpclk/1 */
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putreg32(1 << 1, LPC17_40_PWM1_MCR); /* Reset on match register MR0 */
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@ -465,11 +614,25 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
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{
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struct lpc17_40_pwmtimer_s *priv =
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(struct lpc17_40_pwmtimer_s *)dev;
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uint32_t pincfg;
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uint32_t regval;
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uint32_t i;
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pwminfo("TIM%d pincfg: %08x\n", priv->timid, priv->pincfg);
|
||||
/* Configure the output pin to be output and low */
|
||||
|
||||
/* Make sure that the output has been stopped */
|
||||
for (i = 0; i < priv->chan_num; i++)
|
||||
{
|
||||
regval = priv->channels[i].pincfg;
|
||||
regval &= (GPIO_PORT_MASK | GPIO_PIN_MASK);
|
||||
regval |= (GPIO_OUTPUT | GPIO_VALUE_ZERO);
|
||||
|
||||
lpc17_40_configgpio(regval);
|
||||
}
|
||||
|
||||
/* Power off the pwm peripheral */
|
||||
|
||||
regval = getreg32(LPC17_40_SYSCON_PCONP);
|
||||
regval &= ~SYSCON_PCONP_PCPWM1;
|
||||
putreg32(regval, LPC17_40_SYSCON_PCONP);
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -522,7 +685,6 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
|
||||
(struct lpc17_40_pwmtimer_s *)dev;
|
||||
uint32_t resetbit;
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
irqstate_t flags;
|
||||
|
||||
pwminfo("TIM%d\n", priv->timid);
|
||||
@ -551,7 +713,7 @@ static int pwm_stop(struct pwm_lowerhalf_s *dev)
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
pwminfo("regaddr: %08x resetbit: %08x\n", regaddr, resetbit);
|
||||
pwminfo("regaddr: %08lx resetbit: %08lx\n", regaddr, resetbit);
|
||||
pwm_dumpregs(priv, "After stop");
|
||||
return OK;
|
||||
}
|
||||
@ -616,19 +778,25 @@ struct pwm_lowerhalf_s *lpc17_40_pwminitialize(int timer)
|
||||
switch (timer)
|
||||
{
|
||||
#ifdef CONFIG_LPC17_40_PWM1
|
||||
|
||||
case 0:
|
||||
lower = &g_pwm1dev;
|
||||
|
||||
/* Attach but disable the TIM1 update interrupt */
|
||||
|
||||
break;
|
||||
|
||||
#endif
|
||||
|
||||
default:
|
||||
pwmerr("ERROR: No such timer configured\n");
|
||||
pwmerr("ERROR: No such timer configured or pin defined\n");
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Ensure PWM has been shutdown */
|
||||
|
||||
pwm_shutdown((struct pwm_lowerhalf_s *)lower);
|
||||
|
||||
return (struct pwm_lowerhalf_s *)lower;
|
||||
}
|
||||
|
||||
|
||||
@ -33,6 +33,57 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* PLL0CLK = CCLK * CCLK divider */
|
||||
|
||||
#define LPC17_40_PWM_CLOCK (LPC17_40_CCLK * BOARD_CCLKCFG_DIVIDER)
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL1
|
||||
# define LPC17_40_PWM1_CHANNEL1 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL1 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL2
|
||||
#define LPC17_40_PWM1_CHANNEL2 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL2 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL3
|
||||
#define LPC17_40_PWM1_CHANNEL3 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL3 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL4
|
||||
#define LPC17_40_PWM1_CHANNEL4 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL4 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL5
|
||||
#define LPC17_40_PWM1_CHANNEL5 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL5 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC17_40_PWM1_CHANNEL6
|
||||
#define LPC17_40_PWM1_CHANNEL6 1
|
||||
#else
|
||||
#define LPC17_40_PWM1_CHANNEL6 0
|
||||
#endif
|
||||
|
||||
#define LPC17_40_PWM1_NCHANNELS (LPC17_40_PWM1_CHANNEL1 + \
|
||||
LPC17_40_PWM1_CHANNEL2 + \
|
||||
LPC17_40_PWM1_CHANNEL3 + \
|
||||
LPC17_40_PWM1_CHANNEL4 + \
|
||||
LPC17_40_PWM1_CHANNEL5 + \
|
||||
LPC17_40_PWM1_CHANNEL6)
|
||||
|
||||
#if CONFIG_PWM_NCHANNELS > LPC17_40_PWM1_NCHANNELS
|
||||
# error "PWM subystem has more channels then physical channels enabled"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
@ -68,7 +68,7 @@
|
||||
/* Debug ********************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_PWM_INFO
|
||||
# define pwm_dumpgpio(p,m) stm32_dumpgpio(p,m)
|
||||
# define pwm_dumpgpio(p,m) lpc17_40_dumpgpio(p,m)
|
||||
#else
|
||||
# define pwm_dumpgpio(p,m)
|
||||
#endif
|
||||
@ -220,25 +220,25 @@ static void timer_dumpregs(struct lpc17_40_timer_s *priv,
|
||||
{
|
||||
pwminfo("%s:\n", msg);
|
||||
pwminfo(" CR1: %04x CR2: %04x SMCR: %04x DIER: %04x\n",
|
||||
timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
|
||||
timer_getreg(priv, LPC17_40_TMR_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR3_OFFSET));
|
||||
#if defined(CONFIG_LPC17_40_TMR0)
|
||||
if (priv->timtype == TIMTYPE_ADVANCED)
|
||||
{
|
||||
pwminfo(" RCR: %04x BDTR: %04x DCR: %04x DMAR: %04x\n",
|
||||
timer_getreg(priv, LPC17_40_PWM_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
|
||||
timer_getreg(priv, LPC17_40_TMR_MR0_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR1_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR3_OFFSET));
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
pwminfo(" DCR: %04x DMAR: %04x\n",
|
||||
timer_getreg(priv, LPC17_40_PWM_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_PWM_MR3_OFFSET));
|
||||
timer_getreg(priv, LPC17_40_TMR_MR2_OFFSET),
|
||||
timer_getreg(priv, LPC17_40_TMR_MR3_OFFSET));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -3357,7 +3357,9 @@ void arm_usbinitialize(void)
|
||||
#ifndef CONFIG_LPC17_40_USBDEV_NOVBUS
|
||||
lpc17_40_configgpio(GPIO_USB_VBUS); /* VBUS status input */
|
||||
#endif
|
||||
#ifndef CONFIG_LPC17_40_USBDEV_NOSOFTCONNECT
|
||||
lpc17_40_configgpio(GPIO_USB_CONNECT); /* SoftConnect control signal */
|
||||
#endif
|
||||
#ifndef CONFIG_LPC17_40_USBDEV_NOLED
|
||||
lpc17_40_configgpio(GPIO_USB_UPLED); /* GoodLink LED control signal */
|
||||
#endif
|
||||
|
||||
@ -25,6 +25,7 @@ CONFIG_BOARDCTL_RESET=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=11934
|
||||
CONFIG_BOOT_RUNFROMSDRAM=y
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_CAN=y
|
||||
CONFIG_CANCELLATION_POINTS=y
|
||||
CONFIG_CANUTILS_CANLIB=y
|
||||
CONFIG_CAN_EXTID=y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user