mpfs/mpfs_spi.c: Fix some logic errors in the driver
- putreg32() is used the wrong way around (reg, val) instead of (val, reg) - MPFS_SPI_FRAMESIZE is not a register, FSIZE is the name - Clear all interrupts _before_ writing the FIFO, this prevents a race condition where a short transmission completes before the interrupt is enabled.
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@ -316,7 +316,7 @@ static void mpfs_spi_rxoverflow_recover(struct mpfs_spi_priv_s *priv)
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control_reg = getreg32(MPFS_SPI_CONTROL);
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clk_gen = getreg32(MPFS_SPI_CLK_GEN);
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frame_size = getreg32(MPFS_SPI_FRAMESIZE);
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frame_size = getreg32(MPFS_SPI_FSIZE);
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control2 = getreg32(MPFS_SPI_CONTROL2);
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packet_size = getreg32(MPFS_SPI_PKTSIZE);
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cmd_size = getreg32(MPFS_SPI_CMD_SIZE);
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@ -333,7 +333,7 @@ static void mpfs_spi_rxoverflow_recover(struct mpfs_spi_priv_s *priv)
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putreg32(control_reg, MPFS_SPI_CONTROL);
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putreg32(clk_gen, MPFS_SPI_CLK_GEN);
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putreg32(frame_size, MPFS_SPI_FRAMESIZE);
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putreg32(frame_size, MPFS_SPI_FSIZE);
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mpfs_spi_enable(priv, 1);
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@ -862,6 +862,13 @@ static void mpfs_spi_irq_exchange(struct mpfs_spi_priv_s *priv,
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putreg32(0, MPFS_SPI_FRAMESUP);
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/* Clear the interrupts before writing FIFO */
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putreg32(MPFS_SPI_TXCHUNDRUN |
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MPFS_SPI_RXCHOVRFLW |
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MPFS_SPI_RXRDONECLR |
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MPFS_SPI_TXDONECLR, MPFS_SPI_INT_CLEAR);
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if (nwords > priv->fifosize)
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{
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modifyreg32(MPFS_SPI_CONTROL, MPFS_SPI_FRAMECNT,
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@ -877,11 +884,6 @@ static void mpfs_spi_irq_exchange(struct mpfs_spi_priv_s *priv,
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/* Enable TX, RX, underrun and overflow interrupts */
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putreg32(MPFS_SPI_INT_CLEAR, MPFS_SPI_TXCHUNDRUN |
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MPFS_SPI_RXCHOVRFLW |
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MPFS_SPI_RXRDONECLR |
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MPFS_SPI_TXDONECLR);
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modifyreg32(MPFS_SPI_CONTROL, 0, MPFS_SPI_INTTXTURUN |
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MPFS_SPI_INTRXOVRFLOW |
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MPFS_SPI_INTRXDATA |
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@ -899,10 +901,10 @@ static void mpfs_spi_irq_exchange(struct mpfs_spi_priv_s *priv,
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MPFS_SPI_INTTXDATA,
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0);
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putreg32(MPFS_SPI_INT_CLEAR, MPFS_SPI_TXCHUNDRUN |
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MPFS_SPI_RXCHOVRFLW |
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MPFS_SPI_RXRDONECLR |
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MPFS_SPI_TXDONECLR);
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putreg32(MPFS_SPI_TXCHUNDRUN |
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MPFS_SPI_RXCHOVRFLW |
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MPFS_SPI_RXRDONECLR |
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MPFS_SPI_TXDONECLR, MPFS_SPI_INT_CLEAR);
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}
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/****************************************************************************
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