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Several fixes related to Cortex-M RAM vectors

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This commit is contained in:
Gregory Nutt 2013-12-22 18:19:08 -06:00
parent 88faa55ac1
commit 22e208dbf9
4 changed files with 19 additions and 12 deletions
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7
arch/arm/src/armv7-m/nvic.h
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@ -442,7 +442,6 @@
#define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT) #define NVIC_INTCTRL_VECTACTIVE_MASK (0x1ff << NVIC_INTCTRL_VECTACTIVE_SHIFT)
/* System control register (SYSCON) */ /* System control register (SYSCON) */
/* Bit 0: Reserved */ /* Bit 0: Reserved */
#define NVIC_SYSCON_SLEEPONEXIT (1 << 1) /* Bit 1: Sleep-on-exit (returning from Handler to Thread mode) */ #define NVIC_SYSCON_SLEEPONEXIT (1 << 1) /* Bit 1: Sleep-on-exit (returning from Handler to Thread mode) */
#define NVIC_SYSCON_SLEEPDEEP (1 << 2) /* Bit 2: Use deep sleep in low power mode */ #define NVIC_SYSCON_SLEEPDEEP (1 << 2) /* Bit 2: Use deep sleep in low power mode */
@ -484,11 +483,11 @@
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT) #define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* Vector Table Offset Register (VECTAB). This mask seems to vary among /* Vector Table Offset Register (VECTAB). This mask seems to vary among
* ARMv7-M implementations. It may be be redefined in the architecture- * ARMv7-M implementations. It may need to be redefined in some
* specific chip.h header file. * architecture-specific header file.
*/ */
#define NVIC_VECTAB_TBLOFF_MASK (0xffffffc0) #define NVIC_VECTAB_TBLOFF_MASK (0xffffff80)
/* Application Interrupt and Reset Control Register (AIRCR) */ /* Application Interrupt and Reset Control Register (AIRCR) */

6
arch/arm/src/armv7-m/ram_vectors.h
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@ -64,8 +64,8 @@
#endif #endif
/* This, then is the size of the vector table (in 4-byte entries). This size /* This, then is the size of the vector table (in 4-byte entries). This size
* includes the IDLE stack pointer which lies at the beginning of * includes the (1) the device interrupts, (2) space for 15 Cortex-M excpetions, and
* the table. * (3) IDLE stack pointer which lies at the beginning of the table.
*/ */
#define ARMV7M_VECTAB_SIZE (ARMV7M_PERIPHERAL_INTERRUPTS + 16) #define ARMV7M_VECTAB_SIZE (ARMV7M_PERIPHERAL_INTERRUPTS + 16)
@ -84,7 +84,7 @@
*/ */
extern up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE] extern up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (64))); __attribute__ ((section (".ram_vectors"), aligned (128)));
/************************************************************************************ /************************************************************************************
* Public Function Prototypes * Public Function Prototypes

9
arch/arm/src/armv7-m/up_ramvec_attach.c
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@ -39,6 +39,7 @@
#include <nuttx/config.h> #include <nuttx/config.h>
#include <errno.h>
#include <debug.h> #include <debug.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
@ -94,17 +95,17 @@ void exception_common(void);
* *
* Description: * Description:
* Configure the ram vector table so that IRQ number 'irq' will be * Configure the ram vector table so that IRQ number 'irq' will be
* dipatched by hardware to 'vector' * dispatched by hardware to 'vector'
* *
****************************************************************************/ ****************************************************************************/
int up_ramvec_attach(int irq, up_vector_t vector) int up_ramvec_attach(int irq, up_vector_t vector)
{ {
int ret = ERROR; int ret = -EINVAL;
intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq); intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < ARMV7M_PERIPHERAL_INTERRUPTS) if ((unsigned)irq < (STM32_IRQ_INTERRUPTS + ARMV7M_PERIPHERAL_INTERRUPTS))
{ {
irqstate_t flags; irqstate_t flags;
@ -129,7 +130,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
vector = exception_common; vector = exception_common;
} }
/* Save the new vector in the vector table. */ /* Save the new vector in the vector table */
g_ram_vectors[irq] = vector; g_ram_vectors[irq] = vector;
irqrestore(flags); irqrestore(flags);

9
arch/arm/src/armv7-m/up_ramvec_initialize.c
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@ -88,7 +88,7 @@
*/ */
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE] up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (64))); __attribute__ ((section (".ram_vectors"), aligned (128)));
/**************************************************************************** /****************************************************************************
* Private Variables * Private Variables
@ -139,7 +139,14 @@ void up_ramvec_initialize(void)
/* Now configure the NVIC to use the new vector table. */ /* Now configure the NVIC to use the new vector table. */
putreg32((uint32_t)g_ram_vectors, NVIC_VECTAB); putreg32((uint32_t)g_ram_vectors, NVIC_VECTAB);
/* The number bits required to align the RAM vector table seem to vary
* from part-to-part. The following assertion will catch the case where
* the table alignment is insufficient.
*/
intvdbg("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB)); intvdbg("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
DEBUGASSERT(getreg32(NVIC_VECTAB) == (uint32_t)g_ram_vectors);
} }
#endif /* !CONFIG_ARCH_RAMVECTORS */ #endif /* !CONFIG_ARCH_RAMVECTORS */