diff --git a/arch/arm/src/stm32h7/Kconfig b/arch/arm/src/stm32h7/Kconfig
index 8be129fdc7..74acefccdf 100644
--- a/arch/arm/src/stm32h7/Kconfig
+++ b/arch/arm/src/stm32h7/Kconfig
@@ -149,6 +149,7 @@ config ARCH_CHIP_STM32H747XI
 	select STM32H7_IO_CONFIG_X
 	select STM32H7_HAVE_FDCAN1
 	select STM32H7_HAVE_FDCAN2
+	select STM32H7_HAVE_SMPS
 	---help---
 		Dual core STM32 H7 Cortex M7+M4, 2048 Kb FLASH, 1024K Kb SRAM
 		TFBGA240
diff --git a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
index 81e7e8a627..f1bb765a2b 100644
--- a/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
+++ b/arch/arm/src/stm32h7/stm32h7x7xx_rcc.c
@@ -826,9 +826,17 @@ void stm32_stdclockconfig(void)
        * N.B. The system shall be power cycled before writing a new value.
        */
 
+#if defined(CONFIG_STM32H7_PWR_DIRECT_SMPS_SUPPLY)
+      regval = getreg32(STM32_PWR_CR3);
+      regval &= ~(STM32_PWR_CR3_BYPASS | STM32_PWR_CR3_LDOEN |
+          STM32_PWR_CR3_SMPSEXTHP | STM32_PWR_CR3_SMPSLEVEL_MASK);
+      regval |= STM32_PWR_CR3_LDOESCUEN;
+      putreg32(regval, STM32_PWR_CR3);
+#else
       regval = getreg32(STM32_PWR_CR3);
       regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_LDOESCUEN;
       putreg32(regval, STM32_PWR_CR3);
+#endif
 
       /* Set the voltage output scale */