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CAN ISO-11783 support contributed by Gary Teravskis

Browse Source 
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4400 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-02-18 14:02:34 +00:00
parent 86c799f547
commit 22ffe347bc
6 changed files with 101 additions and 92 deletions
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12
arch/arm/src/stm32/chip/stm32f103ze_pinmap.h
View File

@ -356,14 +356,14 @@
/* CAN */
#if defined(CONFIG_STM32_CAN1_REMAP1)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
#elif defined(CONFIG_STM32_CAN1_REMAP2)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN1)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN1)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN0)
#else
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN11)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN12)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN12)
# define GPIO_CAN1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN11)
#endif
/* FSMC: CF */

6
arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
View File

@ -210,7 +210,8 @@
#define RCC_APB1RSTR_I2C1RST (1 << 21) /* Bit 21: I2C 1 reset */
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
#define RCC_APB1RSTR_CANRST (1 << 25) /* Bit 25: CAN reset */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
#define RCC_APB1RSTR_BKPRST (1 << 27) /* Bit 27: Backup interface reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
@ -262,7 +263,8 @@
#define RCC_APB1ENR_I2C1EN (1 << 21) /* Bit 21: I2C 1 clock enable */
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
#define RCC_APB1ENR_CANEN (1 << 25) /* Bit 25: CAN clock enable */
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN1 clock enable */
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 25: CAN2 clock enable */
#define RCC_APB1ENR_BKPEN (1 << 27) /* Bit 27: Backup interface clock enable */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */

3
arch/arm/src/stm32/stm32_can.c
View File

@ -1282,7 +1282,8 @@ static int can_bittiming(struct stm32_can_s *priv)
uint32_t ts1;
uint32_t ts2;
canllvdbg("CAN%d PCLK1: %d baud: %d\n", priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
canllvdbg("CAN%d PCLK1: %d baud: %d\n",
priv->port, STM32_PCLK1_FREQUENCY, priv->baud);
/* Try to get CAN_BIT_QUANTA quanta in one bit_time.
*

4
arch/arm/src/stm32/stm32_rcc.c
View File

@ -1,8 +1,8 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_rcc.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions

78
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@ -1,8 +1,8 @@
/****************************************************************************
* arch/arm/src/stm32/stm32f10xxx_rcc.c
*
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -114,31 +114,31 @@ static inline void rcc_enableahb(void)
regval = RCC_AHBENR_FLITFEN|RCC_AHBENR_SRAMEN;
#if CONFIG_STM32_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHBENR_DMA1EN;
#endif
#if CONFIG_STM32_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHBENR_DMA2EN;
#endif
#if CONFIG_STM32_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHBENR_CRCEN;
#endif
#if CONFIG_STM32_FSMC
#ifdef CONFIG_STM32_FSMC
/* FSMC clock enable */
regval |= RCC_AHBENR_FSMCEN;
#endif
#if CONFIG_STM32_SDIO
#ifdef CONFIG_STM32_SDIO
/* SDIO clock enable */
regval |= RCC_AHBENR_SDIOEN;
@ -159,7 +159,7 @@ static inline void rcc_enableapb1(void)
{
uint32_t regval;
#if CONFIG_STM32_USB
#ifdef CONFIG_STM32_USB
/* USB clock divider. This bit must be valid before enabling the USB
* clock in the RCC_APB1ENR register. This bit can’t be reset if the USB
* clock is enabled.
@ -176,123 +176,129 @@ static inline void rcc_enableapb1(void)
*/
regval = getreg32(STM32_RCC_APB1ENR);
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
/* Timer 2 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM2EN;
#endif
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
/* Timer 3 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM3EN;
#endif
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
/* Timer 4 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM4EN;
#endif
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
/* Timer 5 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM5EN;
#endif
#endif
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
/* Timer 6 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM6EN;
#endif
#endif
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
/* Timer 7 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_TIM7EN;
#endif
#endif
#if CONFIG_STM32_WWDG
#ifdef CONFIG_STM32_WWDG
/* Window Watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN;
#endif
#if CONFIG_STM32_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI 2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#if CONFIG_STM32_SPI3
#ifdef CONFIG_STM32_SPI3
/* SPI 3 clock enable */
regval |= RCC_APB1ENR_SPI3EN;
#endif
#if CONFIG_STM32_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#if CONFIG_STM32_USART3
#ifdef CONFIG_STM32_USART3
/* USART 3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#if CONFIG_STM32_UART4
#ifdef CONFIG_STM32_UART4
/* UART 4 clock enable */
regval |= RCC_APB1ENR_UART4EN;
#endif
#if CONFIG_STM32_UART5
#ifdef CONFIG_STM32_UART5
/* UART 5 clock enable */
regval |= RCC_APB1ENR_UART5EN;
#endif
#if CONFIG_STM32_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C 1 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_I2C1EN;
#endif
#endif
#if CONFIG_STM32_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C 2 clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB1ENR_I2C2EN;
#endif
#endif
#if CONFIG_STM32_USB
#ifdef CONFIG_STM32_USB
/* USB clock enable */
regval |= RCC_APB1ENR_USBEN;
#endif
#if CONFIG_STM32_CAN
/* CAN clock enable */
#if defined(CONFIG_STM32_CAN) || defined (CONFIG_STM32_CAN1)
/* CAN1 clock enable */
regval |= RCC_APB1ENR_CANEN;
regval |= RCC_APB1ENR_CAN1EN;
#endif
#if CONFIG_STM32_BKP
#ifdef CONFIG_STM32_CAN2
/* CAN2 clock enable */
regval |= RCC_APB1ENR_CAN2EN;
#endif
#ifdef CONFIG_STM32_BKP
/* Backup interface clock enable */
regval |= RCC_APB1ENR_BKPEN;
#endif
#if CONFIG_STM32_PWR
#ifdef CONFIG_STM32_PWR
/* Power interface clock enable */
regval |= RCC_APB1ENR_PWREN;
@ -349,45 +355,45 @@ static inline void rcc_enableapb2(void)
#endif
);
#if CONFIG_STM32_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC 1 interface clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#if CONFIG_STM32_ADC2
#ifdef CONFIG_STM32_ADC2
/* ADC 2 interface clock enable */
regval |= RCC_APB2ENR_ADC2EN;
#endif
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM1EN;
#endif
#endif
#if CONFIG_STM32_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI 1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
/* TIM8 Timer clock enable */
#ifdef CONFIG_STM32_FORCEPOWER
regval |= RCC_APB2ENR_TIM8EN;
#endif
#endif
#if CONFIG_STM32_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#if CONFIG_STM32_ADC3
#ifdef CONFIG_STM32_ADC3
/*ADC3 interface clock enable */
regval |= RCC_APB2ENR_ADC3EN;

90
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@ -151,31 +151,31 @@ static inline void rcc_enableahb1(void)
);
#endif
#if CONFIG_STM32_CRC
#ifdef CONFIG_STM32_CRC
/* CRC clock enable */
regval |= RCC_AHB1ENR_CRCEN;
#endif
#if CONFIG_STM32_BKPSRAM
#ifdef CONFIG_STM32_BKPSRAM
/* Backup SRAM clock enable */
regval |= RCC_AHB1ENR_BKPSRAMEN;
#endif
#if CONFIG_STM32_CCMDATARAM
#ifdef CONFIG_STM32_CCMDATARAM
/* CCM data RAM clock enable */
regval |= RCC_AHB1ENR_CCMDATARAMEN;
#endif
#if CONFIG_STM32_DMA1
#ifdef CONFIG_STM32_DMA1
/* DMA 1 clock enable */
regval |= RCC_AHB1ENR_DMA1EN;
#endif
#if CONFIG_STM32_DMA2
#ifdef CONFIG_STM32_DMA2
/* DMA 2 clock enable */
regval |= RCC_AHB1ENR_DMA2EN;
@ -221,31 +221,31 @@ static inline void rcc_enableahb2(void)
regval = getreg32(STM32_RCC_AHB2ENR);
#if CONFIG_STM32_DCMI
#ifdef CONFIG_STM32_DCMI
/* Camera interface enable */
regval |= RCC_AHB2ENR_DCMIEN;
#endif
#if CONFIG_STM32_CRYP
#ifdef CONFIG_STM32_CRYP
/* Cryptographic modules clock enable */
regval |= RCC_AHB2ENR_CRYPEN;
#endif
#if CONFIG_STM32_HASH
#ifdef CONFIG_STM32_HASH
/* Hash modules clock enable */
regval |= RCC_AHB2ENR_HASHEN;
#endif
#if CONFIG_STM32_RNG
#ifdef CONFIG_STM32_RNG
/* Random number generator clock enable */
regval |= RCC_AHB2ENR_RNGEN;
#endif
#if CONFIG_STM32_OTGFS
#ifdef CONFIG_STM32_OTGFS
/* USB OTG FS clock enable */
regval |= RCC_AHB2ENR_OTGFSEN;
@ -264,7 +264,7 @@ static inline void rcc_enableahb2(void)
static inline void rcc_enableahb3(void)
{
#if CONFIG_STM32_FSMC
#ifdef CONFIG_STM32_FSMC
uint32_t regval;
/* Set the appropriate bits in the AHB3ENR register to enabled the
@ -299,127 +299,127 @@ static inline void rcc_enableapb1(void)
regval = getreg32(STM32_RCC_APB1ENR);
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
/* TIM2 clock enable */
regval |= RCC_APB1ENR_TIM2EN;
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
/* TIM3 clock enable */
regval |= RCC_APB1ENR_TIM3EN;
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
/* TIM4 clock enable */
regval |= RCC_APB1ENR_TIM4EN;
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
/* TIM5 clock enable */
regval |= RCC_APB1ENR_TIM5EN;
#endif
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
/* TIM6 clock enable */
regval |= RCC_APB1ENR_TIM6EN;
#endif
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
/* TIM7 clock enable */
regval |= RCC_APB1ENR_TIM7EN;
#endif
#if CONFIG_STM32_TIM12
#ifdef CONFIG_STM32_TIM12
/* TIM12 clock enable */
regval |= RCC_APB1ENR_TIM12EN;
#endif
#if CONFIG_STM32_TIM13
#ifdef CONFIG_STM32_TIM13
/* TIM13 clock enable */
regval |= RCC_APB1ENR_TIM13EN;
#endif
#if CONFIG_STM32_TIM14
#ifdef CONFIG_STM32_TIM14
/* TIM14 clock enable */
regval |= RCC_APB1ENR_TIM14EN;
#endif
#if CONFIG_STM32_WWDG
#ifdef CONFIG_STM32_WWDG
/* Window watchdog clock enable */
regval |= RCC_APB1ENR_WWDGEN;
#endif
#if CONFIG_STM32_SPI2
#ifdef CONFIG_STM32_SPI2
/* SPI2 clock enable */
regval |= RCC_APB1ENR_SPI2EN;
#endif
#if CONFIG_STM32_SPI3
#ifdef CONFIG_STM32_SPI3
/* SPI3 clock enable */
regval |= RCC_APB1ENR_SPI3EN;
#endif
#if CONFIG_STM32_USART2
#ifdef CONFIG_STM32_USART2
/* USART 2 clock enable */
regval |= RCC_APB1ENR_USART2EN;
#endif
#if CONFIG_STM32_USART3
#ifdef CONFIG_STM32_USART3
/* USART3 clock enable */
regval |= RCC_APB1ENR_USART3EN;
#endif
#if CONFIG_STM32_UART4
#ifdef CONFIG_STM32_UART4
/* UART4 clock enable */
regval |= RCC_APB1ENR_UART4EN;
#endif
#if CONFIG_STM32_UART5
#ifdef CONFIG_STM32_UART5
/* UART5 clock enable */
regval |= RCC_APB1ENR_UART5EN;
#endif
#if CONFIG_STM32_I2C1
#ifdef CONFIG_STM32_I2C1
/* I2C1 clock enable */
regval |= RCC_APB1ENR_I2C1EN;
#endif
#if CONFIG_STM32_I2C2
#ifdef CONFIG_STM32_I2C2
/* I2C2 clock enable */
regval |= RCC_APB1ENR_I2C2EN;
#endif
#if CONFIG_STM32_I2C3
#ifdef CONFIG_STM32_I2C3
/* I2C3 clock enable */
regval |= RCC_APB1ENR_I2C3EN;
#endif
#if CONFIG_STM32_CAN1
#ifdef CONFIG_STM32_CAN1
/* CAN 1 clock enable */
regval |= RCC_APB1ENR_CAN1EN;
#endif
#if CONFIG_STM32_CAN2
#ifdef CONFIG_STM32_CAN2
/* CAN 2 clock enable */
regval |= RCC_APB1ENR_CAN2EN;
@ -458,79 +458,79 @@ static inline void rcc_enableapb2(void)
regval = getreg32(STM32_RCC_APB2ENR);
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
/* TIM1 clock enable */
regval |= RCC_APB2ENR_TIM1EN;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
/* TIM8 clock enable */
regval |= RCC_APB2ENR_TIM8EN;
#endif
#if CONFIG_STM32_USART1
#ifdef CONFIG_STM32_USART1
/* USART1 clock enable */
regval |= RCC_APB2ENR_USART1EN;
#endif
#if CONFIG_STM32_USART6
#ifdef CONFIG_STM32_USART6
/* USART6 clock enable */
regval |= RCC_APB2ENR_USART6EN;
#endif
#if CONFIG_STM32_ADC1
#ifdef CONFIG_STM32_ADC1
/* ADC1 clock enable */
regval |= RCC_APB2ENR_ADC1EN;
#endif
#if CONFIG_STM32_ADC2
#ifdef CONFIG_STM32_ADC2
/* ADC2 clock enable */
regval |= RCC_APB2ENR_ADC2EN;
#endif
#if CONFIG_STM32_ADC3
#ifdef CONFIG_STM32_ADC3
/* ADC3 clock enable */
regval |= RCC_APB2ENR_ADC3EN;
#endif
#if CONFIG_STM32_SDIO
#ifdef CONFIG_STM32_SDIO
/* SDIO clock enable */
regval |= RCC_APB2ENR_SDIOEN;
#endif
#if CONFIG_STM32_SPI1
#ifdef CONFIG_STM32_SPI1
/* SPI1 clock enable */
regval |= RCC_APB2ENR_SPI1EN;
#endif
#if CONFIG_STM32_SYSCFG
#ifdef CONFIG_STM32_SYSCFG
/* System configuration controller clock enable */
regval |= RCC_APB2ENR_SYSCFGEN;
#endif
#if CONFIG_STM32_TIM9
#ifdef CONFIG_STM32_TIM9
/* TIM9 clock enable */
regval |= RCC_APB2ENR_TIM9EN;
#endif
#if CONFIG_STM32_TIM10
#ifdef CONFIG_STM32_TIM10
/* TIM10 clock enable */
regval |= RCC_APB2ENR_TIM10EN;
#endif
#if CONFIG_STM32_TIM11
#ifdef CONFIG_STM32_TIM11
/* TIM11 clock enable */
regval |= RCC_APB2ENR_TIM11EN;