From 232aa62f03645ea701eb46018548c2aa7ddf66b8 Mon Sep 17 00:00:00 2001 From: "Alan C. Assis" Date: Wed, 7 Oct 2020 12:42:48 -0300 Subject: [PATCH] Add support to PSRAM using SPIRAM interface --- arch/xtensa/Kconfig | 2 + arch/xtensa/src/esp32/Kconfig | 92 + arch/xtensa/src/esp32/Make.defs | 5 + arch/xtensa/src/esp32/esp32_allocateheap.c | 10 + arch/xtensa/src/esp32/esp32_psram.c | 1758 ++++++++++++++++++ arch/xtensa/src/esp32/esp32_psram.h | 91 + arch/xtensa/src/esp32/esp32_spiram.c | 385 ++++ arch/xtensa/src/esp32/esp32_spiram.h | 157 ++ arch/xtensa/src/esp32/esp32_start.c | 13 + arch/xtensa/src/esp32/hardware/efuse_reg.h | 1821 +++++++++++++++++++ arch/xtensa/src/esp32/hardware/esp32_caps.h | 64 + arch/xtensa/src/esp32/hardware/esp32_soc.h | 24 + arch/xtensa/src/esp32/rom/esp32_efuse.h | 96 + 13 files changed, 4518 insertions(+) create mode 100644 arch/xtensa/src/esp32/esp32_psram.c create mode 100644 arch/xtensa/src/esp32/esp32_psram.h create mode 100644 arch/xtensa/src/esp32/esp32_spiram.c create mode 100644 arch/xtensa/src/esp32/esp32_spiram.h create mode 100644 arch/xtensa/src/esp32/hardware/efuse_reg.h create mode 100644 arch/xtensa/src/esp32/hardware/esp32_caps.h create mode 100644 arch/xtensa/src/esp32/rom/esp32_efuse.h diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 3b9d2efcda..da6512f745 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -15,6 +15,8 @@ config ARCH_CHIP_ESP32 select XTENSA_HAVE_INTERRUPTS select ARCH_HAVE_MULTICPU select ARCH_HAVE_MODULE_TEXT + select ARCH_HAVE_SDRAM + select ARCH_HAVE_HEAP2 select ARCH_HAVE_RESET select ARCH_TOOLCHAIN_GNU ---help--- diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index 169fd9aab8..a441b5e709 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -131,6 +131,26 @@ config ESP32_SPI3 select ESP32_GPIO_IRQ select SPI +config ESP32_SPIRAM + bool "SPI RAM Support" + default n + +if ESP32_SPIRAM && SMP + +choice + prompt "How does SPIRAM share cache?" + default ESP32_MEMMAP_SPIRAM_CACHE_EVENODD + help + Selects the cache mode to CPU access the external memory. + + config ESP32_MEMMAP_SPIRAM_CACHE_EVENODD + bool "Pro CPU uses even 32 byte ranges, App uses odd ones" + config ESP32_MEMMAP_SPIRAM_CACHE_LOWHIGH + bool "Pro CPU uses low 2MB ranges, App uses high ones" +endchoice # CPU frequency + +endif + config XTENSA_TIMER1 bool "Xtensa Timer 1" default n @@ -497,6 +517,78 @@ config ESP32_SPIFLASH_DEBUG endmenu # ESP32_SPIFLASH +menu "SPI RAM Config" + depends on ESP32_SPIRAM + +choice ESP32_SPIRAM_TYPE + prompt "Type of SPI RAM chip in use" + default ESP32_SPIRAM_TYPE_AUTO + +config ESP32_SPIRAM_TYPE_AUTO + bool "Auto-detect" + +config ESP32_SPIRAM_TYPE_ESPPSRAM32 + bool "ESP-PSRAM32 or IS25WP032" + +config ESP32_SPIRAM_TYPE_ESPPSRAM64 + bool "ESP-PSRAM64 or LY68L6400" +endchoice #ESP32_SPIRAM_TYPE + +config ESP32_SPIRAM_SIZE + int + default -1 if ESP32_SPIRAM_TYPE_AUTO + default 4194304 if ESP32_SPIRAM_TYPE_ESPPSRAM32 + default 8388608 if ESP32_SPIRAM_TYPE_ESPPSRAM64 + default 0 + +choice ESP32_SPIRAM_SPEED + prompt "Set RAM clock speed" + default ESP32_SPIRAM_SPEED_40M + help + Select the speed for the SPI RAM chip. + +config ESP32_SPIRAM_SPEED_40M + bool "40MHz clock speed" + +config ESP32_SPIRAM_SPEED_80M + bool "80MHz clock speed" + +endchoice # ESP32_SPIRAM_SPEED + +config ESP32_SPIRAM_BOOT_INIT + bool "Initialize SPI RAM during startup" + default "y" + help + If this is enabled, the SPI RAM will be enabled during initial + boot. Unless you have specific requirements, you'll want to leave + this enabled so memory allocated during boot-up can also be + placed in SPI RAM. + +config ESP32_SPIRAM_IGNORE_NOTFOUND + bool "Ignore PSRAM when not found" + default "n" + depends on ESP_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA + help + Normally, if psram initialization is enabled during compile time + but not found at runtime, it is seen as an error making the CPU + panic. If this is enabled, booting will complete but no PSRAM + will be available. + +config ESP32_SPIRAM_2T_MODE + bool "Enable SPI PSRAM 2T mode" + depends on ESP32_SPIRAM + default "n" + help + Enable this option to fix single bit errors inside 64Mbit PSRAM. + Some 64Mbit PSRAM chips have a hardware issue in the RAM which + causes bit errors at multiple fixed bit positions. + Note: If this option is enabled, the 64Mbit PSRAM chip will appear + to be 32Mbit in size. + Applications will not be affected unless the use the esp_himem + APIs, which are not supported in 2T mode. + +endmenu #SPI RAM Config + menu "Ethernet configuration" depends on ESP32_EMAC diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index e01a0615c7..abc9f7fc3a 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -114,6 +114,11 @@ ifeq ($(CONFIG_ESP32_SPIFLASH),y) CHIP_CSRCS += esp32_spiflash.c endif +ifeq ($(CONFIG_ESP32_SPIRAM),y) +CHIP_CSRCS += esp32_spiram.c +CHIP_CSRCS += esp32_psram.c +endif + ifeq ($(CONFIG_ESP32_EMAC),y) CHIP_CSRCS += esp32_emac.c endif diff --git a/arch/xtensa/src/esp32/esp32_allocateheap.c b/arch/xtensa/src/esp32/esp32_allocateheap.c index c0b3b82218..c3b048ab70 100644 --- a/arch/xtensa/src/esp32/esp32_allocateheap.c +++ b/arch/xtensa/src/esp32/esp32_allocateheap.c @@ -43,11 +43,16 @@ #include #include +#include #include #include #include "xtensa.h" +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + /**************************************************************************** * Public Functions ****************************************************************************/ @@ -88,5 +93,10 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size) #if CONFIG_MM_REGIONS > 1 void xtensa_add_region(void) { + /* Check for any additional memory regions */ + +#if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_SIZE) + umm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE); +#endif } #endif diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c new file mode 100644 index 0000000000..9c28c9d417 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -0,0 +1,1758 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_psram.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" +#include "xtensa_attr.h" +#include "esp32_rtc.h" +#include "esp32_gpio.h" +#include "esp32_psram.h" +#include "hardware/esp32_spi.h" +#include "hardware/esp32_caps.h" +#include "hardware/esp32_dport.h" +#include "hardware/esp32_iomux.h" +#include "hardware/esp32_rtccntl.h" +#include "hardware/esp32_gpio_sigmap.h" + +#include "rom/esp32_gpio.h" +#include "rom/esp32_gpio.h" +#include "rom/esp32_efuse.h" +#include "rom/esp32_spiflash.h" +#include "hardware/efuse_reg.h" + +#ifdef CONFIG_ESP32_SPIRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */ +#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */ + +/* Commands for PSRAM chip */ + +#define PSRAM_READ 0x03 +#define PSRAM_FAST_READ 0x0b +#define PSRAM_FAST_READ_DUMMY 0x03 +#define PSRAM_FAST_READ_QUAD 0xeb +#define PSRAM_FAST_READ_QUAD_DUMMY 0x05 +#define PSRAM_WRITE 0x02 +#define PSRAM_QUAD_WRITE 0x38 +#define PSRAM_ENTER_QMODE 0x35 +#define PSRAM_EXIT_QMODE 0xf5 +#define PSRAM_RESET_EN 0x66 +#define PSRAM_RESET 0x99 +#define PSRAM_SET_BURST_LEN 0xc0 +#define PSRAM_DEVICE_ID 0x9f + +#define PSRAM_ID_KGD_M 0xff +#define PSRAM_ID_KGD_S 8 +#define PSRAM_ID_KGD 0x5d +#define PSRAM_ID_EID_M 0xff +#define PSRAM_ID_EID_S 16 + +/* Use the [7:5](bit7~bit5) of EID to distinguish the psram size: + * + * BIT7 | BIT6 | BIT5 | SIZE(MBIT) + * ------------------------------------- + * 0 | 0 | 0 | 16 + * 0 | 0 | 1 | 32 + * 0 | 1 | 0 | 64 + */ + +#define PSRAM_EID_SIZE_M 0x07 +#define PSRAM_EID_SIZE_S 5 + +#define PSRAM_KGD(id) (((id) >> PSRAM_ID_KGD_S) & PSRAM_ID_KGD_M) +#define PSRAM_EID(id) (((id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) +#define PSRAM_SIZE_ID(id) ((PSRAM_EID(id) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M) +#define PSRAM_IS_VALID(id) (PSRAM_KGD(id) == PSRAM_ID_KGD) + +/* For the old version 32Mbit psram, using the special driver */ + +#define PSRAM_IS_32MBIT_VER0(id) (PSRAM_EID(id) == 0x20) +#define PSRAM_IS_64MBIT_TRIAL(id) (PSRAM_EID(id) == 0x26) + +/* IO-pins for PSRAM. + * WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these + * defines hardcode the flash pins as well, making this code incompatible + * with either a setup that has the flash on non-standard pins or ESP32s with + * built-in flash. + */ + +#define PSRAM_SPIQ_SD0_IO 7 +#define PSRAM_SPID_SD1_IO 8 +#define PSRAM_SPIWP_SD3_IO 10 +#define PSRAM_SPIHD_SD2_IO 9 + +#define FLASH_HSPI_CLK_IO 14 +#define FLASH_HSPI_CS_IO 15 +#define PSRAM_HSPI_SPIQ_SD0_IO 12 +#define PSRAM_HSPI_SPID_SD1_IO 13 +#define PSRAM_HSPI_SPIWP_SD3_IO 2 +#define PSRAM_HSPI_SPIHD_SD2_IO 4 + +/* PSRAM clock and cs IO should be configured based on hardware design. + * For ESP32-WROVER or ESP32-WROVER-B module, the clock IO is IO17, the CS IO + * is IO16, they are the default value for these two configs. + */ + +#define D0WD_PSRAM_CLK_IO CONFIG_D0WD_PSRAM_CLK_IO /* Default is 17 */ +#define D0WD_PSRAM_CS_IO CONFIG_D0WD_PSRAM_CS_IO /* Default is 16 */ + +#define D2WD_PSRAM_CLK_IO CONFIG_D2WD_PSRAM_CLK_IO /* Default is 9 */ +#define D2WD_PSRAM_CS_IO CONFIG_D2WD_PSRAM_CS_IO /* Default is 10 */ + +/* For ESP32-PICO chip, the psram share clock with flash. The flash clock + * pin is fixed, which is IO6. + */ + +#define PICO_PSRAM_CLK_IO 6 +#define PICO_PSRAM_CS_IO CONFIG_PICO_PSRAM_CS_IO /* Default is 10 */ + +#define PSRAM_INTERNAL_IO_28 28 +#define PSRAM_INTERNAL_IO_29 29 +#define PSRAM_IO_MATRIX_DUMMY_40M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M +#define PSRAM_IO_MATRIX_DUMMY_80M ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M + +#define _SPI_CACHE_PORT 0 +#define _SPI_FLASH_PORT 1 +#define _SPI_80M_CLK_DIV 1 +#define _SPI_40M_CLK_DIV 2 + +/* For 4MB PSRAM, we need one more SPI host, select which one to use by + * kconfig + */ + +#ifdef CONFIG_ESP32_SPIRAM_OCCUPY_HSPI_HOST +# define PSRAM_SPI_MODULE PERIPH_HSPI_MODULE +# define PSRAM_SPI_HOST HSPI_HOST +# define PSRAM_CLK_SIGNAL HSPICLK_OUT_IDX +# define PSRAM_SPI_NUM PSRAM_SPI_2 +# define PSRAM_SPICLKEN DPORT_SPI2_CLK_EN +#elif defined CONFIG_ESP32_SPIRAM_OCCUPY_VSPI_HOST +# define PSRAM_SPI_MODULE PERIPH_VSPI_MODULE +# define PSRAM_SPI_HOST VSPI_HOST +# define PSRAM_CLK_SIGNAL VSPICLK_OUT_IDX +# define PSRAM_SPI_NUM PSRAM_SPI_3 +# define PSRAM_SPICLKEN DPORT_SPI3_CLK_EN +#else /* set to SPI avoid HSPI and VSPI being used */ +# define PSRAM_SPI_MODULE PERIPH_SPI_MODULE +# define PSRAM_SPI_HOST SPI_HOST +# define PSRAM_CLK_SIGNAL SPICLK_OUT_IDX +# define PSRAM_SPI_NUM PSRAM_SPI_1 +# define PSRAM_SPICLKEN DPORT_SPI01_CLK_EN +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +typedef enum +{ + PSRAM_CLK_MODE_NORM = 0, /* Normal SPI mode */ + PSRAM_CLK_MODE_DCLK = 1, /* 2 clock cycles after CS is high level */ +} psram_clk_mode_t; + +typedef enum +{ + PSRAM_EID_SIZE_16MBITS = 0, + PSRAM_EID_SIZE_32MBITS = 1, + PSRAM_EID_SIZE_64MBITS = 2, +} psram_eid_size_t; + +typedef struct +{ + uint8_t flash_clk_io; + uint8_t flash_cs_io; + uint8_t psram_clk_io; + uint8_t psram_cs_io; + uint8_t psram_spiq_sd0_io; + uint8_t psram_spid_sd1_io; + uint8_t psram_spiwp_sd3_io; + uint8_t psram_spihd_sd2_io; +} psram_io_t; + +typedef enum +{ + PSRAM_SPI_1 = 0x1, + PSRAM_SPI_2, + PSRAM_SPI_3, + PSRAM_SPI_MAX , +} psram_spi_num_t; + +typedef enum +{ + PSRAM_CMD_QPI, + PSRAM_CMD_SPI, +} psram_cmd_mode_t; + +typedef struct +{ + uint16_t cmd; /* Command value */ + uint16_t cmd_bit_len; /* Command byte length */ + uint32_t *addr; /* Point to address value */ + uint16_t addr_bit_len; /* Address byte length */ + uint32_t *tx_data; /* Point to send data buffer */ + uint16_t tx_data_bit_len; /* Send data byte length. */ + uint32_t *rx_data; /* Point to recevie data buffer */ + uint16_t rx_data_bit_len; /* Recevie Data byte length. */ + uint32_t dummy_bit_len; +} psram_cmd_t; + +/* Structure describing vddsdio configuration. */ + +/* Note: this struct is also defined on esp32_pm.c */ + +struct rtc_vddsdio_config_s +{ + uint32_t force : 1; /* If 1, use configuration from RTC registers; + * if 0, use EFUSE/bootstrapping pins. + */ + uint32_t enable : 1; /* Enable VDDSDIO regulator */ + uint32_t tieh : 1; /* Select VDDSDIO voltage. One of + * RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + */ + uint32_t drefh : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefm : 2; /* Tuning parameter for VDDSDIO regulator */ + uint32_t drefl : 2; /* Tuning parameter for VDDSDIO regulator */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX; +static psram_clk_mode_t s_clk_mode = PSRAM_CLK_MODE_DCLK; +static uint64_t s_psram_id = 0; +static bool s_2t_mode_enabled = false; +static int extra_dummy = 0; + +/**************************************************************************** + * ROM Data + ****************************************************************************/ + +/* dummy_len_plus values defined in ROM for SPI flash configuration */ + +extern uint8_t g_rom_spiflash_dummy_len_plus[]; + +/**************************************************************************** + * Private Functions Prototypes + ****************************************************************************/ + +static int IRAM_ATTR esp32_get_vddsdio_config( + struct rtc_vddsdio_config_s *config); + +static void IRAM_ATTR +psram_cache_init(psram_cache_mode_t psram_cache_mode, + psram_vaddr_mode_t vaddrmode); + +static void psram_clear_spi_fifo(psram_spi_num_t spi_num); + +static void psram_set_basic_write_mode(psram_spi_num_t spi_num); + +static void psram_set_qio_write_mode(psram_spi_num_t spi_num); + +static void psram_set_qio_read_mode(psram_spi_num_t spi_num); + +static void psram_set_basic_read_mode(psram_spi_num_t spi_num); + +static void IRAM_ATTR +psram_cmd_recv_start(psram_spi_num_t spi_num, + uint32_t *data, + uint16_t rx_byte_len, + psram_cmd_mode_t cmd_mode); + +static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t *data); + +static void psram_cmd_end(int spi_num); + +static void psram_disable_qio_mode(psram_spi_num_t spi_num); + +static void psram_read_id(uint64_t *dev_id); + +static int IRAM_ATTR +psram_enable_qio_mode(psram_spi_num_t spi_num); + +static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address, + uint32_t *data_buffer, uint32_t data_len); + +static void spi_user_psram_read(psram_spi_num_t spi_num, uint32_t address, + uint32_t *data_buffer, uint32_t data_len); + +static int IRAM_ATTR +psram_2t_mode_enable(psram_spi_num_t spi_num); + +static int psram_2t_mode_check(psram_spi_num_t spi_num); + +/**************************************************************************** + * ROM function prototypes + ****************************************************************************/ + +extern void ets_delay_us(int delay_us); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp32_get_vddsdio_config + * + * Description: + * Get current VDDSDIO configuration. + * + * Input Parameters: + * Incoming parameter address of VDDSDIO configuration to be saved + * + * Returned Value: + * Zero (OK) is returned on success. + * + ****************************************************************************/ + +static int IRAM_ATTR esp32_get_vddsdio_config( + struct rtc_vddsdio_config_s *config) +{ + struct rtc_vddsdio_config_s *result = config; + uint32_t efuse_reg; + uint32_t strap_reg; + uint32_t sdio_conf_reg = getreg32(RTC_CNTL_SDIO_CONF_REG); + + result->drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) + >> RTC_CNTL_DREFH_SDIO_S; + result->drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) + >> RTC_CNTL_DREFM_SDIO_S; + result->drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) + >> RTC_CNTL_DREFL_SDIO_S; + + if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) + { + /* Get configuration from RTC */ + + result->force = 1; + result->enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) + >> RTC_CNTL_XPD_SDIO_REG_S; + result->tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) + >> RTC_CNTL_SDIO_TIEH_S; + + return OK; + } + + efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); + + if (efuse_reg & EFUSE_RD_SDIO_FORCE) + { + /* Get configuration from EFUSE */ + + result->force = 0; + result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) + >> EFUSE_RD_XPD_SDIO_REG_S; + result->tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) + >> EFUSE_RD_SDIO_TIEH_S; + + if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_BLK3_PART_RESERVE) == 0) + { + result->drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) + >> EFUSE_RD_SDIO_DREFH_S; + result->drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) + >> EFUSE_RD_SDIO_DREFM_S; + result->drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) + >> EFUSE_RD_SDIO_DREFL_S; + } + + return OK; + } + + /* Otherwise, VDD_SDIO is controlled by bootstrapping pin */ + + strap_reg = getreg32(GPIO_STRAP_REG); + result->force = 0; + result->tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V + : RTC_VDDSDIO_TIEH_3_3V; + result->enable = 1; + + return OK; +} + +static void psram_clear_spi_fifo(psram_spi_num_t spi_num) +{ + int i; + + for (i = 0; i < 16; i++) + { + putreg32(0, SPI_W0_REG(spi_num) + i * 4); + } +} + +/* set basic SPI write mode */ + +static void psram_set_basic_write_mode(psram_spi_num_t spi_num) +{ + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_QIO, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_DIO, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL, 0); +} + +/* set QPI write mode */ + +static void psram_set_qio_write_mode(psram_spi_num_t spi_num) +{ + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_FWRITE_QIO); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_DIO, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL, 0); +} + +/* set QPI read mode */ + +static void psram_set_qio_read_mode(psram_spi_num_t spi_num) +{ + modifyreg32(SPI_CTRL_REG(spi_num), 0, SPI_FREAD_QIO); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO, 0); +} + +/* set SPI read mode */ + +static void psram_set_basic_read_mode(psram_spi_num_t spi_num) +{ + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO, 0); +} + +/* start sending cmd/addr and optionally, receiving data */ + +static void IRAM_ATTR +psram_cmd_recv_start(psram_spi_num_t spi_num, + uint32_t *data, + uint16_t rx_byte_len, + psram_cmd_mode_t cmd_mode) +{ + /* Get CS1 */ + + modifyreg32(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M, 0); + modifyreg32(SPI_PIN_REG(PSRAM_SPI_1), 0, SPI_CS0_DIS_M); + + uint32_t mode_backup = (getreg32(SPI_USER_REG(spi_num)) >> + SPI_FWRITE_DUAL_S) & 0xf; + + uint32_t rd_mode_backup = getreg32(SPI_CTRL_REG(spi_num)) & + (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | + SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M); + + if (cmd_mode == PSRAM_CMD_SPI) + { + psram_set_basic_write_mode(spi_num); + psram_set_basic_read_mode(spi_num); + } + else + { + if (cmd_mode == PSRAM_CMD_QPI) + { + psram_set_qio_write_mode(spi_num); + psram_set_qio_read_mode(spi_num); + } + } + + /* Wait for SPI0 to idle */ + + while (getreg32(SPI_EXT2_REG(0)) != 0); + + modifyreg32(DPORT_HOST_INF_SEL_REG, 0, 1 << 14); + + /* Start send data */ + + modifyreg32(SPI_CMD_REG(spi_num), 0, SPI_USR); + + while ((getreg32(SPI_CMD_REG(spi_num)) & SPI_USR)); + + modifyreg32(DPORT_HOST_INF_SEL_REG, 1 << 14, 0); + + /* recover spi mode */ + + SET_PERI_REG_BITS(SPI_USER_REG(spi_num), + (data?SPI_FWRITE_DUAL_M:0xf), + mode_backup, SPI_FWRITE_DUAL_S); + + modifyreg32(SPI_CTRL_REG(spi_num), + (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | + SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M), 0); + + modifyreg32(SPI_CTRL_REG(spi_num), 0, rd_mode_backup); + + /* return cs to cs0 */ + + modifyreg32(SPI_PIN_REG(PSRAM_SPI_1), 0, SPI_CS1_DIS_M); + modifyreg32(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M, 0); + + if (data) + { + int idx = 0; + + /* Read data out */ + + do + { + *data++ = getreg32(SPI_W0_REG(spi_num) + (idx << 2)); + } + while (++idx < ((rx_byte_len / 4) + ((rx_byte_len % 4) ? 1 : 0))); + } +} + +static uint32_t backup_usr[3]; +static uint32_t backup_usr1[3]; +static uint32_t backup_usr2[3]; + +/* setup spi command/addr/data/dummy in user mode */ + +static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t *data) +{ + while (getreg32(SPI_CMD_REG(spi_num)) & SPI_USR); + + backup_usr[spi_num] = getreg32(SPI_USER_REG(spi_num)); + backup_usr1[spi_num] = getreg32(SPI_USER1_REG(spi_num)); + backup_usr2[spi_num] = getreg32(SPI_USER2_REG(spi_num)); + + /* Set command by user. */ + + if (data->cmd_bit_len != 0) + { + /* Max command length 16 bits. */ + + SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), + SPI_USR_COMMAND_BITLEN, + data->cmd_bit_len - 1, + SPI_USR_COMMAND_BITLEN_S); + + /* Enable command */ + + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_USR_COMMAND); + + /* Load command,bit15-0 is cmd value. */ + + SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), + SPI_USR_COMMAND_VALUE, + data->cmd, + SPI_USR_COMMAND_VALUE_S); + } + else + { + modifyreg32(SPI_USER_REG(spi_num), SPI_USR_COMMAND, 0); + SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, + 0, SPI_USR_COMMAND_BITLEN_S); + } + + /* Set Address by user. */ + + if (data->addr_bit_len != 0) + { + SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, + (data->addr_bit_len - 1), + SPI_USR_ADDR_BITLEN_S); + + /* Enable address */ + + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_USR_ADDR); + + /* Set address */ + + putreg32(*data->addr, SPI_ADDR_REG(spi_num)); + } + else + { + modifyreg32(SPI_USER_REG(spi_num), SPI_USR_ADDR, 0); + SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, + 0, SPI_USR_ADDR_BITLEN_S); + } + + /* Set data by user. */ + + uint32_t *p_tx_val = data->tx_data; + + if (data->tx_data_bit_len != 0) + { + /* Enable MOSI */ + + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_USR_MOSI); + + /* Load send buffer */ + + int len = (data->tx_data_bit_len + 31) / 32; + if (p_tx_val != NULL) + { + memcpy((void *) SPI_W0_REG(spi_num), p_tx_val, len * 4); + } + + /* Set data send buffer length.Max data length 64 bytes. */ + + SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, + (data->tx_data_bit_len - 1), + SPI_USR_MOSI_DBITLEN_S); + } + else + { + modifyreg32(SPI_USER_REG(spi_num), SPI_USR_MOSI, 0); + SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, + 0, SPI_USR_MOSI_DBITLEN_S); + } + + /* Set rx data by user. */ + + if (data->rx_data_bit_len != 0) + { + /* Enable MOSI */ + + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_USR_MISO); + + /* Set data send buffer length.Max data length 64 bytes. */ + + SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, + (data->rx_data_bit_len - 1), + SPI_USR_MISO_DBITLEN_S); + } + else + { + modifyreg32(SPI_USER_REG(spi_num), SPI_USR_MISO, 0); + SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, + 0, SPI_USR_MISO_DBITLEN_S); + } + + if (data->dummy_bit_len != 0) + { + modifyreg32(SPI_USER_REG(PSRAM_SPI_1), 0, SPI_USR_DUMMY); /* Dummy EN */ + SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, + data->dummy_bit_len - 1, + SPI_USR_DUMMY_CYCLELEN_S); /* DUMMY */ + } + else + { + modifyreg32(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY, 0); /* dummy en */ + SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, + 0, SPI_USR_DUMMY_CYCLELEN_S); /* DUMMY */ + } + + return 0; +} + +static void psram_cmd_end(int spi_num) +{ + while (getreg32(SPI_CMD_REG(spi_num)) & SPI_USR); + + putreg32(backup_usr[spi_num], SPI_USER_REG(spi_num)); + putreg32(backup_usr1[spi_num], SPI_USER1_REG(spi_num)); + putreg32(backup_usr2[spi_num], SPI_USER2_REG(spi_num)); +} + +/* exit QPI mode(set back to SPI mode) */ + +static void psram_disable_qio_mode(psram_spi_num_t spi_num) +{ + psram_cmd_t ps_cmd; + uint32_t cmd_exit_qpi; + + cmd_exit_qpi = PSRAM_EXIT_QMODE; + ps_cmd.tx_data_bit_len = 8; + if (s_clk_mode == PSRAM_CLK_MODE_DCLK) + { + switch (s_psram_mode) + { + case PSRAM_CACHE_F80M_S80M: + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + cmd_exit_qpi = PSRAM_EXIT_QMODE << 8; + ps_cmd.tx_data_bit_len = 16; + break; + } + } + + ps_cmd.tx_data = &cmd_exit_qpi; + ps_cmd.cmd = 0; + ps_cmd.cmd_bit_len = 0; + ps_cmd.addr = 0; + ps_cmd.addr_bit_len = 0; + ps_cmd.rx_data = NULL; + ps_cmd.rx_data_bit_len = 0; + ps_cmd.dummy_bit_len = 0; + psram_cmd_config(spi_num, &ps_cmd); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI); + psram_cmd_end(spi_num); +} + +/* read psram id */ + +static void psram_read_id(uint64_t *dev_id) +{ + psram_spi_num_t spi_num = PSRAM_SPI_1; + psram_disable_qio_mode(spi_num); + uint32_t dummy_bits = 0 + extra_dummy; + uint32_t psram_id[2] = + { + 0 + }; + + psram_cmd_t ps_cmd; + + uint32_t addr = 0; + ps_cmd.addr_bit_len = 3 * 8; + ps_cmd.cmd = PSRAM_DEVICE_ID; + ps_cmd.cmd_bit_len = 8; + + if (s_clk_mode == PSRAM_CLK_MODE_DCLK) + { + switch (s_psram_mode) + { + case PSRAM_CACHE_F80M_S80M: + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + ps_cmd.cmd_bit_len = 2; /* this 2 bits is used to delay 2 clk cycle */ + ps_cmd.cmd = 0; + addr = (PSRAM_DEVICE_ID << 24) | 0; + ps_cmd.addr_bit_len = 4 * 8; + break; + } + } + + ps_cmd.addr = &addr; + ps_cmd.tx_data_bit_len = 0; + ps_cmd.tx_data = NULL; + ps_cmd.rx_data_bit_len = 8 * 8; + ps_cmd.rx_data = psram_id; + ps_cmd.dummy_bit_len = dummy_bits; + + psram_cmd_config(spi_num, &ps_cmd); + psram_clear_spi_fifo(spi_num); + psram_cmd_recv_start(spi_num, ps_cmd.rx_data, + ps_cmd.rx_data_bit_len / 8, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + *dev_id = (uint64_t)(((uint64_t)psram_id[1] << 32) | psram_id[0]); +} + +/* enter QPI mode */ + +static int IRAM_ATTR +psram_enable_qio_mode(psram_spi_num_t spi_num) +{ + psram_cmd_t ps_cmd; + uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0; + + ps_cmd.cmd_bit_len = 0; + + if (s_clk_mode == PSRAM_CLK_MODE_DCLK) + { + switch (s_psram_mode) + { + case PSRAM_CACHE_F80M_S80M: + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + ps_cmd.cmd_bit_len = 2; + break; + } + } + + ps_cmd.cmd = 0; + ps_cmd.addr = &addr; + ps_cmd.addr_bit_len = 8; + ps_cmd.tx_data = NULL; + ps_cmd.tx_data_bit_len = 0; + ps_cmd.rx_data = NULL; + ps_cmd.rx_data_bit_len = 0; + ps_cmd.dummy_bit_len = 0; + psram_cmd_config(spi_num, &ps_cmd); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + return OK; +} + +#if defined(CONFIG_ESP32_SPIRAM_2T_MODE) +/* use SPI user mode to write psram */ + +static void spi_user_psram_write(psram_spi_num_t spi_num, uint32_t address, + uint32_t *data_buffer, uint32_t data_len) +{ + uint32_t addr = (PSRAM_QUAD_WRITE << 24) | (address & 0x7fffff); + psram_cmd_t ps_cmd; + ps_cmd.cmd_bit_len = 0; + ps_cmd.cmd = 0; + ps_cmd.addr = &addr; + ps_cmd.addr_bit_len = 4 * 8; + ps_cmd.tx_data_bit_len = 32 * 8; + ps_cmd.tx_data = NULL; + ps_cmd.rx_data_bit_len = 0; + ps_cmd.rx_data = NULL; + ps_cmd.dummy_bit_len = 0; + + for (uint32_t i = 0; i < data_len; i += 32) + { + psram_clear_spi_fifo(spi_num); + addr = (PSRAM_QUAD_WRITE << 24) | ((address & 0x7fffff) + i); + ps_cmd.tx_data = data_buffer + (i / 4); + psram_cmd_config(spi_num, &ps_cmd); + psram_cmd_recv_start(spi_num, ps_cmd.rx_data, + ps_cmd.rx_data_bit_len / 8, PSRAM_CMD_QPI); + } + + psram_cmd_end(spi_num); +} + +/* use SPI user mode to read psram */ + +static void spi_user_psram_read(psram_spi_num_t spi_num, uint32_t address, + uint32_t *data_buffer, uint32_t data_len) +{ + uint32_t addr = (PSRAM_FAST_READ_QUAD << 24) | (address & 0x7fffff); + uint32_t dummy_bits = PSRAM_FAST_READ_QUAD_DUMMY + 1; + + psram_cmd_t ps_cmd; + ps_cmd.cmd_bit_len = 0; + ps_cmd.cmd = 0; + ps_cmd.addr = &addr; + ps_cmd.addr_bit_len = 4 * 8; + ps_cmd.tx_data_bit_len = 0; + ps_cmd.tx_data = NULL; + ps_cmd.rx_data_bit_len = 32 * 8; + ps_cmd.dummy_bit_len = dummy_bits + extra_dummy; + + for (uint32_t i = 0; i < data_len; i += 32) + { + psram_clear_spi_fifo(spi_num); + addr = (PSRAM_FAST_READ_QUAD << 24) | ((address & 0x7fffff) + i); + ps_cmd.rx_data = data_buffer + (i / 4); + psram_cmd_config(spi_num, &ps_cmd); + psram_cmd_recv_start(spi_num, ps_cmd.rx_data, + ps_cmd.rx_data_bit_len / 8, PSRAM_CMD_QPI); + } + + psram_cmd_end(spi_num); +} + +/* enable psram 2T mode */ + +static int IRAM_ATTR +psram_2t_mode_enable(psram_spi_num_t spi_num) +{ + psram_disable_qio_mode(spi_num); + + /* configure psram clock as 5 MHz */ + + uint32_t div = rtc_clk_apb_freq_get() / 5000000; + esp_rom_spiflash_config_clk(div, spi_num); + + psram_cmd_t ps_cmd; + + /* setp1: send cmd 0x5e + * send one more bit clock after send cmd + */ + + ps_cmd.cmd = 0x5e; + ps_cmd.cmd_bit_len = 8; + ps_cmd.addr_bit_len = 0; + ps_cmd.addr = 0; + ps_cmd.tx_data_bit_len = 0; + ps_cmd.tx_data = NULL; + ps_cmd.rx_data_bit_len = 0; + ps_cmd.rx_data = NULL; + ps_cmd.dummy_bit_len = 1; + psram_cmd_config(spi_num, &ps_cmd); + psram_clear_spi_fifo(spi_num); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + + /* setp2: send cmd 0x5f + * send one more bit clock after send cmd + */ + + ps_cmd.cmd = 0x5f; + psram_cmd_config(spi_num, &ps_cmd); + psram_clear_spi_fifo(spi_num); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + + /* setp3: keep cs as high level + * send 128 cycles clock + * send 1 bit high levle in ninth clock from the back to PSRAM SIO1 + */ + + GPIO_OUTPUT_SET(D0WD_PSRAM_CS_IO, 1); + gpio_matrix_out(D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0); + + gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0); + gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0); + gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0); + gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0); + + uint32_t w_data_2t[4] = + { + 0x0, 0x0, 0x0, 0x00010000 + }; + + ps_cmd.cmd = 0; + ps_cmd.cmd_bit_len = 0; + ps_cmd.tx_data_bit_len = 128; + ps_cmd.tx_data = w_data_2t; + ps_cmd.dummy_bit_len = 0; + psram_clear_spi_fifo(spi_num); + psram_cmd_config(spi_num, &ps_cmd); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + + gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0); + gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0); + gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0); + gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0); + + gpio_matrix_out(D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0); + + /* setp4: send cmd 0x5f + * send one more bit clock after send cmd + */ + + ps_cmd.cmd = 0x5f; + ps_cmd.cmd_bit_len = 8; + ps_cmd.tx_data_bit_len = 0; + ps_cmd.tx_data = NULL; + ps_cmd.dummy_bit_len = 1; + psram_cmd_config(spi_num, &ps_cmd); + psram_clear_spi_fifo(spi_num); + psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); + psram_cmd_end(spi_num); + + /* configure psram clock back to the default value */ + + switch (s_psram_mode) + { + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, spi_num); + break; + case PSRAM_CACHE_F80M_S80M: + esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, spi_num); + break; + default: + break; + } + + psram_enable_qio_mode(spi_num); + return OK; +} + +#define CHECK_DATA_LEN (1024) +#define CHECK_ADDR_STEP (0x100000) +#define SIZE_32MBIT (0x400000) +#define SIZE_64MBIT (0x800000) + +static int psram_2t_mode_check(psram_spi_num_t spi_num) +{ + uint32_t addr; + uint8_t w_check_data[CHECK_DATA_LEN] = + { + 0 + }; + + uint8_t r_check_data[CHECK_DATA_LEN] = + { + 0 + }; + + for (uint32_t addr = 0; addr < SIZE_32MBIT; addr += CHECK_ADDR_STEP) + { + spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, + CHECK_DATA_LEN); + } + + memset(w_check_data, 0xff, sizeof(w_check_data)); + + for (addr = SIZE_32MBIT; addr < SIZE_64MBIT; addr += CHECK_ADDR_STEP) + { + spi_user_psram_write(spi_num, addr, (uint32_t *)w_check_data, + CHECK_DATA_LEN); + } + + for (uint32_t addr = 0; addr < SIZE_32MBIT; addr += CHECK_ADDR_STEP) + { + spi_user_psram_read(spi_num, addr, (uint32_t *)r_check_data, + CHECK_DATA_LEN); + for (uint32_t j = 0; j < CHECK_DATA_LEN; j++) + { + if (r_check_data[j] != 0xff) + { + return -EFAULT; + } + } + } + + return ESP_OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void psram_set_cs_timing(psram_spi_num_t spi_num, psram_clk_mode_t clk_mode) +{ + if (clk_mode == PSRAM_CLK_MODE_NORM) + { + modifyreg32(SPI_USER_REG(spi_num), 0, SPI_CS_HOLD_M | SPI_CS_SETUP_M); + + /* Set cs time. */ + + SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_HOLD_TIME_V, 1, + SPI_HOLD_TIME_S); + SET_PERI_REG_BITS(SPI_CTRL2_REG(spi_num), SPI_SETUP_TIME_V, 0, + SPI_SETUP_TIME_S); + } + else + { + modifyreg32(SPI_USER_REG(spi_num), + SPI_CS_HOLD_M | SPI_CS_SETUP_M, 0); + } +} + +/* spi param init for psram */ + +void IRAM_ATTR +psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode) +{ + modifyreg32(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5, 0); + + /* SPI_CPOL & SPI_CPHA */ + + modifyreg32(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE, 0); + modifyreg32(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE, 0); + + /* SPI bit order */ + + modifyreg32(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER, 0); + modifyreg32(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER, 0); + + /* SPI bit order */ + + modifyreg32(SPI_USER_REG(spi_num), SPI_DOUTDIN, 0); + + /* May be not must to do. */ + + putreg32(0, SPI_USER1_REG(spi_num)); + + /* SPI mode type */ + + modifyreg32(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE, 0); + memset((void *)SPI_W0_REG(spi_num), 0, 16 * 4); + psram_set_cs_timing(spi_num, s_clk_mode); +} + +/* psram gpio init , different working frequency we have different + * solutions + */ + +static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, + psram_cache_mode_t mode) +{ + int spi_cache_dummy = 0; + uint32_t rd_mode_reg = getreg32(SPI_CTRL_REG(0)); + + if (rd_mode_reg & SPI_FREAD_QIO_M) + { + spi_cache_dummy = SPI0_R_QIO_DUMMY_CYCLELEN; + } + else + { + if (rd_mode_reg & SPI_FREAD_DIO_M) + { + spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; + SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_ADDR_BITLEN_V, + SPI0_R_DIO_ADDR_BITSLEN, SPI_USR_ADDR_BITLEN_S); + } + else + { + if (rd_mode_reg & (SPI_FREAD_QUAD_M | SPI_FREAD_DUAL_M)) + { + spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; + } + else + { + spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN; + } + } + } + + switch (mode) + { + case PSRAM_CACHE_F80M_S40M: + extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; + g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = + PSRAM_IO_MATRIX_DUMMY_80M; + g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = + PSRAM_IO_MATRIX_DUMMY_40M; + SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), + SPI_USR_DUMMY_CYCLELEN_V, + spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, + SPI_USR_DUMMY_CYCLELEN_S); /* DUMMY */ + esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); + esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT); + break; + + case PSRAM_CACHE_F80M_S80M: + extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M; + g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = + PSRAM_IO_MATRIX_DUMMY_80M; + g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = + PSRAM_IO_MATRIX_DUMMY_80M; + SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), + SPI_USR_DUMMY_CYCLELEN_V, + spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_80M, + SPI_USR_DUMMY_CYCLELEN_S); /* DUMMY */ + esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_CACHE_PORT); + esp_rom_spiflash_config_clk(_SPI_80M_CLK_DIV, _SPI_FLASH_PORT); + break; + + case PSRAM_CACHE_F40M_S40M: + extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M; + g_rom_spiflash_dummy_len_plus[_SPI_CACHE_PORT] = + PSRAM_IO_MATRIX_DUMMY_40M; + g_rom_spiflash_dummy_len_plus[_SPI_FLASH_PORT] = + PSRAM_IO_MATRIX_DUMMY_40M; + SET_PERI_REG_BITS(SPI_USER1_REG(_SPI_CACHE_PORT), + SPI_USR_DUMMY_CYCLELEN_V, + spi_cache_dummy + PSRAM_IO_MATRIX_DUMMY_40M, + SPI_USR_DUMMY_CYCLELEN_S); /* DUMMY */ + esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_CACHE_PORT); + esp_rom_spiflash_config_clk(_SPI_40M_CLK_DIV, _SPI_FLASH_PORT); + + break; + + default: + break; + } + + SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); /* dummy enable */ + + /* In bootloader, all the signals are already configured */ + + /* We keep the following code in case the bootloader is some older + * version. + */ + + gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0); + gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0); + gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0); + gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0); + gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0); + gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0); + gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0); + gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0); + gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0); + gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0); + + /* select pin function gpio */ + + if ((psram_io->flash_clk_io == SPI_IOMUX_PIN_NUM_CLK) && + (psram_io->flash_clk_io != psram_io->psram_clk_io)) + { + /* flash clock signal should come from IO MUX. */ + + esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_1); + } + else + { + /* flash clock signal should come from GPIO matrix. */ + + esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_2); + } + + esp32_configgpio(psram_io->flash_cs_io, OUTPUT | FUNCTION_2); + esp32_configgpio(psram_io->psram_cs_io, OUTPUT | FUNCTION_2); + esp32_configgpio(psram_io->psram_clk_io, OUTPUT | FUNCTION_2); + esp32_configgpio(psram_io->psram_spiq_sd0_io, OUTPUT | INPUT | FUNCTION_2); + esp32_configgpio(psram_io->psram_spid_sd1_io, OUTPUT | INPUT | FUNCTION_2); + esp32_configgpio(psram_io->psram_spihd_sd2_io, OUTPUT | INPUT | \ + FUNCTION_2); + esp32_configgpio(psram_io->psram_spiwp_sd3_io, OUTPUT | INPUT | \ + FUNCTION_2); + +#if 0 + uint32_t flash_id = g_rom_flashchip.device_id; + if (flash_id == FLASH_ID_GD25LQ32C) + { + /* Set drive ability for 1.8v flash in 80Mhz. */ + + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_cs_io], FUN_DRV_V, + 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->flash_clk_io], FUN_DRV_V, + 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_cs_io], FUN_DRV_V, + 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_clk_io], FUN_DRV_V, + 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiq_sd0_io], + FUN_DRV_V, 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spid_sd1_io], + FUN_DRV_V, 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spihd_sd2_io], + FUN_DRV_V, 3, FUN_DRV_S); + SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[psram_io->psram_spiwp_sd3_io], + FUN_DRV_V, 3, FUN_DRV_S); + } +#endif +} + +psram_size_t psram_get_size(void) +{ + if ((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || + PSRAM_IS_64MBIT_TRIAL(s_psram_id)) + { + return s_2t_mode_enabled ? PSRAM_SIZE_32MBITS : PSRAM_SIZE_64MBITS; + } + else + { + if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_32MBITS) + { + return PSRAM_SIZE_32MBITS; + } + else + { + if (PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_16MBITS) + { + return PSRAM_SIZE_16MBITS; + } + else + { + return PSRAM_SIZE_MAX; + } + } + } +} + +/* used in UT only */ + +bool psram_is_32mbit_ver0(void) +{ + return PSRAM_IS_32MBIT_VER0(s_psram_id); +} + +/* PSRAM mode init will overwrite original flash speed mode, so that it is + * possible to change psram and flash speed after OTA. + * Flash read mode(QIO/QOUT/DIO/DOUT) will not be changed in app bin. + * It is decided by bootloader, OTA can not change this mode. + */ + +int IRAM_ATTR +psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) /* psram init */ +{ + struct rtc_vddsdio_config_s cfg; + + /* Let's assume we are not worring about OTA issue and ignore for now */ + + psram_io_t psram_io = + { + 0 + }; + + uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, + EFUSE_RD_CHIP_VER_PKG); + uint32_t pkg_ver = chip_ver & 0x7; + uint32_t spiconfig; + + if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) + { + minfo("This chip is ESP32-D2WD\n"); + + esp32_get_vddsdio_config(&cfg); + if (cfg.tieh != RTC_VDDSDIO_TIEH_1_8V) + { + merr("VDDSDIO is not 1.8V"); + return -EFAULT; + } + + psram_io.psram_clk_io = D2WD_PSRAM_CLK_IO; + psram_io.psram_cs_io = D2WD_PSRAM_CS_IO; + } + else + { + if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || + (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) + { + minfo("This chip is ESP32-PICO"); + + esp32_get_vddsdio_config(&cfg); + if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) + { + merr("VDDSDIO is not 3.3V"); + return -EFAULT; + } + + s_clk_mode = PSRAM_CLK_MODE_NORM; + psram_io.psram_clk_io = PICO_PSRAM_CLK_IO; + psram_io.psram_cs_io = PICO_PSRAM_CS_IO; + } + else + { + if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || + (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)) + { + minfo("This chip is ESP32-D0WD\n"); + psram_io.psram_clk_io = D0WD_PSRAM_CLK_IO; + psram_io.psram_cs_io = D0WD_PSRAM_CS_IO; + } + else + { + merr("Not a valid or known package id: %d", pkg_ver); + PANIC(); + } + } + } + + spiconfig = ets_efuse_get_spiconfig(); + if (spiconfig == EFUSE_SPICFG_SPI_DEFAULTS) + { + minfo("SPI Defaults\n"); + psram_io.flash_clk_io = SPI_IOMUX_PIN_NUM_CLK; + psram_io.flash_cs_io = SPI_IOMUX_PIN_NUM_CS; + psram_io.psram_spiq_sd0_io = PSRAM_SPIQ_SD0_IO; + psram_io.psram_spid_sd1_io = PSRAM_SPID_SD1_IO; + psram_io.psram_spiwp_sd3_io = PSRAM_SPIWP_SD3_IO; + psram_io.psram_spihd_sd2_io = PSRAM_SPIHD_SD2_IO; + } + else + { + if (spiconfig == EFUSE_SPICFG_HSPI_DEFAULTS) + { + minfo("HSPI Defaults\n"); + psram_io.flash_clk_io = FLASH_HSPI_CLK_IO; + psram_io.flash_cs_io = FLASH_HSPI_CS_IO; + psram_io.psram_spiq_sd0_io = PSRAM_HSPI_SPIQ_SD0_IO; + psram_io.psram_spid_sd1_io = PSRAM_HSPI_SPID_SD1_IO; + psram_io.psram_spiwp_sd3_io = PSRAM_HSPI_SPIWP_SD3_IO; + psram_io.psram_spihd_sd2_io = PSRAM_HSPI_SPIHD_SD2_IO; + } + else + { + minfo("SPI EFUSE Config\n"); + psram_io.flash_clk_io = EFUSE_SPICFG_RET_SPICLK(spiconfig); + psram_io.flash_cs_io = EFUSE_SPICFG_RET_SPICS0(spiconfig); + psram_io.psram_spiq_sd0_io = EFUSE_SPICFG_RET_SPIQ(spiconfig); + psram_io.psram_spid_sd1_io = EFUSE_SPICFG_RET_SPID(spiconfig); + psram_io.psram_spihd_sd2_io = EFUSE_SPICFG_RET_SPIHD(spiconfig); + + /* If flash mode is set to QIO or QOUT, the WP pin is equal the + * value configured in bootloader. If flash mode is set to DIO or + * DOUT, the WP pin should config it via menuconfig. + */ + + /* Since the default value is the same from the bootloader + * Let's use it for now. + */ + + psram_io.psram_spiwp_sd3_io = CONFIG_ESP32_SPIRAM_SPIWP_SD3_PIN; + } + } + + assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode."); + s_psram_mode = mode; + + putreg32(0x1, SPI_EXT3_REG(0)); + modifyreg32(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M, 0); + + psram_spi_init(PSRAM_SPI_1, mode); + + switch (mode) + { + case PSRAM_CACHE_F80M_S80M: + gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + if (s_clk_mode == PSRAM_CLK_MODE_DCLK) + { + /* We need to delay CLK to the PSRAM with respect to the clock + * signal as output by the SPI peripheral. We do this by routing + * it signal to signal 224/225, which are used as a loopback; the + * extra run through the GPIO matrix causes the delay. We use + * GPIO20 (which is not in any package but has pad logic in + * silicon) as a temporary pad for this. So the signal path is: + * SPI CLK --> GPIO28 --> signal224(in then out) --> + * internal GPIO29 --> signal225(in then out) --> + * GPIO17(PSRAM CLK) + */ + + minfo("clk_mode == PSRAM_CLK_MODE_DCLK\n"); + gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0); + gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0); + gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0); + gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0); + gpio_matrix_out(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0); + } + else + { + minfo("clk_io == OUT_IDX\n"); + gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); + } + break; + } + + /* Rise VDDSIO for 1.8V psram. */ + + /* bootloader_common_vddsdio_configure(); */ + + /* GPIO related settings */ + + psram_gpio_config(&psram_io, mode); + psram_read_id(&s_psram_id); + + minfo("psram ID = 0x%x\n", (uint32_t)s_psram_id); + + if (!PSRAM_IS_VALID(s_psram_id)) + { + minfo("PSRAM ID NOT VALID\n"); + return -ENODEV; + } + + if (psram_is_32mbit_ver0()) + { + s_clk_mode = PSRAM_CLK_MODE_DCLK; + if (mode == PSRAM_CACHE_F80M_S80M) + { +#ifdef CONFIG_ESP32_SPIRAM_OCCUPY_NO_HOST + merr("This version of PSRAM needs to claim an extra SPI" + "peripheral at 80MHz. Please either: choose lower" + "frequency by SPIRAM_SPEED_, or select one SPI peripheral" + "it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig."); + abort(); +#else + /* note: If the third mode(80Mhz+80Mhz) is enabled for 32MBit 1V8 + * psram, one of HSPI/VSPI port will be occupied by the system + * (according to kconfig). Application code should never touch + * HSPI/VSPI hardware in this case. We try to stop applications + * from doing this using the drivers by claiming the port for + * ourselves + */ + + gpio_matrix_out(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0); + + /* use spi3 clock,but use spi1 data/cs wires + * We get a solid 80MHz clock from SPI3 by setting it up, starting + * a transaction, waiting until it is in progress, then cutting the + * clock (but not the reset!) to that peripheral. + */ + + putreg32(32 << 24, SPI_ADDR_REG(PSRAM_SPI_NUM)); + modifyreg32(SPI_CMD_REG(PSRAM_SPI_NUM), 0, SPI_FLASH_READ_M); + uint32_t spi_status; + while (1) + { + spi_status = getreg32(SPI_EXT2_REG(PSRAM_SPI_NUM)); + if (spi_status != 0 && spi_status != 1) + { + modifyreg32(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1, 0); + break; + } + } +#endif + } + } + else + { + /* For other psram, we don't need any extra clock cycles after cs get + * back to high level + */ + + s_clk_mode = PSRAM_CLK_MODE_NORM; + gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0); + gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0); + gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); + } + + /* Update cs timing according to psram driving method. */ + + psram_set_cs_timing(PSRAM_SPI_1, s_clk_mode); + psram_set_cs_timing(_SPI_CACHE_PORT, s_clk_mode); + psram_enable_qio_mode(PSRAM_SPI_1); + + if (((PSRAM_SIZE_ID(s_psram_id) == PSRAM_EID_SIZE_64MBITS) || + PSRAM_IS_64MBIT_TRIAL(s_psram_id))) + { +#if defined(CONFIG_ESP32_SPIRAM_2T_MODE) +# if CONFIG_ESP32_SPIRAM_BANKSWITCH_ENABLE + merr("PSRAM 2T mode and SPIRAM bank switching can not enabled\ + meanwhile. Please read the help text for SPIRAM_2T_MODE in the\ + project configuration menu."); + abort(); +# endif + /* Note: 2T mode command should not be sent twice, + * otherwise psram would get back to normal mode. + */ + + if (psram_2t_mode_check(PSRAM_SPI_1) != OK) + { + psram_2t_mode_enable(PSRAM_SPI_1); + if (psram_2t_mode_check(PSRAM_SPI_1) != OK) + { + merr("PSRAM 2T mode enable fail!\n"); + return -EINVAL; + } + } + + s_2t_mode_enabled = true; + minfo("PSRAM is in 2T mode"); +#endif + } + + psram_cache_init(mode, vaddrmode); + + return OK; +} + +/* register initialization for sram cache params and r/w commands */ + +static void IRAM_ATTR +psram_cache_init(psram_cache_mode_t psram_cache_mode, + psram_vaddr_mode_t vaddrmode) +{ + uint32_t regval; + + switch (psram_cache_mode) + { + case PSRAM_CACHE_F80M_S80M: + + /* flash 1 div clk,80+40; */ + + modifyreg32(SPI_DATE_REG(0), BIT(31), 0); + + /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. + * FLASH DIV 2+SRAM DIV4 + */ + + modifyreg32(SPI_DATE_REG(0), BIT(30), 0); + break; + + case PSRAM_CACHE_F80M_S40M: + modifyreg32(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M, 0); + SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, + SPI_CLKDIV_PRE_S); + SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S); + SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S); + SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S); + modifyreg32(SPI_DATE_REG(0), BIT(31), 0); /* flash 1 div clk */ + + /* pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. */ + + modifyreg32(SPI_DATE_REG(0), BIT(30), 0); + break; + case PSRAM_CACHE_F40M_S40M: + default: + + /* flash 1 div clk */ + + modifyreg32(SPI_DATE_REG(0), BIT(31), 0); + + /* pre clk div */ + + modifyreg32(SPI_DATE_REG(0), BIT(30), 0); + break; + } + + /* disable dio mode for cache command */ + + modifyreg32(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M, 0); + + /* enable qio mode for cache command */ + + modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_SRAM_QIO_M); + + /* enable cache read command */ + + modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_RCMD_M); + + /* enable cache write command */ + + modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_CACHE_SRAM_USR_WCMD_M); + + /* write address for cache command */ + + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, + SPI_SRAM_ADDR_BITLEN_S); + + /* enable cache read dummy */ + + modifyreg32(SPI_CACHE_SCTRL_REG(0), 0, SPI_USR_RD_SRAM_DUMMY_M); + + /* config sram cache r/w command */ + + SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), + SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7, + SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), + SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, + PSRAM_FAST_READ_QUAD, + SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); /* 0xEB */ + + SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), + SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7, + SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); + + SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), + SPI_CACHE_SRAM_USR_WR_CMD_VALUE, + PSRAM_QUAD_WRITE, + SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); /* 0x38 */ + + /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */ + + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, + PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, + SPI_SRAM_DUMMY_CYCLELEN_S); + + switch (psram_cache_mode) + { + /* in this mode , no delay is needed */ + + case PSRAM_CACHE_F80M_S80M: + break; + + /* if sram is @40M, need 2 cycles of delay */ + + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + if (s_clk_mode == PSRAM_CLK_MODE_DCLK) + { + /* read command length, 2 bytes(1byte for delay), sending in qio + * mode in cache + */ + + SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), + SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15, + SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); + + /* 0xEB, read command value,(0x00 for delay,0xeb for cmd) */ + + SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), + SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, + ((PSRAM_FAST_READ_QUAD) << 8), + SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); + + /* write command length,2 bytes(1byte for delay,send in qio mode + * in cache) + */ + + SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), + SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15, + SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); + + /* 0x38, write command value,(0x00 for delay) */ + + SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), + SPI_CACHE_SRAM_USR_WR_CMD_VALUE, + ((PSRAM_QUAD_WRITE) << 8), + SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); + + /* dummy, psram cache : 40m--+1dummy; 80m--+2dummy */ + + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), + SPI_SRAM_DUMMY_CYCLELEN_V, + PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy, + SPI_SRAM_DUMMY_CYCLELEN_S); + } + break; + } + + modifyreg32(DPORT_PRO_CACHE_CTRL_REG, + DPORT_PRO_DRAM_HL | DPORT_PRO_DRAM_SPLIT, 0); + modifyreg32(DPORT_APP_CACHE_CTRL_REG, + DPORT_APP_DRAM_HL | DPORT_APP_DRAM_SPLIT, 0); + if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) + { + modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_HL); + modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_HL); + } + else + { + if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) + { + modifyreg32(DPORT_PRO_CACHE_CTRL_REG, 0, DPORT_PRO_DRAM_SPLIT); + modifyreg32(DPORT_APP_CACHE_CTRL_REG, 0, DPORT_APP_DRAM_SPLIT); + } + } + + /* use Dram1 to visit ext sram. */ + + modifyreg32(DPORT_PRO_CACHE_CTRL1_REG, + DPORT_PRO_CACHE_MASK_DRAM1 | DPORT_PRO_CACHE_MASK_OPSDRAM, 0); + + /* cache page mode : + * 1 -->16k + * 4 -->2k + * 0 -->32k,(accord with the settings in cache_sram_mmu_set) + */ + + /* get into unknow exception if not comment */ + + regval = getreg32(DPORT_PRO_CACHE_CTRL1_REG); + regval &= ~(DPORT_PRO_CMMU_SRAM_PAGE_MODE << + DPORT_PRO_CMMU_SRAM_PAGE_MODE_S); + putreg32(regval, DPORT_PRO_CACHE_CTRL1_REG); + + /* use DRAM1 to visit ext sram. */ + + modifyreg32(DPORT_APP_CACHE_CTRL1_REG, + DPORT_APP_CACHE_MASK_DRAM1 | + DPORT_APP_CACHE_MASK_OPSDRAM, 0); + + /* cache page mode : + * 1 -->16k + * 4 -->2k + * 0 -->32k, (accord with the settings in cache_sram_mmu_set) + */ + + regval = getreg32(DPORT_APP_CACHE_CTRL1_REG); + regval &= ~(DPORT_APP_CMMU_SRAM_PAGE_MODE << + DPORT_APP_CMMU_SRAM_PAGE_MODE_S); + putreg32(regval, DPORT_APP_CACHE_CTRL1_REG); + + /* ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) */ + + modifyreg32(SPI_PIN_REG(0), SPI_CS1_DIS_M, 0); +} + +#endif /* CONFIG_ESP32_SPIRAM */ diff --git a/arch/xtensa/src/esp32/esp32_psram.h b/arch/xtensa/src/esp32/esp32_psram.h new file mode 100644 index 0000000000..110c13f00c --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_psram.h @@ -0,0 +1,91 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_psram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_PSRAM_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_PSRAM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +typedef enum +{ + PSRAM_CACHE_F80M_S40M = 0, + PSRAM_CACHE_F40M_S40M, + PSRAM_CACHE_F80M_S80M, + PSRAM_CACHE_MAX, +} psram_cache_mode_t; + +typedef enum +{ + PSRAM_SIZE_16MBITS = 0, + PSRAM_SIZE_32MBITS = 1, + PSRAM_SIZE_64MBITS = 2, + PSRAM_SIZE_MAX, +} psram_size_t; + +/* See the TRM, chapter PID/MPU/MMU, header 'External RAM' for the + * definitions of these modes. Important is that NORMAL works with the app + * CPU cache disabled, but gives huge cache coherency issues when both app + * and pro CPU are enabled. LOWHIGH and EVENODD do not have these coherency + * issues but cannot be used when the app CPU cache is disabled. + */ + +typedef enum +{ + PSRAM_VADDR_MODE_NORMAL = 0, /* App and Pro CPU use their own flash cache + * for external RAM access + */ + + PSRAM_VADDR_MODE_LOWHIGH, /* App and Pro CPU share external RAM caches: + * pro CPU has low 2M, app CPU has high 2M + */ + PSRAM_VADDR_MODE_EVENODD, /* App and Pro CPU share external RAM caches: + * pro CPU does even 32yte ranges, app does + * odd ones. + */ +} psram_vaddr_mode_t; + +/* Description: Get PSRAM size + * return: + * - PSRAM_SIZE_MAX if psram not enabled or not valid + * - PSRAM size + */ + +psram_size_t psram_get_size(void); + +/* Description: PSRAM cache enable function + * + * Esp-idf uses this to initialize cache for psram, mapping it into the main + * memory address space. + * + * param: + * mode SPI mode to access psram in + * vaddrmode Mode the psram cache works in. + * return: + * OK on success + * EINVAL when VSPI peripheral is needed but cannot be + * claimed. + */ + +int psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t + vaddrmode); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_HIMEM_H */ diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c new file mode 100644 index 0000000000..9989aef9c6 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -0,0 +1,385 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_spiflash.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_ESP32_SPIRAM + +#include +#include +#include +#include +#include +#include +#include + +#include "esp32_spiram.h" +#include "esp32_psram.h" +#include "xtensa.h" +#include "xtensa_attr.h" +#include "hardware/esp32_soc.h" +#include "hardware/esp32_dport.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef CONFIG_SMP +# define PSRAM_MODE PSRAM_VADDR_MODE_NORMAL +#else +#if CONFIG_ESP32_MEMMAP_SPIRAM_CACHE_EVENODD +# define PSRAM_MODE PSRAM_VADDR_MODE_EVENODD +#else +# define PSRAM_MODE PSRAM_VADDR_MODE_LOWHIGH +#endif +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Let's to assume SPIFLASH SPEED == SPIRAM SPEED for now */ + +#if CONFIG_ESP32_SPIRAM_SPEED_40M +# define PSRAM_SPEED PSRAM_CACHE_F40M_S40M +#elif CONFIG_ESP32_SPIRAM_SPEED_80M +# define PSRAM_SPEED PSRAM_CACHE_F80M_S80M +#else +# error "FLASH speed can only be equal to or higher than SRAM speed while SRAM is enabled!" +#endif + +#if defined(CONFIG_BOOT_SDRAM_DATA) +extern uint8_t _ext_ram_bss_start; +extern uint8_t _ext_ram_bss_end; +#endif +static bool spiram_inited = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* If no function in esp_himem.c is used, this function will be linked into + * the binary instead of the one in esp_himem.c, automatically making sure + * no memory is reserved if no himem function is used. + */ + +size_t __attribute__((weak)) esp_himem_reserved_area_size(void) +{ + return 0; +} + +static int spiram_size_usable_for_malloc(void) +{ + int s = esp_spiram_get_size(); + + if (s > 4 * 1024 * 1024) + { + s = 4 * 1024 * 1024; /* we can map at most 4MiB */ + } + + return s - esp_himem_reserved_area_size(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void IRAM_ATTR esp_spiram_init_cache(void) +{ + /* Enable external RAM in MMU */ + + cache_sram_mmu_set(0, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128); + + /* Flush and enable icache for APP CPU */ + +#ifdef CONFIG_SMP + DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, + DPORT_APP_CACHE_MASK_DRAM1); + cache_sram_mmu_set(1, 0, SOC_EXTRAM_DATA_LOW, 0, 32, 128); +#endif +} + +esp_spiram_size_t esp_spiram_get_chip_size(void) +{ + if (!spiram_inited) + { + merr("SPI RAM not initialized"); + return ESP_SPIRAM_SIZE_INVALID; + } + + psram_size_t psram_size = psram_get_size(); + switch (psram_size) + { + case PSRAM_SIZE_16MBITS: + return ESP_SPIRAM_SIZE_16MBITS; + + case PSRAM_SIZE_32MBITS: + return ESP_SPIRAM_SIZE_32MBITS; + + case PSRAM_SIZE_64MBITS: + return ESP_SPIRAM_SIZE_64MBITS; + + default: + return ESP_SPIRAM_SIZE_INVALID; + } +} + +int esp_spiram_init(void) +{ + int ret; + ret = psram_enable(PSRAM_SPEED, PSRAM_MODE); + if (ret != OK) + { +#ifdef CONFIG_ESP32_SPIRAM_IGNORE_NOTFOUND + merr("SPI RAM enabled but initialization failed.\ + Bailing out."); +#endif + return ret; + } + + /* note: this needs to be set before esp_spiram_get_chip_* / + * esp_spiram_get_size calls. + */ + + spiram_inited = true; + +#if (CONFIG_ESP32_SPIRAM_SIZE != -1) + if (esp_spiram_get_size() != CONFIG_ESP32_SPIRAM_SIZE) + { + merr("Expected %dKiB chip but found %dKiB chip.\ + Bailing out..\n", CONFIG_ESP32_SPIRAM_SIZE / 1024, + esp_spiram_get_size() / 1024); + return -EINVAL; + } +#endif + + minfo("Found %dMBit SPI RAM device\n", + (esp_spiram_get_size() * 8) / (1024 * 1024)); + + minfo("SPI RAM mode: %s\n", + PSRAM_SPEED == PSRAM_CACHE_F40M_S40M ? "flash 40m sram 40m" : \ + PSRAM_SPEED == PSRAM_CACHE_F80M_S40M ? "flash 80m sram 40m" : \ + PSRAM_SPEED == PSRAM_CACHE_F80M_S80M ? "flash 80m sram 80m" : \ + "ERROR"); + + minfo("PSRAM initialized, cache is in %s mode.\n", \ + (PSRAM_MODE == PSRAM_VADDR_MODE_EVENODD) ? "even/odd (2-core)": \ + (PSRAM_MODE == PSRAM_VADDR_MODE_LOWHIGH) ? "low/high (2-core)": \ + (PSRAM_MODE == PSRAM_VADDR_MODE_NORMAL) ? "normal (1-core)":"ERROR"); + + return OK; +} + +#if 0 +/* DMA is not supported yet */ + +static uint8_t *dma_heap; + +int esp_spiram_reserve_dma_pool(size_t size) +{ + minfo("Reserving pool of %dK of internal memory for DMA/internal\ + allocations", size / 1024); + + /* Pool may be allocated in multiple non-contiguous chunks, depending on + * available RAM + */ + + while (size > 0) + { + size_t next_size = heap_caps_get_largest_free_block(MALLOC_CAP_DMA | + MALLOC_CAP_INTERNAL); + + next_size = MIN(next_size, size); + + minfo("Allocating block of size %d bytes", next_size); + + dma_heap = heap_caps_malloc(next_size, MALLOC_CAP_DMA | + MALLOC_CAP_INTERNAL); + + if (!dma_heap || next_size == 0) + { + return ESP_ERR_NO_MEM; + } + + uint32_t caps[] = + { + 0, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, + MALLOC_CAP_8BIT | MALLOC_CAP_32BIT + }; + + int e = heap_caps_add_region_with_caps(caps, (intptr_t) dma_heap, + (intptr_t) dma_heap + next_size - 1); + + if (e != ESP_OK) + { + return e; + } + + size -= next_size; + } + + return OK; +} +#endif + +size_t esp_spiram_get_size(void) +{ + psram_size_t size = esp_spiram_get_chip_size(); + + if (size == PSRAM_SIZE_16MBITS) + { + return 2 * 1024 * 1024; + } + + if (size == PSRAM_SIZE_32MBITS) + { + return 4 * 1024 * 1024; + } + + if (size == PSRAM_SIZE_64MBITS) + { + return 8 * 1024 * 1024; + } + + return CONFIG_ESP32_SPIRAM_SIZE; +} + +/* Before flushing the cache, if psram is enabled as a memory-mapped thing, + * we need to write back the data in the cache to the psram first, otherwise + * it will get lost. For now, we just read 64/128K of random PSRAM memory to + * do this. Note that this routine assumes some unique mapping for the first + * 2 banks of the PSRAM memory range, as well as the 2 banks after the 2 MiB + * mark. + */ + +void IRAM_ATTR esp_spiram_writeback_cache(void) +{ + int x; + uint32_t regval; + volatile int i = 0; + volatile uint8_t *psram = (volatile uint8_t *)SOC_EXTRAM_DATA_LOW; + int cache_was_disabled = 0; + + if (!spiram_inited) + { + return; + } + + /* We need cache enabled for this to work. Re-enable it if needed; make + * sure we disable it again on exit as well. + */ + + regval = getreg32(DPORT_PRO_CACHE_CTRL_REG); + + if ((regval & DPORT_PRO_CACHE_ENABLE) == 0) + { + cache_was_disabled |= (1 << 0); + regval = getreg32(DPORT_PRO_CACHE_CTRL_REG); + regval |= (1 << DPORT_PRO_CACHE_ENABLE_S); + putreg32(regval, DPORT_PRO_CACHE_CTRL_REG); + } + +#ifdef CONFIG_SMP + regval = getreg32(DPORT_APP_CACHE_CTRL_REG); + + if ((regval & DPORT_APP_CACHE_ENABLE) == 0) + { + cache_was_disabled |= (1 << 1); + regval = getreg32(DPORT_APP_CACHE_CTRL_REG); + regval |= 1 << DPORT_APP_CACHE_ENABLE_S; + putreg32(regval, DPORT_APP_CACHE_CTRL_REG); + } +#endif + +#if (PSRAM_MODE != PSRAM_VADDR_MODE_LOWHIGH) + /* Single-core and even/odd mode only have 32K of cache evenly distributed + * over the address lines. We can clear the cache by just reading 64K + * worth of cache lines. + */ + + for (x = 0; x < 1024 * 64; x += 32) + { + i += psram[x]; + } +#else + /* Low/high psram cache mode uses one 32K cache for the lowest 2MiB of SPI + * flash and another 32K for the highest 2MiB. Clear this by reading from + * both regions. Note: this assumes the amount of external RAM is >2M. + * If it is 2M or less, what this code does is undefined. If we ever + * support external RAM chips of 2M or smaller, this may need adjusting. + */ + + for (x = 0; x < 1024 * 64; x += 32) + { + i += psram[x]; + i += psram[x + (1024 * 1024 * 2)]; + } +#endif + + if (cache_was_disabled & (1 << 0)) + { + while (((getreg32(DPORT_PRO_DCACHE_DBUG0_REG) >> + (DPORT_PRO_CACHE_STATE_S)) & + (DPORT_PRO_CACHE_STATE)) != 1) + { + }; + + regval = getreg32(DPORT_PRO_CACHE_CTRL_REG); + regval &= ~(1 << DPORT_PRO_CACHE_ENABLE_S); + putreg32(regval, DPORT_PRO_CACHE_CTRL_REG); + } + +#ifdef CONFIG_SMP + if (cache_was_disabled & (1 << 1)) + { + while (((getreg32(DPORT_APP_DCACHE_DBUG0_REG) >> + (DPORT_APP_CACHE_STATE_S)) & + (DPORT_APP_CACHE_STATE)) != 1) + { + }; + + regval = getreg32(DPORT_APP_CACHE_CTRL_REG); + regval &= ~(1 << DPORT_APP_CACHE_ENABLE_S); + putreg32(regval, DPORT_APP_CACHE_CTRL_REG); + } +#endif +} + +/* If SPI RAM(PSRAM) has been initialized + * + * Return: + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void) +{ + return spiram_inited; +} + +#endif diff --git a/arch/xtensa/src/esp32/esp32_spiram.h b/arch/xtensa/src/esp32/esp32_spiram.h new file mode 100644 index 0000000000..924f1b63e3 --- /dev/null +++ b/arch/xtensa/src/esp32/esp32_spiram.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/esp32_spiram.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_SPIRAM_H +#define __ARCH_XTENSA_SRC_ESP32_ESP32_SPIRAM_H + +#include +#include +#include +#include "xtensa_attr.h" + +typedef enum +{ + ESP_SPIRAM_SIZE_16MBITS = 0, /* SPI RAM size is 16 MBits */ + ESP_SPIRAM_SIZE_32MBITS = 1, /* SPI RAM size is 32 MBits */ + ESP_SPIRAM_SIZE_64MBITS = 2, /* SPI RAM size is 64 MBits */ + ESP_SPIRAM_SIZE_INVALID, /* SPI RAM size is invalid */ +} esp_spiram_size_t; + +/* Description: get SPI RAM size + * return + * - ESP_SPIRAM_SIZE_INVALID if SPI RAM not enabled or not valid + * - SPI RAM size + */ + +esp_spiram_size_t esp_spiram_get_chip_size(void); + +/* Description: Initialize spiram interface/hardware. Normally called from + * cpu_start.c. + * + * return: + * OK on success + */ + +int esp_spiram_init(void); + +/* Description: Configure Cache/MMU for access to external SPI RAM. + * + * Normally this function is called from cpu_start, if + * CONFIG_ESP32_SPIRAM_BOOT_INIT option is enabled. Applications which need to + * enable SPI RAM at run time can disable CONFIG_ESP32_SPIRAM_BOOT_INIT, and + * call this function later. + * + * Attention this function must be called with flash cache disabled. + */ + +void esp_spiram_init_cache(void); + +/* Description: Memory test for SPI RAM. Should be called after SPI RAM is + * initialized and (in case of a dual-core system) the app CPU + * is online. This test overwrites the memory with crap, so do + * not call after e.g. the heap allocator has stored important + * stuff in SPI RAM. + * + * return: + * true on success, false on failed memory test + */ + +bool esp_spiram_test(void); + +/* Description Add the initialized SPI RAM to the heap allocator. */ + +int esp_spiram_add_to_heapalloc(void); + +/* Description: Get the size of the attached SPI RAM chip selected in + * menuconfig + * + * return: + * Size in bytes, or 0 if no external RAM chip support compiled in. + */ + +size_t esp_spiram_get_size(void); + +/* Description: Force a writeback of the data in the SPI RAM cache. This is + * to be called whenever cache is disabled, because disabling cache on the + * ESP32 discards the data in the SPI RAM cache. + * + * This is meant for use from within the SPI flash code. + */ + +void esp_spiram_writeback_cache(void); + +/* Description: Reserve a pool of internal memory for specific DMA/internal + * allocations. + * + * param: + * size Size of reserved pool in bytes + * + * return: + * - ESP_OK on success + * - ESP_ERR_NO_MEM when no memory available for pool + */ + +int esp_spiram_reserve_dma_pool(size_t size); + +/* Description: If SPI RAM(PSRAM) has been initialized + * + * return: + * - true SPI RAM has been initialized successfully + * - false SPI RAM hasn't been initialized or initialized failed + */ + +bool esp_spiram_is_initialized(void); + +/* Description: Set Ext-SRAM-Cache mmu mapping. + * + * Note that this code lives in IRAM and has a bugfix in respect to the + * ROM version of this function (which erroneously refused a vaddr > 2MiB + * + * param: + * int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu. + * int pod : process identifier. Range 0~7. + * unsigned int vaddr : virtual address in CPU address space. + * Can be IRam0, IRam1, IRom0 and DRom0 memory + * address. + * Should be aligned by psize. + * + * unsigned int paddr : physical address in Ext-SRAM. + * Should be aligned by psize. + * int psize : page size of flash, in kilobytes. Should be 32 here. + * int num : pages to be set. + * + * unsigned int: error status + * 0 : mmu set success + * 1 : vaddr or paddr is not aligned + * 2 : pid error + * 3 : psize error + * 4 : mmu table to be written is out of range + * 5 : vaddr is out of range + */ + +unsigned int IRAM_ATTR + cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, + unsigned int paddr, int psize, int num); + +#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_SPIRAM_H */ diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 36b5796251..026d3f90e4 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -43,6 +43,7 @@ #include "esp32_clockconfig.h" #include "esp32_region.h" #include "esp32_start.h" +#include "esp32_spiram.h" /**************************************************************************** * Public Data @@ -146,6 +147,18 @@ void IRAM_ATTR __start(void) xtensa_early_serial_initialize(); #endif +#if defined(CONFIG_ESP32_SPIRAM_BOOT_INIT) + esp_spiram_init_cache(); + if (esp_spiram_init() != OK) + { +# if defined(ESP32_SPIRAM_IGNORE_NOTFOUND) + mwarn("SPIRAM Initialization failed!\n"); +# else + PANIC(); +# endif + } +#endif + /* Initialize onboard resources */ esp32_board_initialize(); diff --git a/arch/xtensa/src/esp32/hardware/efuse_reg.h b/arch/xtensa/src/esp32/hardware/efuse_reg.h new file mode 100644 index 0000000000..89551cc6b8 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/efuse_reg.h @@ -0,0 +1,1821 @@ +/**************************************************************************** + * arch/xtensa/include/esp32/efuse_reg.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_INCLUDE_EFUSE_REG_H +#define __ARCH_XTENSA_INCLUDE_EFUSE_REG_H + +#define EFUSE_BLK0_RDATA0_REG (DR_REG_EFUSE_BASE + 0x000) + +/* EFUSE_RD_FLASH_CRYPT_CNT : RO ;bitpos:[26:20] ;default: 7'b0 ; + * Description: read for flash_crypt_cnt + */ + +#define EFUSE_RD_FLASH_CRYPT_CNT 0x0000007f +#define EFUSE_RD_FLASH_CRYPT_CNT_M ((EFUSE_RD_FLASH_CRYPT_CNT_V) << \ + (EFUSE_RD_FLASH_CRYPT_CNT_S)) +#define EFUSE_RD_FLASH_CRYPT_CNT_V 0x7f +#define EFUSE_RD_FLASH_CRYPT_CNT_S 20 + +/* EFUSE_RD_EFUSE_RD_DIS : RO ;bitpos:[19:16] ;default: 4'b0 ; + * Description: read for efuse_rd_disable + */ + +#define EFUSE_RD_EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_EFUSE_RD_DIS_M ((EFUSE_RD_EFUSE_RD_DIS_V) << \ + (EFUSE_RD_EFUSE_RD_DIS_S)) +#define EFUSE_RD_EFUSE_RD_DIS_V 0xf +#define EFUSE_RD_EFUSE_RD_DIS_S 16 + +/* Read disable bits for efuse blocks 1-3 */ + +#define EFUSE_RD_DIS_BLK1 (1 << 16) +#define EFUSE_RD_DIS_BLK2 (1 << 17) +#define EFUSE_RD_DIS_BLK3 (1 << 18) + +/* Read disable FLASH_CRYPT_CONFIG, CODING_SCHEME & KEY_STATUS + * in efuse block 0 + */ + +#define EFUSE_RD_DIS_BLK0_PARTIAL (1 << 19) + +/* EFUSE_RD_EFUSE_WR_DIS : RO ;bitpos:[15:0] ;default: 16'b0 ; + * Description: read for efuse_wr_disable + */ + +#define EFUSE_RD_EFUSE_WR_DIS 0x0000ffff +#define EFUSE_RD_EFUSE_WR_DIS_M ((EFUSE_RD_EFUSE_WR_DIS_V) << \ + (EFUSE_RD_EFUSE_WR_DIS_S)) +#define EFUSE_RD_EFUSE_WR_DIS_V 0xffff +#define EFUSE_RD_EFUSE_WR_DIS_S 0 + +/* Write disable bits */ + +#define EFUSE_WR_DIS_RD_DIS (1 << 0) /* disable writing read disable reg */ +#define EFUSE_WR_DIS_WR_DIS (1 << 1) /* disable writing write disable reg */ +#define EFUSE_WR_DIS_FLASH_CRYPT_CNT (1 << 2) +#define EFUSE_WR_DIS_MAC_SPI_CONFIG_HD (1 << 3) /* disable writing MAC & SPI config hd efuses */ +#define EFUSE_WR_DIS_XPD_SDIO (1 << 5) /* disable writing SDIO config efuses */ +#define EFUSE_WR_DIS_SPI_PAD_CONFIG (1 << 6) /* disable writing SPI_PAD_CONFIG efuses */ +#define EFUSE_WR_DIS_BLK1 (1 << 7) /* disable writing BLK1 efuses */ +#define EFUSE_WR_DIS_BLK2 (1 << 8) /* disable writing BLK2 efuses */ +#define EFUSE_WR_DIS_BLK3 (1 << 9) /* disable writing BLK3 efuses */ +#define EFUSE_WR_DIS_FL_CRYPT_COD_SCH (1 << 10) /* disable writing FLASH_CRYPT_CONFIG and CODING_SCHEME efuses */ +#define EFUSE_WR_DIS_ABS_DONE_0 (1 << 12) /* disable writing ABS_DONE_0 efuse */ +#define EFUSE_WR_DIS_ABS_DONE_1 (1 << 13) /* disable writing ABS_DONE_1 efuse */ +#define EFUSE_WR_DIS_JTAG_DISABLE (1 << 14) /* disable writing JTAG_DISABLE efuse */ +#define EFUSE_WR_DIS_CONSOLE_DL_DISABLE (1 << 15) /* disable writing CONSOLE_DEBUG_DISABLE, DISABLE_DL_ENCRYPT, DISABLE_DL_DECRYPT and DISABLE_DL_CACHE efuses */ + +#define EFUSE_BLK0_RDATA1_REG (DR_REG_EFUSE_BASE + 0x004) + +/* EFUSE_RD_WIFI_MAC_CRC_LOW : RO ;bitpos:[31:0] ;default: 32'b0 ; + * Description: read for low 32bit WIFI_MAC_Address + */ + +#define EFUSE_RD_WIFI_MAC_CRC_LOW 0xffffffff +#define EFUSE_RD_WIFI_MAC_CRC_LOW_M ((EFUSE_RD_WIFI_MAC_CRC_LOW_V) << \ + (EFUSE_RD_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_RD_WIFI_MAC_CRC_LOW_V 0xffffffff +#define EFUSE_RD_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_RDATA2_REG (DR_REG_EFUSE_BASE + 0x008) + +/* EFUSE_RD_WIFI_MAC_CRC_HIGH : RO ;bitpos:[23:0] ;default: 24'b0 ; + * Description: read for high 24bit WIFI_MAC_Address + */ + +#define EFUSE_RD_WIFI_MAC_CRC_HIGH 0x00ffffff +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_M ((EFUSE_RD_WIFI_MAC_CRC_HIGH_V) << \ + (EFUSE_RD_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_V 0xffffff +#define EFUSE_RD_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_RDATA3_REG (DR_REG_EFUSE_BASE + 0x00c) + +/* EFUSE_RD_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; + * Description: bit is set to 1 for rev1 silicon + */ + +#define EFUSE_RD_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_RD_CHIP_VER_REV1_M ((EFUSE_RD_CHIP_VER_REV1_V) << \ + (EFUSE_RD_CHIP_VER_REV1_S)) +#define EFUSE_RD_CHIP_VER_REV1_V 0x1 +#define EFUSE_RD_CHIP_VER_REV1_S 15 + +/* EFUSE_RD_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; + * Description: If set, this bit indicates that BLOCK3[143:96] is reserved + * for internal use + */ + +#define EFUSE_RD_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_RD_BLK3_PART_RESERVE_M ((EFUSE_RD_BLK3_PART_RESERVE_V) << \ + (EFUSE_RD_BLK3_PART_RESERVE_S)) +#define EFUSE_RD_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_RD_BLK3_PART_RESERVE_S 14 + +/* EFUSE_RD_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; + * Description: If set, the ESP32's maximum CPU frequency has been rated + */ + +#define EFUSE_RD_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_M ((EFUSE_RD_CHIP_CPU_FREQ_RATED_V) << \ + (EFUSE_RD_CHIP_CPU_FREQ_RATED_S)) +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_V 0x1 +#define EFUSE_RD_CHIP_CPU_FREQ_RATED_S 13 + +/* EFUSE_RD_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; + * Description: If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED, the ESP32's + * max CPU frequency is rated for 160MHz. 240MHz otherwise + */ + +#define EFUSE_RD_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_M ((EFUSE_RD_CHIP_CPU_FREQ_LOW_V) << \ + (EFUSE_RD_CHIP_CPU_FREQ_LOW_S)) +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_V 0x1 +#define EFUSE_RD_CHIP_CPU_FREQ_LOW_S 12 + +/* EFUSE_RD_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; + * Description: chip package + */ + +#define EFUSE_RD_CHIP_VER_PKG 0x00000007 +#define EFUSE_RD_CHIP_VER_PKG_M ((EFUSE_RD_CHIP_VER_PKG_V) << \ + (EFUSE_RD_CHIP_VER_PKG_S)) +#define EFUSE_RD_CHIP_VER_PKG_V 0x7 +#define EFUSE_RD_CHIP_VER_PKG_S 9 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2 4 +#define EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 5 + +/* EFUSE_RD_SPI_PAD_CONFIG_HD : RO ;bitpos:[8:4] ;default: 5'b0 ; + * Description: read for SPI_pad_config_hd + */ + +#define EFUSE_RD_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_M ((EFUSE_RD_SPI_PAD_CONFIG_HD_V) << \ + (EFUSE_RD_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_HD_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_HD_S 4 + +/* EFUSE_RD_CHIP_VER_DIS_CACHE : RO ;bitpos:[3] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_RD_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_RD_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_CACHE_S 3 + +/* EFUSE_RD_CHIP_VER_32PAD : RO ;bitpos:[2] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_RD_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_RD_CHIP_VER_32PAD_V 0x1 +#define EFUSE_RD_CHIP_VER_32PAD_S 2 + +/* EFUSE_RD_CHIP_VER_DIS_BT : RO ;bitpos:[1] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_RD_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_RD_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_BT_S 1 + +/* EFUSE_RD_CHIP_VER_DIS_APP_CPU : RO ;bitpos:[0] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_RD_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_RDATA4_REG (DR_REG_EFUSE_BASE + 0x010) + +/* EFUSE_RD_SDIO_FORCE : RO ;bitpos:[16] ;default: 1'b0 ; + * Description: read for sdio_force + */ + +#define EFUSE_RD_SDIO_FORCE (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_M (BIT(16)) +#define EFUSE_RD_SDIO_FORCE_V 0x1 +#define EFUSE_RD_SDIO_FORCE_S 16 + +/* EFUSE_RD_SDIO_TIEH : RO ;bitpos:[15] ;default: 1'b0 ; + * Description: read for SDIO_TIEH + */ + +#define EFUSE_RD_SDIO_TIEH (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_M (BIT(15)) +#define EFUSE_RD_SDIO_TIEH_V 0x1 +#define EFUSE_RD_SDIO_TIEH_S 15 + +/* EFUSE_RD_XPD_SDIO_REG : RO ;bitpos:[14] ;default: 1'b0 ; + * Description: read for XPD_SDIO_REG + */ + +#define EFUSE_RD_XPD_SDIO_REG (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_RD_XPD_SDIO_REG_V 0x1 +#define EFUSE_RD_XPD_SDIO_REG_S 14 + +/* EFUSE_RD_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; + * Description: True ADC reference voltage + */ + +#define EFUSE_RD_ADC_VREF 0x0000001f +#define EFUSE_RD_ADC_VREF_M ((EFUSE_RD_ADC_VREF_V) << \ + (EFUSE_RD_ADC_VREF_S)) +#define EFUSE_RD_ADC_VREF_V 0x1f +#define EFUSE_RD_ADC_VREF_S 8 + +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. + * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, + * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 + */ + +/* EFUSE_RD_SDIO_DREFL : RO ;bitpos:[13:12] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_RD_SDIO_DREFL 0x00000003 +#define EFUSE_RD_SDIO_DREFL_M ((EFUSE_RD_SDIO_DREFL_V) << \ + (EFUSE_RD_SDIO_DREFL_S)) +#define EFUSE_RD_SDIO_DREFL_V 0x3 +#define EFUSE_RD_SDIO_DREFL_S 12 + +/* EFUSE_RD_SDIO_DREFM : RO ;bitpos:[11:10] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_RD_SDIO_DREFM 0x00000003 +#define EFUSE_RD_SDIO_DREFM_M ((EFUSE_RD_SDIO_DREFM_V) << \ + (EFUSE_RD_SDIO_DREFM_S)) +#define EFUSE_RD_SDIO_DREFM_V 0x3 +#define EFUSE_RD_SDIO_DREFM_S 10 + +/* EFUSE_RD_SDIO_DREFH : RO ;bitpos:[9:8] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_RD_SDIO_DREFH 0x00000003 +#define EFUSE_RD_SDIO_DREFH_M ((EFUSE_RD_SDIO_DREFH_V) << \ + (EFUSE_RD_SDIO_DREFH_S)) +#define EFUSE_RD_SDIO_DREFH_V 0x3 +#define EFUSE_RD_SDIO_DREFH_S 8 + +/* EFUSE_RD_CK8M_FREQ : RO ;bitpos:[7:0] ;default: 8'b0 ; + * Description: + */ + +#define EFUSE_RD_CK8M_FREQ 0x000000ff +#define EFUSE_RD_CK8M_FREQ_M ((EFUSE_RD_CK8M_FREQ_V) << \ + (EFUSE_RD_CK8M_FREQ_S)) +#define EFUSE_RD_CK8M_FREQ_V 0xff +#define EFUSE_RD_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014) + +/* EFUSE_RD_FLASH_CRYPT_CONFIG : RO ;bitpos:[31:28] ;default: 4'b0 ; + * Description: read for flash_crypt_config + */ + +#define EFUSE_RD_FLASH_CRYPT_CONFIG 0x0000000f +#define EFUSE_RD_FLASH_CRYPT_CONFIG_M ((EFUSE_RD_FLASH_CRYPT_CONFIG_V) << \ + (EFUSE_RD_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_RD_FLASH_CRYPT_CONFIG_V 0xf +#define EFUSE_RD_FLASH_CRYPT_CONFIG_S 28 + +/* EFUSE_RD_DIG_VOL_L6: RO; bitpos:[27:24]; + * Descritpion: This field stores the difference between the digital + * regulator voltage at level6 and 1.2 V. (RO) + * BIT[27] is the sign bit, 0: + , 1: - + * BIT[26:24] is the difference value, unit: 0.017V + * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + + * BIT[26:24] * 0.017 + */ + +#define EFUSE_RD_DIG_VOL_L6 0x0f +#define EFUSE_RD_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ + (EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_RD_DIG_VOL_L6_V 0x0f +#define EFUSE_RD_DIG_VOL_L6_S 24 + +/* EFUSE_RD_VOL_LEVEL_HP_INV: RO; bitpos:[23:22] + * Description: This field stores the voltage level for CPU to run at 240 MHz + * or for flash/PSRAM to run at 80 MHz. + * 0x0: level 7; + * 0x1: level 6; + * 0x2: level 5; + * 0x3: level 4. (RO) + */ + +#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ + (EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_RD_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_RD_INST_CONFIG : RO ;bitpos:[27:20] ;default: 8'b0 ; + * Deprecated + */ + +#define EFUSE_RD_INST_CONFIG 0x000000ff /* Deprecated */ +#define EFUSE_RD_INST_CONFIG_M ((EFUSE_RD_INST_CONFIG_V) << \ + (EFUSE_RD_INST_CONFIG_S)) +#define EFUSE_RD_INST_CONFIG_V 0xff /* Deprecated */ +#define EFUSE_RD_INST_CONFIG_S 20 /* Deprecated */ + +/* EFUSE_RD_SPI_PAD_CONFIG_CS0 : RO ;bitpos:[19:15] ;default: 5'b0 ; + * Description: read for SPI_pad_config_cs0 + */ + +#define EFUSE_RD_SPI_PAD_CONFIG_CS0 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_M ((EFUSE_RD_SPI_PAD_CONFIG_CS0_V) << \ + (EFUSE_RD_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_CS0_S 15 + +/* EFUSE_RD_SPI_PAD_CONFIG_D : RO ;bitpos:[14:10] ;default: 5'b0 ; + * Description: read for SPI_pad_config_d + */ + +#define EFUSE_RD_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_D_M ((EFUSE_RD_SPI_PAD_CONFIG_D_V) << \ + (EFUSE_RD_SPI_PAD_CONFIG_D_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_D_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_D_S 10 + +/* EFUSE_RD_SPI_PAD_CONFIG_Q : RO ;bitpos:[9:5] ;default: 5'b0 ; + * Description: read for SPI_pad_config_q + */ + +#define EFUSE_RD_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_M ((EFUSE_RD_SPI_PAD_CONFIG_Q_V) << \ + (EFUSE_RD_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_Q_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_Q_S 5 + +/* EFUSE_RD_SPI_PAD_CONFIG_CLK : RO ;bitpos:[4:0] ;default: 5'b0 ; + * Description: read for SPI_pad_config_clk + */ + +#define EFUSE_RD_SPI_PAD_CONFIG_CLK 0x0000001f +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_M ((EFUSE_RD_SPI_PAD_CONFIG_CLK_V) << \ + (EFUSE_RD_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_V 0x1f +#define EFUSE_RD_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_RDATA6_REG (DR_REG_EFUSE_BASE + 0x018) + +/* EFUSE_RD_KEY_STATUS : RO ;bitpos:[10] ;default: 1'b0 ; + * Description: read for key_status + */ + +#define EFUSE_RD_KEY_STATUS (BIT(10)) +#define EFUSE_RD_KEY_STATUS_M (BIT(10)) +#define EFUSE_RD_KEY_STATUS_V 0x1 +#define EFUSE_RD_KEY_STATUS_S 10 + +/* EFUSE_RD_DISABLE_DL_CACHE : RO ;bitpos:[9] ;default: 1'b0 ; + * Description: read for download_dis_cache + */ + +#define EFUSE_RD_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_RD_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_RD_DISABLE_DL_CACHE_S 9 + +/* EFUSE_RD_DISABLE_DL_DECRYPT : RO ;bitpos:[8] ;default: 1'b0 ; + * Description: read for download_dis_decrypt + */ + +#define EFUSE_RD_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_RD_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_DECRYPT_S 8 + +/* EFUSE_RD_DISABLE_DL_ENCRYPT : RO ;bitpos:[7] ;default: 1'b0 ; + * Description: read for download_dis_encrypt + */ + +#define EFUSE_RD_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_RD_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_RD_DISABLE_DL_ENCRYPT_S 7 + +/* EFUSE_RD_DISABLE_JTAG : RO ;bitpos:[6] ;default: 1'b0 ; + * Description: read for JTAG_disable + */ + +#define EFUSE_RD_DISABLE_JTAG (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_RD_DISABLE_JTAG_V 0x1 +#define EFUSE_RD_DISABLE_JTAG_S 6 + +/* EFUSE_RD_ABS_DONE_1 : RO ;bitpos:[5] ;default: 1'b0 ; + * Description: read for abstract_done_1 + */ + +#define EFUSE_RD_ABS_DONE_1 (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_M (BIT(5)) +#define EFUSE_RD_ABS_DONE_1_V 0x1 +#define EFUSE_RD_ABS_DONE_1_S 5 + +/* EFUSE_RD_ABS_DONE_0 : RO ;bitpos:[4] ;default: 1'b0 ; + * Description: read for abstract_done_0 + */ + +#define EFUSE_RD_ABS_DONE_0 (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_M (BIT(4)) +#define EFUSE_RD_ABS_DONE_0_V 0x1 +#define EFUSE_RD_ABS_DONE_0_S 4 + +/* EFUSE_RD_DISABLE_SDIO_HOST : RO ;bitpos:[3] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_RD_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_RD_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_RD_DISABLE_SDIO_HOST_S 3 + +/* EFUSE_RD_CONSOLE_DEBUG_DISABLE : RO ;bitpos:[2] ;default: 1'b0 ; + * Description: read for console_debug_disable + */ + +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_RD_CONSOLE_DEBUG_DISABLE_S 2 + +/* EFUSE_RD_CODING_SCHEME : RO ;bitpos:[1:0] ;default: 2'b0 ; + * Description: read for coding_scheme + */ + +#define EFUSE_RD_CODING_SCHEME 0x00000003 +#define EFUSE_RD_CODING_SCHEME_M ((EFUSE_RD_CODING_SCHEME_V) << \ + (EFUSE_RD_CODING_SCHEME_S)) +#define EFUSE_RD_CODING_SCHEME_V 0x3 +#define EFUSE_RD_CODING_SCHEME_S 0 + +#define EFUSE_CODING_SCHEME_VAL_NONE 0x0 +#define EFUSE_CODING_SCHEME_VAL_34 0x1 +#define EFUSE_CODING_SCHEME_VAL_REPEAT 0x2 + +#define EFUSE_BLK0_WDATA0_REG (DR_REG_EFUSE_BASE + 0x01c) + +/* EFUSE_FLASH_CRYPT_CNT : R/W ;bitpos:[26:20] ;default: 7'b0 ; + * Description: program for flash_crypt_cnt + */ + +#define EFUSE_FLASH_CRYPT_CNT 0x0000007f +#define EFUSE_FLASH_CRYPT_CNT_M ((EFUSE_FLASH_CRYPT_CNT_V) << \ + (EFUSE_FLASH_CRYPT_CNT_S)) +#define EFUSE_FLASH_CRYPT_CNT_V 0x7f +#define EFUSE_FLASH_CRYPT_CNT_S 20 + +/* EFUSE_RD_DIS : R/W ;bitpos:[19:16] ;default: 4'b0 ; + * Description: program for efuse_rd_disable + */ + +#define EFUSE_RD_DIS 0x0000000f +#define EFUSE_RD_DIS_M ((EFUSE_RD_DIS_V) << \ + (EFUSE_RD_DIS_S)) +#define EFUSE_RD_DIS_V 0xf +#define EFUSE_RD_DIS_S 16 + +/* EFUSE_WR_DIS : R/W ;bitpos:[15:0] ;default: 16'b0 ; + * Description: program for efuse_wr_disable + */ + +#define EFUSE_WR_DIS 0x0000ffff +#define EFUSE_WR_DIS_M ((EFUSE_WR_DIS_V) << \ + (EFUSE_WR_DIS_S)) +#define EFUSE_WR_DIS_V 0xffff +#define EFUSE_WR_DIS_S 0 + +#define EFUSE_BLK0_WDATA1_REG (DR_REG_EFUSE_BASE + 0x020) + +/* EFUSE_WIFI_MAC_CRC_LOW : R/W ;bitpos:[31:0] ;default: 32'b0 ; + * Description: program for low 32bit WIFI_MAC_Address + */ + +#define EFUSE_WIFI_MAC_CRC_LOW 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_M ((EFUSE_WIFI_MAC_CRC_LOW_V) << \ + (EFUSE_WIFI_MAC_CRC_LOW_S)) +#define EFUSE_WIFI_MAC_CRC_LOW_V 0xffffffff +#define EFUSE_WIFI_MAC_CRC_LOW_S 0 + +#define EFUSE_BLK0_WDATA2_REG (DR_REG_EFUSE_BASE + 0x024) + +/* EFUSE_WIFI_MAC_CRC_HIGH : R/W ;bitpos:[23:0] ;default: 24'b0 ; + * Description: program for high 24bit WIFI_MAC_Address + */ + +#define EFUSE_WIFI_MAC_CRC_HIGH 0x00ffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_M ((EFUSE_WIFI_MAC_CRC_HIGH_V) << \ + (EFUSE_WIFI_MAC_CRC_HIGH_S)) +#define EFUSE_WIFI_MAC_CRC_HIGH_V 0xffffff +#define EFUSE_WIFI_MAC_CRC_HIGH_S 0 + +#define EFUSE_BLK0_WDATA3_REG (DR_REG_EFUSE_BASE + 0x028) + +/* EFUSE_CHIP_VER_REV1 : R/W ;bitpos:[15] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_REV1 (BIT(15)) +#define EFUSE_CHIP_VER_REV1_M ((EFUSE_CHIP_VER_REV1_V) << \ + (EFUSE_CHIP_VER_REV1_S)) +#define EFUSE_CHIP_VER_REV1_V 0x1 +#define EFUSE_CHIP_VER_REV1_S 15 + +/* EFUSE_BLK3_PART_RESERVE : R/W ; bitpos:[14] ; default: 1'b0; + * Description: If set, this bit indicates that BLOCK3[143:96] is reserved + * for internal use + */ + +#define EFUSE_BLK3_PART_RESERVE (BIT(14)) +#define EFUSE_BLK3_PART_RESERVE_M ((EFUSE_BLK3_PART_RESERVE_V) << \ + (EFUSE_BLK3_PART_RESERVE_S)) +#define EFUSE_BLK3_PART_RESERVE_V 0x1 +#define EFUSE_BLK3_PART_RESERVE_S 14 + +/* EFUSE_CHIP_CPU_FREQ_RATED : R/W ;bitpos:[13] ;default: 1'b0 ; + * Description: If set, the ESP32's maximum CPU frequency has been rated + */ + +#define EFUSE_CHIP_CPU_FREQ_RATED (BIT(13)) +#define EFUSE_CHIP_CPU_FREQ_RATED_M ((EFUSE_CHIP_CPU_FREQ_RATED_V) << \ + (EFUSE_CHIP_CPU_FREQ_RATED_S)) +#define EFUSE_CHIP_CPU_FREQ_RATED_V 0x1 +#define EFUSE_CHIP_CPU_FREQ_RATED_S 13 + +/* EFUSE_CHIP_CPU_FREQ_LOW : R/W ;bitpos:[12] ;default: 1'b0 ; + * Description: If set alongside EFUSE_CHIP_CPU_FREQ_RATED, the ESP32's max + * CPU frequency is rated for 160MHz. 240MHz otherwise + */ + +#define EFUSE_CHIP_CPU_FREQ_LOW (BIT(12)) +#define EFUSE_CHIP_CPU_FREQ_LOW_M ((EFUSE_CHIP_CPU_FREQ_LOW_V) << \ + (EFUSE_CHIP_CPU_FREQ_LOW_S)) +#define EFUSE_CHIP_CPU_FREQ_LOW_V 0x1 +#define EFUSE_CHIP_CPU_FREQ_LOW_S 12 + +/* EFUSE_CHIP_VER_PKG : R/W ;bitpos:[11:9] ;default: 3'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_PKG 0x00000007 +#define EFUSE_CHIP_VER_PKG_M ((EFUSE_CHIP_VER_PKG_V) << \ + (EFUSE_CHIP_VER_PKG_S)) +#define EFUSE_CHIP_VER_PKG_V 0x7 +#define EFUSE_CHIP_VER_PKG_S 9 +#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ6 0 +#define EFUSE_CHIP_VER_PKG_ESP32D0WDQ5 1 +#define EFUSE_CHIP_VER_PKG_ESP32D2WDQ5 2 +#define EFUSE_CHIP_VER_PKG_ESP32PICOD2 4 +#define EFUSE_CHIP_VER_PKG_ESP32PICOD4 5 + +/* EFUSE_SPI_PAD_CONFIG_HD : R/W ;bitpos:[8:4] ;default: 5'b0 ; + * Description: program for SPI_pad_config_hd + */ + +#define EFUSE_SPI_PAD_CONFIG_HD 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_HD_M ((EFUSE_SPI_PAD_CONFIG_HD_V) << \ + (EFUSE_SPI_PAD_CONFIG_HD_S)) +#define EFUSE_SPI_PAD_CONFIG_HD_V 0x1f +#define EFUSE_SPI_PAD_CONFIG_HD_S 4 + +/* EFUSE_CHIP_VER_DIS_CACHE : R/W ;bitpos:[3] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_DIS_CACHE (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_M (BIT(3)) +#define EFUSE_CHIP_VER_DIS_CACHE_V 0x1 +#define EFUSE_CHIP_VER_DIS_CACHE_S 3 + +/* EFUSE_CHIP_VER_32PAD : R/W ;bitpos:[2] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_32PAD (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_M (BIT(2)) +#define EFUSE_CHIP_VER_32PAD_V 0x1 +#define EFUSE_CHIP_VER_32PAD_S 2 + +/* EFUSE_CHIP_VER_DIS_BT : R/W ;bitpos:[1] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_DIS_BT (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_M (BIT(1)) +#define EFUSE_CHIP_VER_DIS_BT_V 0x1 +#define EFUSE_CHIP_VER_DIS_BT_S 1 + +/* EFUSE_CHIP_VER_DIS_APP_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CHIP_VER_DIS_APP_CPU (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_M (BIT(0)) +#define EFUSE_CHIP_VER_DIS_APP_CPU_V 0x1 +#define EFUSE_CHIP_VER_DIS_APP_CPU_S 0 + +#define EFUSE_BLK0_WDATA4_REG (DR_REG_EFUSE_BASE + 0x02c) + +/* EFUSE_SDIO_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; + * Description: program for sdio_force + */ + +#define EFUSE_SDIO_FORCE (BIT(16)) +#define EFUSE_SDIO_FORCE_M (BIT(16)) +#define EFUSE_SDIO_FORCE_V 0x1 +#define EFUSE_SDIO_FORCE_S 16 + +/* EFUSE_SDIO_TIEH : R/W ;bitpos:[15] ;default: 1'b0 ; + * Description: program for SDIO_TIEH + */ + +#define EFUSE_SDIO_TIEH (BIT(15)) +#define EFUSE_SDIO_TIEH_M (BIT(15)) +#define EFUSE_SDIO_TIEH_V 0x1 +#define EFUSE_SDIO_TIEH_S 15 + +/* EFUSE_XPD_SDIO_REG : R/W ;bitpos:[14] ;default: 1'b0 ; + * Description: program for XPD_SDIO_REG + */ + +#define EFUSE_XPD_SDIO_REG (BIT(14)) +#define EFUSE_XPD_SDIO_REG_M (BIT(14)) +#define EFUSE_XPD_SDIO_REG_V 0x1 +#define EFUSE_XPD_SDIO_REG_S 14 + +/* EFUSE_ADC_VREF : R/W ;bitpos:[12:8] ;default: 5'b0 ; + * Description: True ADC reference voltage + */ + +#define EFUSE_ADC_VREF 0x0000001f +#define EFUSE_ADC_VREF_M ((EFUSE_ADC_VREF_V) << \ + (EFUSE_ADC_VREF_S)) +#define EFUSE_ADC_VREF_V 0x1f +#define EFUSE_ADC_VREF_S 8 + +/* Note: EFUSE_ADC_VREF and SDIO_DREFH/M/L share the same address space. + * Newer versions of ESP32 come with EFUSE_ADC_VREF already burned, + * therefore SDIO_DREFH/M/L is only available in older versions of ESP32 + */ + +/* EFUSE_SDIO_DREFL : R/W ;bitpos:[13:12] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_SDIO_DREFL 0x00000003 +#define EFUSE_SDIO_DREFL_M ((EFUSE_SDIO_DREFL_V) << \ + (EFUSE_SDIO_DREFL_S)) +#define EFUSE_SDIO_DREFL_V 0x3 +#define EFUSE_SDIO_DREFL_S 12 + +/* EFUSE_SDIO_DREFM : R/W ;bitpos:[11:10] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_SDIO_DREFM 0x00000003 +#define EFUSE_SDIO_DREFM_M ((EFUSE_SDIO_DREFM_V) << \ + (EFUSE_SDIO_DREFM_S)) +#define EFUSE_SDIO_DREFM_V 0x3 +#define EFUSE_SDIO_DREFM_S 10 + +/* EFUSE_SDIO_DREFH : R/W ;bitpos:[9:8] ;default: 2'b0 ; + * Description: + */ + +#define EFUSE_SDIO_DREFH 0x00000003 +#define EFUSE_SDIO_DREFH_M ((EFUSE_SDIO_DREFH_V) << \ + (EFUSE_SDIO_DREFH_S)) +#define EFUSE_SDIO_DREFH_V 0x3 +#define EFUSE_SDIO_DREFH_S 8 + +/* EFUSE_CK8M_FREQ : R/W ;bitpos:[7:0] ;default: 8'b0 ; + * Description: + */ + +#define EFUSE_CK8M_FREQ 0x000000ff +#define EFUSE_CK8M_FREQ_M ((EFUSE_CK8M_FREQ_V) << \ + (EFUSE_CK8M_FREQ_S)) +#define EFUSE_CK8M_FREQ_V 0xff +#define EFUSE_CK8M_FREQ_S 0 + +#define EFUSE_BLK0_WDATA5_REG (DR_REG_EFUSE_BASE + 0x030) + +/* EFUSE_FLASH_CRYPT_CONFIG : R/W ;bitpos:[31:28] ;default: 4'b0 ; + * Description: program for flash_crypt_config + */ + +#define EFUSE_FLASH_CRYPT_CONFIG 0x0000000f +#define EFUSE_FLASH_CRYPT_CONFIG_M ((EFUSE_FLASH_CRYPT_CONFIG_V) << \ + (EFUSE_FLASH_CRYPT_CONFIG_S)) +#define EFUSE_FLASH_CRYPT_CONFIG_V 0xf +#define EFUSE_FLASH_CRYPT_CONFIG_S 28 + +/* EFUSE_DIG_VOL_L6: R/W; bitpos:[27:24]; + * Descritpion: This field stores the difference between the digital + * regulator voltage at level6 and 1.2 V. (R/W) + * BIT[27] is the sign bit, 0: + , 1: - + * BIT[26:24] is the difference value, unit: 0.017V + * volt_lv6 = BIT[27] ? 1.2 - BIT[26:24] * 0.017 : 1.2 + + * BIT[26:24] * 0.017 + */ + +#define EFUSE_DIG_VOL_L6 0x0f +#define EFUSE_DIG_VOL_L6_M ((EFUSE_RD_DIG_VOL_L6_V) << \ + (EFUSE_RD_DIG_VOL_L6_S)) +#define EFUSE_DIG_VOL_L6_V 0x0f +#define EFUSE_DIG_VOL_L6_S 24 + +/* EFUSE_VOL_LEVEL_HP_INV: R/W; bitpos:[23:22] + * Description: This field stores the voltage level for CPU to run at + * 240 MHz, or for flash/PSRAM to run at 80 MHz. + * 0x0: level 7; + * 0x1: level 6; + * 0x2: level 5; + * 0x3: level 4. (R/W) + */ + +#define EFUSE_VOL_LEVEL_HP_INV 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_M ((EFUSE_RD_VOL_LEVEL_HP_INV_V) << \ + (EFUSE_RD_VOL_LEVEL_HP_INV_S)) +#define EFUSE_VOL_LEVEL_HP_INV_V 0x03 +#define EFUSE_VOL_LEVEL_HP_INV_S 22 + +/* EFUSE_INST_CONFIG : R/W ;bitpos:[27:20] ;default: 8'b0 ; + * Deprecated + */ + +#define EFUSE_INST_CONFIG 0x000000ff /* Deprecated */ +#define EFUSE_INST_CONFIG_M ((EFUSE_INST_CONFIG_V) << \ + (EFUSE_INST_CONFIG_S)) /* Deprecated */ +#define EFUSE_INST_CONFIG_V 0xff /* Deprecated */ +#define EFUSE_INST_CONFIG_S 20 /* Deprecated */ + +/* EFUSE_SPI_PAD_CONFIG_CS0 : R/W ;bitpos:[19:15] ;default: 5'b0 ; + * Description: program for SPI_pad_config_cs0 + */ + +#define EFUSE_SPI_PAD_CONFIG_CS0 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CS0_M ((EFUSE_SPI_PAD_CONFIG_CS0_V) << \ + (EFUSE_SPI_PAD_CONFIG_CS0_S)) +#define EFUSE_SPI_PAD_CONFIG_CS0_V 0x1f +#define EFUSE_SPI_PAD_CONFIG_CS0_S 15 + +/* EFUSE_SPI_PAD_CONFIG_D : R/W ;bitpos:[14:10] ;default: 5'b0 ; + * Description: program for SPI_pad_config_d + */ + +#define EFUSE_SPI_PAD_CONFIG_D 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_D_M ((EFUSE_SPI_PAD_CONFIG_D_V) << \ + (EFUSE_SPI_PAD_CONFIG_D_S)) +#define EFUSE_SPI_PAD_CONFIG_D_V 0x1f +#define EFUSE_SPI_PAD_CONFIG_D_S 10 + +/* EFUSE_SPI_PAD_CONFIG_Q : R/W ;bitpos:[9:5] ;default: 5'b0 ; + * Description: program for SPI_pad_config_q + */ + +#define EFUSE_SPI_PAD_CONFIG_Q 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_Q_M ((EFUSE_SPI_PAD_CONFIG_Q_V) << \ + (EFUSE_SPI_PAD_CONFIG_Q_S)) +#define EFUSE_SPI_PAD_CONFIG_Q_V 0x1f +#define EFUSE_SPI_PAD_CONFIG_Q_S 5 + +/* EFUSE_SPI_PAD_CONFIG_CLK : R/W ;bitpos:[4:0] ;default: 5'b0 ; + * Description: program for SPI_pad_config_clk + */ + +#define EFUSE_SPI_PAD_CONFIG_CLK 0x0000001f +#define EFUSE_SPI_PAD_CONFIG_CLK_M ((EFUSE_SPI_PAD_CONFIG_CLK_V) << \ + (EFUSE_SPI_PAD_CONFIG_CLK_S)) +#define EFUSE_SPI_PAD_CONFIG_CLK_V 0x1f +#define EFUSE_SPI_PAD_CONFIG_CLK_S 0 + +#define EFUSE_BLK0_WDATA6_REG (DR_REG_EFUSE_BASE + 0x034) + +/* EFUSE_KEY_STATUS : R/W ;bitpos:[10] ;default: 1'b0 ; + * Description: program for key_status + */ + +#define EFUSE_KEY_STATUS (BIT(10)) +#define EFUSE_KEY_STATUS_M (BIT(10)) +#define EFUSE_KEY_STATUS_V 0x1 +#define EFUSE_KEY_STATUS_S 10 + +/* EFUSE_DISABLE_DL_CACHE : R/W ;bitpos:[9] ;default: 1'b0 ; + * Description: program for download_dis_cache + */ + +#define EFUSE_DISABLE_DL_CACHE (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_M (BIT(9)) +#define EFUSE_DISABLE_DL_CACHE_V 0x1 +#define EFUSE_DISABLE_DL_CACHE_S 9 + +/* EFUSE_DISABLE_DL_DECRYPT : R/W ;bitpos:[8] ;default: 1'b0 ; + * Description: program for download_dis_decrypt + */ + +#define EFUSE_DISABLE_DL_DECRYPT (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_M (BIT(8)) +#define EFUSE_DISABLE_DL_DECRYPT_V 0x1 +#define EFUSE_DISABLE_DL_DECRYPT_S 8 + +/* EFUSE_DISABLE_DL_ENCRYPT : R/W ;bitpos:[7] ;default: 1'b0 ; + * Description: program for download_dis_encrypt + */ + +#define EFUSE_DISABLE_DL_ENCRYPT (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_M (BIT(7)) +#define EFUSE_DISABLE_DL_ENCRYPT_V 0x1 +#define EFUSE_DISABLE_DL_ENCRYPT_S 7 + +/* EFUSE_DISABLE_JTAG : R/W ;bitpos:[6] ;default: 1'b0 ; + * Description: program for JTAG_disable + */ + +#define EFUSE_DISABLE_JTAG (BIT(6)) +#define EFUSE_DISABLE_JTAG_M (BIT(6)) +#define EFUSE_DISABLE_JTAG_V 0x1 +#define EFUSE_DISABLE_JTAG_S 6 + +/* EFUSE_ABS_DONE_1 : R/W ;bitpos:[5] ;default: 1'b0 ; + * Description: program for abstract_done_1 + */ + +#define EFUSE_ABS_DONE_1 (BIT(5)) +#define EFUSE_ABS_DONE_1_M (BIT(5)) +#define EFUSE_ABS_DONE_1_V 0x1 +#define EFUSE_ABS_DONE_1_S 5 + +/* EFUSE_ABS_DONE_0 : R/W ;bitpos:[4] ;default: 1'b0 ; + * Description: program for abstract_done_0 + */ + +#define EFUSE_ABS_DONE_0 (BIT(4)) +#define EFUSE_ABS_DONE_0_M (BIT(4)) +#define EFUSE_ABS_DONE_0_V 0x1 +#define EFUSE_ABS_DONE_0_S 4 + +/* EFUSE_DISABLE_SDIO_HOST : R/W ;bitpos:[3] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_DISABLE_SDIO_HOST (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_M (BIT(3)) +#define EFUSE_DISABLE_SDIO_HOST_V 0x1 +#define EFUSE_DISABLE_SDIO_HOST_S 3 + +/* EFUSE_CONSOLE_DEBUG_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; + * Description: program for console_debug_disable + */ + +#define EFUSE_CONSOLE_DEBUG_DISABLE (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_M (BIT(2)) +#define EFUSE_CONSOLE_DEBUG_DISABLE_V 0x1 +#define EFUSE_CONSOLE_DEBUG_DISABLE_S 2 + +/* EFUSE_CODING_SCHEME : R/W ;bitpos:[1:0] ;default: 2'b0 ; + * Description: program for coding_scheme + */ + +#define EFUSE_CODING_SCHEME 0x00000003 +#define EFUSE_CODING_SCHEME_M ((EFUSE_CODING_SCHEME_V) << \ + (EFUSE_CODING_SCHEME_S)) +#define EFUSE_CODING_SCHEME_V 0x3 +#define EFUSE_CODING_SCHEME_S 0 + +#define EFUSE_BLK1_RDATA0_REG (DR_REG_EFUSE_BASE + 0x038) + +/* EFUSE_BLK1_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT0 0xffffffff +#define EFUSE_BLK1_DOUT0_M ((EFUSE_BLK1_DOUT0_V) << \ + (EFUSE_BLK1_DOUT0_S)) +#define EFUSE_BLK1_DOUT0_V 0xffffffff +#define EFUSE_BLK1_DOUT0_S 0 + +#define EFUSE_BLK1_RDATA1_REG (DR_REG_EFUSE_BASE + 0x03c) + +/* EFUSE_BLK1_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT1 0xffffffff +#define EFUSE_BLK1_DOUT1_M ((EFUSE_BLK1_DOUT1_V) << \ + (EFUSE_BLK1_DOUT1_S)) +#define EFUSE_BLK1_DOUT1_V 0xffffffff +#define EFUSE_BLK1_DOUT1_S 0 + +#define EFUSE_BLK1_RDATA2_REG (DR_REG_EFUSE_BASE + 0x040) + +/* EFUSE_BLK1_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT2 0xffffffff +#define EFUSE_BLK1_DOUT2_M ((EFUSE_BLK1_DOUT2_V) << \ + (EFUSE_BLK1_DOUT2_S)) +#define EFUSE_BLK1_DOUT2_V 0xffffffff +#define EFUSE_BLK1_DOUT2_S 0 + +#define EFUSE_BLK1_RDATA3_REG (DR_REG_EFUSE_BASE + 0x044) + +/* EFUSE_BLK1_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT3 0xffffffff +#define EFUSE_BLK1_DOUT3_M ((EFUSE_BLK1_DOUT3_V) << \ + (EFUSE_BLK1_DOUT3_S)) +#define EFUSE_BLK1_DOUT3_V 0xffffffff +#define EFUSE_BLK1_DOUT3_S 0 + +#define EFUSE_BLK1_RDATA4_REG (DR_REG_EFUSE_BASE + 0x048) + +/* EFUSE_BLK1_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT4 0xffffffff +#define EFUSE_BLK1_DOUT4_M ((EFUSE_BLK1_DOUT4_V) << \ + (EFUSE_BLK1_DOUT4_S)) +#define EFUSE_BLK1_DOUT4_V 0xffffffff +#define EFUSE_BLK1_DOUT4_S 0 + +#define EFUSE_BLK1_RDATA5_REG (DR_REG_EFUSE_BASE + 0x04c) + +/* EFUSE_BLK1_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT5 0xffffffff +#define EFUSE_BLK1_DOUT5_M ((EFUSE_BLK1_DOUT5_V) << \ + (EFUSE_BLK1_DOUT5_S)) +#define EFUSE_BLK1_DOUT5_V 0xffffffff +#define EFUSE_BLK1_DOUT5_S 0 + +#define EFUSE_BLK1_RDATA6_REG (DR_REG_EFUSE_BASE + 0x050) + +/* EFUSE_BLK1_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT6 0xffffffff +#define EFUSE_BLK1_DOUT6_M ((EFUSE_BLK1_DOUT6_V) << \ + (EFUSE_BLK1_DOUT6_S)) +#define EFUSE_BLK1_DOUT6_V 0xffffffff +#define EFUSE_BLK1_DOUT6_S 0 + +#define EFUSE_BLK1_RDATA7_REG (DR_REG_EFUSE_BASE + 0x054) + +/* EFUSE_BLK1_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK1 + */ + +#define EFUSE_BLK1_DOUT7 0xffffffff +#define EFUSE_BLK1_DOUT7_M ((EFUSE_BLK1_DOUT7_V) << \ + (EFUSE_BLK1_DOUT7_S)) +#define EFUSE_BLK1_DOUT7_V 0xffffffff +#define EFUSE_BLK1_DOUT7_S 0 + +#define EFUSE_BLK2_RDATA0_REG (DR_REG_EFUSE_BASE + 0x058) + +/* EFUSE_BLK2_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT0 0xffffffff +#define EFUSE_BLK2_DOUT0_M ((EFUSE_BLK2_DOUT0_V) << \ + (EFUSE_BLK2_DOUT0_S)) +#define EFUSE_BLK2_DOUT0_V 0xffffffff +#define EFUSE_BLK2_DOUT0_S 0 + +#define EFUSE_BLK2_RDATA1_REG (DR_REG_EFUSE_BASE + 0x05c) + +/* EFUSE_BLK2_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT1 0xffffffff +#define EFUSE_BLK2_DOUT1_M ((EFUSE_BLK2_DOUT1_V) << \ + (EFUSE_BLK2_DOUT1_S)) +#define EFUSE_BLK2_DOUT1_V 0xffffffff +#define EFUSE_BLK2_DOUT1_S 0 + +#define EFUSE_BLK2_RDATA2_REG (DR_REG_EFUSE_BASE + 0x060) + +/* EFUSE_BLK2_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT2 0xffffffff +#define EFUSE_BLK2_DOUT2_M ((EFUSE_BLK2_DOUT2_V) << \ + (EFUSE_BLK2_DOUT2_S)) +#define EFUSE_BLK2_DOUT2_V 0xffffffff +#define EFUSE_BLK2_DOUT2_S 0 + +#define EFUSE_BLK2_RDATA3_REG (DR_REG_EFUSE_BASE + 0x064) + +/* EFUSE_BLK2_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT3 0xffffffff +#define EFUSE_BLK2_DOUT3_M ((EFUSE_BLK2_DOUT3_V) << \ + (EFUSE_BLK2_DOUT3_S)) +#define EFUSE_BLK2_DOUT3_V 0xffffffff +#define EFUSE_BLK2_DOUT3_S 0 + +#define EFUSE_BLK2_RDATA4_REG (DR_REG_EFUSE_BASE + 0x068) + +/* EFUSE_BLK2_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT4 0xffffffff +#define EFUSE_BLK2_DOUT4_M ((EFUSE_BLK2_DOUT4_V) << \ + (EFUSE_BLK2_DOUT4_S)) +#define EFUSE_BLK2_DOUT4_V 0xffffffff +#define EFUSE_BLK2_DOUT4_S 0 + +#define EFUSE_BLK2_RDATA5_REG (DR_REG_EFUSE_BASE + 0x06c) + +/* EFUSE_BLK2_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT5 0xffffffff +#define EFUSE_BLK2_DOUT5_M ((EFUSE_BLK2_DOUT5_V) << \ + (EFUSE_BLK2_DOUT5_S)) +#define EFUSE_BLK2_DOUT5_V 0xffffffff +#define EFUSE_BLK2_DOUT5_S 0 + +#define EFUSE_BLK2_RDATA6_REG (DR_REG_EFUSE_BASE + 0x070) + +/* EFUSE_BLK2_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT6 0xffffffff +#define EFUSE_BLK2_DOUT6_M ((EFUSE_BLK2_DOUT6_V) << \ + (EFUSE_BLK2_DOUT6_S)) +#define EFUSE_BLK2_DOUT6_V 0xffffffff +#define EFUSE_BLK2_DOUT6_S 0 + +#define EFUSE_BLK2_RDATA7_REG (DR_REG_EFUSE_BASE + 0x074) + +/* EFUSE_BLK2_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK2 + */ + +#define EFUSE_BLK2_DOUT7 0xffffffff +#define EFUSE_BLK2_DOUT7_M ((EFUSE_BLK2_DOUT7_V) << \ + (EFUSE_BLK2_DOUT7_S)) +#define EFUSE_BLK2_DOUT7_V 0xffffffff +#define EFUSE_BLK2_DOUT7_S 0 + +#define EFUSE_BLK3_RDATA0_REG (DR_REG_EFUSE_BASE + 0x078) + +/* EFUSE_BLK3_DOUT0 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT0 0xffffffff +#define EFUSE_BLK3_DOUT0_M ((EFUSE_BLK3_DOUT0_V) << \ + (EFUSE_BLK3_DOUT0_S)) +#define EFUSE_BLK3_DOUT0_V 0xffffffff +#define EFUSE_BLK3_DOUT0_S 0 + +#define EFUSE_BLK3_RDATA1_REG (DR_REG_EFUSE_BASE + 0x07c) + +/* EFUSE_BLK3_DOUT1 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT1 0xffffffff +#define EFUSE_BLK3_DOUT1_M ((EFUSE_BLK3_DOUT1_V) << \ + (EFUSE_BLK3_DOUT1_S)) +#define EFUSE_BLK3_DOUT1_V 0xffffffff +#define EFUSE_BLK3_DOUT1_S 0 + +#define EFUSE_BLK3_RDATA2_REG (DR_REG_EFUSE_BASE + 0x080) + +/* EFUSE_BLK3_DOUT2 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT2 0xffffffff +#define EFUSE_BLK3_DOUT2_M ((EFUSE_BLK3_DOUT2_V) << \ + (EFUSE_BLK3_DOUT2_S)) +#define EFUSE_BLK3_DOUT2_V 0xffffffff +#define EFUSE_BLK3_DOUT2_S 0 + +/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for + * calibration purposes. This usage is indicated by the + * EFUSE_RD_BLK3_PART_RESERVE bit. + */ + +#define EFUSE_BLK3_RDATA3_REG (DR_REG_EFUSE_BASE + 0x084) + +/* EFUSE_BLK3_DOUT3 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT3 0xffffffff +#define EFUSE_BLK3_DOUT3_M ((EFUSE_BLK3_DOUT3_V) << \ + (EFUSE_BLK3_DOUT3_S)) +#define EFUSE_BLK3_DOUT3_V 0xffffffff +#define EFUSE_BLK3_DOUT3_S 0 + +/* EFUSE_RD_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; + * Description: ADC2 Two Point calibration high point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_RD_ADC2_TP_HIGH 0x1ff +#define EFUSE_RD_ADC2_TP_HIGH_M ((EFUSE_RD_ADC2_TP_HIGH_V) << \ + (EFUSE_RD_ADC2_TP_HIGH_S)) +#define EFUSE_RD_ADC2_TP_HIGH_V 0x1ff +#define EFUSE_RD_ADC2_TP_HIGH_S 23 + +/* EFUSE_RD_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; + * Description: ADC2 Two Point calibration low point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_RD_ADC2_TP_LOW 0x7f +#define EFUSE_RD_ADC2_TP_LOW_M ((EFUSE_RD_ADC2_TP_LOW_V) << \ + (EFUSE_RD_ADC2_TP_LOW_S)) +#define EFUSE_RD_ADC2_TP_LOW_V 0x7f +#define EFUSE_RD_ADC2_TP_LOW_S 16 + +/* EFUSE_RD_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; + * Description: ADC1 Two Point calibration high point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_RD_ADC1_TP_HIGH 0x1ff +#define EFUSE_RD_ADC1_TP_HIGH_M ((EFUSE_RD_ADC1_TP_HIGH_V) << \ + (EFUSE_RD_ADC1_TP_HIGH_S)) +#define EFUSE_RD_ADC1_TP_HIGH_V 0x1ff +#define EFUSE_RD_ADC1_TP_HIGH_S 7 + +/* EFUSE_RD_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; + * Description: ADC1 Two Point calibration low point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_RD_ADC1_TP_LOW 0x7f +#define EFUSE_RD_ADC1_TP_LOW_M ((EFUSE_RD_ADC1_TP_LOW_V) << \ + (EFUSE_RD_ADC1_TP_LOW_S)) +#define EFUSE_RD_ADC1_TP_LOW_V 0x7f +#define EFUSE_RD_ADC1_TP_LOW_S 0 + +#define EFUSE_BLK3_RDATA4_REG (DR_REG_EFUSE_BASE + 0x088) + +/* EFUSE_BLK3_DOUT4 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT4 0xffffffff +#define EFUSE_BLK3_DOUT4_M ((EFUSE_BLK3_DOUT4_V) << \ + (EFUSE_BLK3_DOUT4_S)) +#define EFUSE_BLK3_DOUT4_V 0xffffffff +#define EFUSE_BLK3_DOUT4_S 0 + +/* EFUSE_RD_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; + * Description: Reserved for future calibration use. Indicated by + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_RD_CAL_RESERVED 0x0000ffff +#define EFUSE_RD_CAL_RESERVED_M ((EFUSE_RD_CAL_RESERVED_V) << \ + (EFUSE_RD_CAL_RESERVED_S)) +#define EFUSE_RD_CAL_RESERVED_V 0xffff +#define EFUSE_RD_CAL_RESERVED_S 0 + +#define EFUSE_BLK3_RDATA5_REG (DR_REG_EFUSE_BASE + 0x08c) + +/* EFUSE_BLK3_DOUT5 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT5 0xffffffff +#define EFUSE_BLK3_DOUT5_M ((EFUSE_BLK3_DOUT5_V) << \ + (EFUSE_BLK3_DOUT5_S)) +#define EFUSE_BLK3_DOUT5_V 0xffffffff +#define EFUSE_BLK3_DOUT5_S 0 + +#define EFUSE_BLK3_RDATA6_REG (DR_REG_EFUSE_BASE + 0x090) + +/* EFUSE_BLK3_DOUT6 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT6 0xffffffff +#define EFUSE_BLK3_DOUT6_M ((EFUSE_BLK3_DOUT6_V) << (EFUSE_BLK3_DOUT6_S)) +#define EFUSE_BLK3_DOUT6_V 0xffffffff +#define EFUSE_BLK3_DOUT6_S 0 + +#define EFUSE_BLK3_RDATA7_REG (DR_REG_EFUSE_BASE + 0x094) + +/* EFUSE_BLK3_DOUT7 : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: read for BLOCK3 + */ + +#define EFUSE_BLK3_DOUT7 0xffffffff +#define EFUSE_BLK3_DOUT7_M ((EFUSE_BLK3_DOUT7_V) << \ + (EFUSE_BLK3_DOUT7_S)) +#define EFUSE_BLK3_DOUT7_V 0xffffffff +#define EFUSE_BLK3_DOUT7_S 0 + +#define EFUSE_BLK1_WDATA0_REG (DR_REG_EFUSE_BASE + 0x098) + +/* EFUSE_BLK1_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN0 0xffffffff +#define EFUSE_BLK1_DIN0_M ((EFUSE_BLK1_DIN0_V) << \ + (EFUSE_BLK1_DIN0_S)) +#define EFUSE_BLK1_DIN0_V 0xffffffff +#define EFUSE_BLK1_DIN0_S 0 + +#define EFUSE_BLK1_WDATA1_REG (DR_REG_EFUSE_BASE + 0x09c) + +/* EFUSE_BLK1_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN1 0xffffffff +#define EFUSE_BLK1_DIN1_M ((EFUSE_BLK1_DIN1_V) << \ + (EFUSE_BLK1_DIN1_S)) +#define EFUSE_BLK1_DIN1_V 0xffffffff +#define EFUSE_BLK1_DIN1_S 0 + +#define EFUSE_BLK1_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0a0) + +/* EFUSE_BLK1_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN2 0xffffffff +#define EFUSE_BLK1_DIN2_M ((EFUSE_BLK1_DIN2_V) << \ + (EFUSE_BLK1_DIN2_S)) +#define EFUSE_BLK1_DIN2_V 0xffffffff +#define EFUSE_BLK1_DIN2_S 0 + +#define EFUSE_BLK1_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0a4) + +/* EFUSE_BLK1_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN3 0xffffffff +#define EFUSE_BLK1_DIN3_M ((EFUSE_BLK1_DIN3_V) << \ + (EFUSE_BLK1_DIN3_S)) +#define EFUSE_BLK1_DIN3_V 0xffffffff +#define EFUSE_BLK1_DIN3_S 0 + +#define EFUSE_BLK1_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0a8) + +/* EFUSE_BLK1_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN4 0xffffffff +#define EFUSE_BLK1_DIN4_M ((EFUSE_BLK1_DIN4_V) << \ + (EFUSE_BLK1_DIN4_S)) +#define EFUSE_BLK1_DIN4_V 0xffffffff +#define EFUSE_BLK1_DIN4_S 0 + +#define EFUSE_BLK1_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ac) + +/* EFUSE_BLK1_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN5 0xffffffff +#define EFUSE_BLK1_DIN5_M ((EFUSE_BLK1_DIN5_V) << \ + (EFUSE_BLK1_DIN5_S)) +#define EFUSE_BLK1_DIN5_V 0xffffffff +#define EFUSE_BLK1_DIN5_S 0 + +#define EFUSE_BLK1_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0b0) + +/* EFUSE_BLK1_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN6 0xffffffff +#define EFUSE_BLK1_DIN6_M ((EFUSE_BLK1_DIN6_V) << \ + (EFUSE_BLK1_DIN6_S)) +#define EFUSE_BLK1_DIN6_V 0xffffffff +#define EFUSE_BLK1_DIN6_S 0 + +#define EFUSE_BLK1_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0b4) + +/* EFUSE_BLK1_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK1 + */ + +#define EFUSE_BLK1_DIN7 0xffffffff +#define EFUSE_BLK1_DIN7_M ((EFUSE_BLK1_DIN7_V) << \ + (EFUSE_BLK1_DIN7_S)) +#define EFUSE_BLK1_DIN7_V 0xffffffff +#define EFUSE_BLK1_DIN7_S 0 + +#define EFUSE_BLK2_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0b8) + +/* EFUSE_BLK2_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN0 0xffffffff +#define EFUSE_BLK2_DIN0_M ((EFUSE_BLK2_DIN0_V) << \ + (EFUSE_BLK2_DIN0_S)) +#define EFUSE_BLK2_DIN0_V 0xffffffff +#define EFUSE_BLK2_DIN0_S 0 + +#define EFUSE_BLK2_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0bc) + +/* EFUSE_BLK2_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN1 0xffffffff +#define EFUSE_BLK2_DIN1_M ((EFUSE_BLK2_DIN1_V) << \ + (EFUSE_BLK2_DIN1_S)) +#define EFUSE_BLK2_DIN1_V 0xffffffff +#define EFUSE_BLK2_DIN1_S 0 + +#define EFUSE_BLK2_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0c0) + +/* EFUSE_BLK2_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN2 0xffffffff +#define EFUSE_BLK2_DIN2_M ((EFUSE_BLK2_DIN2_V) << \ + (EFUSE_BLK2_DIN2_S)) +#define EFUSE_BLK2_DIN2_V 0xffffffff +#define EFUSE_BLK2_DIN2_S 0 + +#define EFUSE_BLK2_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0c4) + +/* EFUSE_BLK2_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN3 0xffffffff +#define EFUSE_BLK2_DIN3_M ((EFUSE_BLK2_DIN3_V) << \ + (EFUSE_BLK2_DIN3_S)) +#define EFUSE_BLK2_DIN3_V 0xffffffff +#define EFUSE_BLK2_DIN3_S 0 + +#define EFUSE_BLK2_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0c8) + +/* EFUSE_BLK2_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN4 0xffffffff +#define EFUSE_BLK2_DIN4_M ((EFUSE_BLK2_DIN4_V) << \ + (EFUSE_BLK2_DIN4_S)) +#define EFUSE_BLK2_DIN4_V 0xffffffff +#define EFUSE_BLK2_DIN4_S 0 + +#define EFUSE_BLK2_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0cc) + +/* EFUSE_BLK2_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN5 0xffffffff +#define EFUSE_BLK2_DIN5_M ((EFUSE_BLK2_DIN5_V) << \ + (EFUSE_BLK2_DIN5_S)) +#define EFUSE_BLK2_DIN5_V 0xffffffff +#define EFUSE_BLK2_DIN5_S 0 + +#define EFUSE_BLK2_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0d0) + +/* EFUSE_BLK2_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN6 0xffffffff +#define EFUSE_BLK2_DIN6_M ((EFUSE_BLK2_DIN6_V) << \ + (EFUSE_BLK2_DIN6_S)) +#define EFUSE_BLK2_DIN6_V 0xffffffff +#define EFUSE_BLK2_DIN6_S 0 + +#define EFUSE_BLK2_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0d4) + +/* EFUSE_BLK2_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK2 + */ + +#define EFUSE_BLK2_DIN7 0xffffffff +#define EFUSE_BLK2_DIN7_M ((EFUSE_BLK2_DIN7_V) << \ + (EFUSE_BLK2_DIN7_S)) +#define EFUSE_BLK2_DIN7_V 0xffffffff +#define EFUSE_BLK2_DIN7_S 0 + +#define EFUSE_BLK3_WDATA0_REG (DR_REG_EFUSE_BASE + 0x0d8) + +/* EFUSE_BLK3_DIN0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN0 0xffffffff +#define EFUSE_BLK3_DIN0_M ((EFUSE_BLK3_DIN0_V) << \ + (EFUSE_BLK3_DIN0_S)) +#define EFUSE_BLK3_DIN0_V 0xffffffff +#define EFUSE_BLK3_DIN0_S 0 + +#define EFUSE_BLK3_WDATA1_REG (DR_REG_EFUSE_BASE + 0x0dc) + +/* EFUSE_BLK3_DIN1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN1 0xffffffff +#define EFUSE_BLK3_DIN1_M ((EFUSE_BLK3_DIN1_V) << \ + (EFUSE_BLK3_DIN1_S)) +#define EFUSE_BLK3_DIN1_V 0xffffffff +#define EFUSE_BLK3_DIN1_S 0 + +#define EFUSE_BLK3_WDATA2_REG (DR_REG_EFUSE_BASE + 0x0e0) + +/* EFUSE_BLK3_DIN2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN2 0xffffffff +#define EFUSE_BLK3_DIN2_M ((EFUSE_BLK3_DIN2_V) << \ + (EFUSE_BLK3_DIN2_S)) +#define EFUSE_BLK3_DIN2_V 0xffffffff +#define EFUSE_BLK3_DIN2_S 0 + +/* Note: Newer ESP32s utilize BLK3_DATA3 and parts of BLK3_DATA4 for + * calibration purposes. This usage is indicated by the + * EFUSE_RD_BLK3_PART_RESERVE bit. + */ + +#define EFUSE_BLK3_WDATA3_REG (DR_REG_EFUSE_BASE + 0x0e4) + +/* EFUSE_BLK3_DIN3 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN3 0xffffffff +#define EFUSE_BLK3_DIN3_M ((EFUSE_BLK3_DIN3_V) << \ + (EFUSE_BLK3_DIN3_S)) +#define EFUSE_BLK3_DIN3_V 0xffffffff +#define EFUSE_BLK3_DIN3_S 0 + +/* EFUSE_ADC2_TP_HIGH : R/W ;bitpos:[31:23] ;default: 9'b0 ; + * Description: ADC2 Two Point calibration high point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_ADC2_TP_HIGH 0x1ff +#define EFUSE_ADC2_TP_HIGH_M ((EFUSE_ADC2_TP_HIGH_V) << \ + (EFUSE_ADC2_TP_HIGH_S)) +#define EFUSE_ADC2_TP_HIGH_V 0x1ff +#define EFUSE_ADC2_TP_HIGH_S 23 + +/* EFUSE_ADC2_TP_LOW : R/W ;bitpos:[22:16] ;default: 7'b0 ; + * Description: ADC2 Two Point calibration low point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_ADC2_TP_LOW 0x7f +#define EFUSE_ADC2_TP_LOW_M ((EFUSE_ADC2_TP_LOW_V) << \ + (EFUSE_ADC2_TP_LOW_S)) +#define EFUSE_ADC2_TP_LOW_V 0x7f +#define EFUSE_ADC2_TP_LOW_S 16 + +/* EFUSE_ADC1_TP_HIGH : R/W ;bitpos:[15:7] ;default: 9'b0 ; + * Description: ADC1 Two Point calibration high point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_ADC1_TP_HIGH 0x1ff +#define EFUSE_ADC1_TP_HIGH_M ((EFUSE_ADC1_TP_HIGH_V) << \ + (EFUSE_ADC1_TP_HIGH_S)) +#define EFUSE_ADC1_TP_HIGH_V 0x1ff +#define EFUSE_ADC1_TP_HIGH_S 7 + +/* EFUSE_ADC1_TP_LOW : R/W ;bitpos:[6:0] ;default: 7'b0 ; + * Description: ADC1 Two Point calibration low point. Only valid if + * EFUSE_RD_BLK3_PART_RESERVE + */ + +#define EFUSE_ADC1_TP_LOW 0x7f +#define EFUSE_ADC1_TP_LOW_M ((EFUSE_ADC1_TP_LOW_V) << \ + (EFUSE_ADC1_TP_LOW_S)) +#define EFUSE_ADC1_TP_LOW_V 0x7f +#define EFUSE_ADC1_TP_LOW_S 0 + +#define EFUSE_BLK3_WDATA4_REG (DR_REG_EFUSE_BASE + 0x0e8) + +/* EFUSE_BLK3_DIN4 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN4 0xffffffff +#define EFUSE_BLK3_DIN4_M ((EFUSE_BLK3_DIN4_V) << \ + (EFUSE_BLK3_DIN4_S)) +#define EFUSE_BLK3_DIN4_V 0xffffffff +#define EFUSE_BLK3_DIN4_S 0 + +/* EFUSE_CAL_RESERVED: R/W ; bitpos:[0:15] ; default : 16'h0 ; + * Description: Reserved for future calibration use. Indicated by + * EFUSE_BLK3_PART_RESERVE + */ + +#define EFUSE_CAL_RESERVED 0x0000ffff +#define EFUSE_CAL_RESERVED_M ((EFUSE_CAL_RESERVED_V) << \ + (EFUSE_CAL_RESERVED_S)) +#define EFUSE_CAL_RESERVED_V 0xffff +#define EFUSE_CAL_RESERVED_S 0 + +#define EFUSE_BLK3_WDATA5_REG (DR_REG_EFUSE_BASE + 0x0ec) + +/* EFUSE_BLK3_DIN5 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN5 0xffffffff +#define EFUSE_BLK3_DIN5_M ((EFUSE_BLK3_DIN5_V) << \ + (EFUSE_BLK3_DIN5_S)) +#define EFUSE_BLK3_DIN5_V 0xffffffff +#define EFUSE_BLK3_DIN5_S 0 + +#define EFUSE_BLK3_WDATA6_REG (DR_REG_EFUSE_BASE + 0x0f0) + +/* EFUSE_BLK3_DIN6 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN6 0xffffffff +#define EFUSE_BLK3_DIN6_M ((EFUSE_BLK3_DIN6_V) << \ + (EFUSE_BLK3_DIN6_S)) +#define EFUSE_BLK3_DIN6_V 0xffffffff +#define EFUSE_BLK3_DIN6_S 0 + +#define EFUSE_BLK3_WDATA7_REG (DR_REG_EFUSE_BASE + 0x0f4) + +/* EFUSE_BLK3_DIN7 : R/W ;bitpos:[31:0] ;default: 32'h0 ; + * Description: program for BLOCK3 + */ + +#define EFUSE_BLK3_DIN7 0xffffffff +#define EFUSE_BLK3_DIN7_M ((EFUSE_BLK3_DIN7_V) << \ + (EFUSE_BLK3_DIN7_S)) +#define EFUSE_BLK3_DIN7_V 0xffffffff +#define EFUSE_BLK3_DIN7_S 0 + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x0f8) + +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (BIT(16)) +#define EFUSE_CLK_EN_V 0x1 +#define EFUSE_CLK_EN_S 16 + +/* EFUSE_CLK_SEL1 : R/W ;bitpos:[15:8] ;default: 8'h40 ; + * Description: efuse timing configure + */ + +#define EFUSE_CLK_SEL1 0x000000ff +#define EFUSE_CLK_SEL1_M ((EFUSE_CLK_SEL1_V) << \ + (EFUSE_CLK_SEL1_S)) +#define EFUSE_CLK_SEL1_V 0xff +#define EFUSE_CLK_SEL1_S 8 + +/* EFUSE_CLK_SEL0 : R/W ;bitpos:[7:0] ;default: 8'h52 ; + * Description: efuse timing configure + */ + +#define EFUSE_CLK_SEL0 0x000000ff +#define EFUSE_CLK_SEL0_M ((EFUSE_CLK_SEL0_V) << \ + (EFUSE_CLK_SEL0_S)) +#define EFUSE_CLK_SEL0_V 0xff +#define EFUSE_CLK_SEL0_S 0 + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x0fc) + +/* EFUSE_FORCE_NO_WR_RD_DIS : R/W ;bitpos:[16] ;default: 1'h1 ; + * Description: + */ + +#define EFUSE_FORCE_NO_WR_RD_DIS (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_M (BIT(16)) +#define EFUSE_FORCE_NO_WR_RD_DIS_V 0x1 +#define EFUSE_FORCE_NO_WR_RD_DIS_S 16 + +/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; + * Description: efuse operation code + */ + +#define EFUSE_OP_CODE 0x0000ffff +#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << \ + (EFUSE_OP_CODE_S)) +#define EFUSE_OP_CODE_V 0xffff +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x100) + +/* EFUSE_DEBUG : RO ;bitpos:[31:0] ;default: 32'h0 ; + * Description: + */ + +#define EFUSE_DEBUG 0xffffffff +#define EFUSE_DEBUG_M ((EFUSE_DEBUG_V) << \ + (EFUSE_DEBUG_S)) +#define EFUSE_DEBUG_V 0xffffffff +#define EFUSE_DEBUG_S 0 + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x104) + +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; + * Description: command for program + */ + +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (BIT(1)) +#define EFUSE_PGM_CMD_V 0x1 +#define EFUSE_PGM_CMD_S 1 + +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; + * Description: command for read + */ + +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (BIT(0)) +#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_S 0 + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x108) + +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; + * Description: program done interrupt raw status + */ + +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_V 0x1 +#define EFUSE_PGM_DONE_INT_RAW_S 1 + +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; + * Description: read done interrupt raw status + */ + +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x10c) + +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; + * Description: program done interrupt status + */ + +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_V 0x1 +#define EFUSE_PGM_DONE_INT_ST_S 1 + +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; + * Description: read done interrupt status + */ + +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_S 0 + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x110) + +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; + * Description: program done interrupt enable + */ + +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_V 0x1 +#define EFUSE_PGM_DONE_INT_ENA_S 1 + +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; + * Description: read done interrupt enable + */ + +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x114) + +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; + * Description: program done interrupt clear + */ + +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_V 0x1 +#define EFUSE_PGM_DONE_INT_CLR_S 1 + +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; + * Description: read done interrupt clear + */ + +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x118) + +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; + * Description: + */ + +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 + +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; + * Description: efuse timing configure + */ + +#define EFUSE_DAC_CLK_DIV 0x000000ff +#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << \ + (EFUSE_DAC_CLK_DIV_S)) +#define EFUSE_DAC_CLK_DIV_V 0xff +#define EFUSE_DAC_CLK_DIV_S 0 + +#define EFUSE_DEC_STATUS_REG (DR_REG_EFUSE_BASE + 0x11c) + +/* EFUSE_DEC_WARNINGS : RO ;bitpos:[11:0] ;default: 12'b0 ; + * Description: the decode result of 3/4 coding scheme has warning + */ + +#define EFUSE_DEC_WARNINGS 0x00000fff +#define EFUSE_DEC_WARNINGS_M ((EFUSE_DEC_WARNINGS_V) << \ + (EFUSE_DEC_WARNINGS_S)) +#define EFUSE_DEC_WARNINGS_V 0xfff +#define EFUSE_DEC_WARNINGS_S 0 + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) + +/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h16042600 ; + * Description: + */ + +#define EFUSE_DATE 0xffffffff +#define EFUSE_DATE_M ((EFUSE_DATE_V) << \ + (EFUSE_DATE_S)) +#define EFUSE_DATE_V 0xffffffff +#define EFUSE_DATE_S 0 + +#endif /* __ARCH_XTENSA_INCLUDE_EFUSE_REG_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_caps.h b/arch/xtensa/src/esp32/hardware/esp32_caps.h new file mode 100644 index 0000000000..e8e2871175 --- /dev/null +++ b/arch/xtensa/src/esp32/hardware/esp32_caps.h @@ -0,0 +1,64 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/hardware/esp32_caps.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_CAPS_H +#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_CAPS_H + +#define SOC_SPI_PERIPH_NUM 3 +#define SOC_SPI_DMA_CHAN_NUM 2 +#define SOC_SPI_PERIPH_CS_NUM(i) 3 + +#define SPI_FUNC_NUM 1 +#define SPI_IOMUX_PIN_NUM_MISO 7 +#define SPI_IOMUX_PIN_NUM_MOSI 8 +#define SPI_IOMUX_PIN_NUM_CLK 6 +#define SPI_IOMUX_PIN_NUM_CS 11 +#define SPI_IOMUX_PIN_NUM_WP 10 +#define SPI_IOMUX_PIN_NUM_HD 9 + +#define HSPI_FUNC_NUM 1 + +/* For D2WD and PICO-D4 chip */ + +#define SPI_D2WD_PIN_NUM_MISO 17 +#define SPI_D2WD_PIN_NUM_MOSI 8 +#define SPI_D2WD_PIN_NUM_CLK 6 +#define SPI_D2WD_PIN_NUM_CS 16 +#define SPI_D2WD_PIN_NUM_WP 7 +#define SPI_D2WD_PIN_NUM_HD 11 + +#define HSPI_IOMUX_PIN_NUM_MISO 12 +#define HSPI_IOMUX_PIN_NUM_MOSI 13 +#define HSPI_IOMUX_PIN_NUM_CLK 14 +#define HSPI_IOMUX_PIN_NUM_CS 15 +#define HSPI_IOMUX_PIN_NUM_WP 2 +#define HSPI_IOMUX_PIN_NUM_HD 4 + +#define VSPI_FUNC_NUM 1 +#define VSPI_IOMUX_PIN_NUM_MISO 19 +#define VSPI_IOMUX_PIN_NUM_MOSI 23 +#define VSPI_IOMUX_PIN_NUM_CLK 18 +#define VSPI_IOMUX_PIN_NUM_CS 5 +#define VSPI_IOMUX_PIN_NUM_WP 22 +#define VSPI_IOMUX_PIN_NUM_HD 21 + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 + +#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_CAPS_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 6dc649e289..6bee44c22d 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -246,6 +246,30 @@ #define DR_REG_PWM3_BASE 0x3ff70000 #define PERIPHS_SPI_ENCRYPT_BASEADDR DR_REG_SPI_ENCRYPT_BASE +/* Overall memory map */ +#define SOC_DROM_LOW 0x3f400000 +#define SOC_DROM_HIGH 0x3f800000 +#define SOC_DRAM_LOW 0x3ffae000 +#define SOC_DRAM_HIGH 0x40000000 +#define SOC_IROM_LOW 0x400d0000 +#define SOC_IROM_HIGH 0x40400000 +#define SOC_IROM_MASK_LOW 0x40000000 +#define SOC_IROM_MASK_HIGH 0x40064f00 +#define SOC_CACHE_PRO_LOW 0x40070000 +#define SOC_CACHE_PRO_HIGH 0x40078000 +#define SOC_CACHE_APP_LOW 0x40078000 +#define SOC_CACHE_APP_HIGH 0x40080000 +#define SOC_IRAM_LOW 0x40080000 +#define SOC_IRAM_HIGH 0x400a0000 +#define SOC_RTC_IRAM_LOW 0x400c0000 +#define SOC_RTC_IRAM_HIGH 0x400c2000 +#define SOC_RTC_DRAM_LOW 0x3ff80000 +#define SOC_RTC_DRAM_HIGH 0x3ff82000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_EXTRAM_DATA_LOW 0x3f800000 +#define SOC_EXTRAM_DATA_HIGH 0x3fc00000 + /* Interrupt hardware source table * This table is decided by hardware, don't touch this. */ diff --git a/arch/xtensa/src/esp32/rom/esp32_efuse.h b/arch/xtensa/src/esp32/rom/esp32_efuse.h new file mode 100644 index 0000000000..c199624e04 --- /dev/null +++ b/arch/xtensa/src/esp32/rom/esp32_efuse.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/xtensa/src/esp32/rom/esp32_efuse.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __XTENSA_SRC_ESP32_ROM_ESP32_EFUSE_H +#define __XTENSA_SRC_ESP32_ROM_ESP32_EFUSE_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: ets_efuse_read_op + ****************************************************************************/ + +void ets_efuse_read_op(void); + +/**************************************************************************** + * Name: ets_efuse_program_op + ****************************************************************************/ + +void ets_efuse_program_op(void); + +/**************************************************************************** + * Name: ets_efuse_get_8m_clock + ****************************************************************************/ + +uint32_t ets_efuse_get_8m_clock(void); + +/**************************************************************************** + * name: ets_efuse_get_spiconfig + ****************************************************************************/ + +uint32_t ets_efuse_get_spiconfig(void); + +#define EFUSE_SPICFG_SPI_DEFAULTS 0 +#define EFUSE_SPICFG_HSPI_DEFAULTS 1 + +#define EFUSE_SPICFG_RET_SPICLK_MASK 0x3f +#define EFUSE_SPICFG_RET_SPICLK_SHIFT 0 +#define EFUSE_SPICFG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICFG_RET_SPICLK_SHIFT) & EFUSE_SPICFG_RET_SPICLK_MASK) + +#define EFUSE_SPICFG_RET_SPIQ_MASK 0x3f +#define EFUSE_SPICFG_RET_SPIQ_SHIFT 6 +#define EFUSE_SPICFG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICFG_RET_SPIQ_SHIFT) & EFUSE_SPICFG_RET_SPIQ_MASK) + +#define EFUSE_SPICFG_RET_SPID_MASK 0x3f +#define EFUSE_SPICFG_RET_SPID_SHIFT 12 +#define EFUSE_SPICFG_RET_SPID(ret) (((ret) >> EFUSE_SPICFG_RET_SPID_SHIFT) & EFUSE_SPICFG_RET_SPID_MASK) + +#define EFUSE_SPICFG_RET_SPICS0_MASK 0x3f +#define EFUSE_SPICFG_RET_SPICS0_SHIFT 18 +#define EFUSE_SPICFG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICFG_RET_SPICS0_SHIFT) & EFUSE_SPICFG_RET_SPICS0_MASK) + +#define EFUSE_SPICFG_RET_SPIHD_MASK 0x3f +#define EFUSE_SPICFG_RET_SPIHD_SHIFT 24 +#define EFUSE_SPICFG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICFG_RET_SPIHD_SHIFT) & EFUSE_SPICFG_RET_SPIHD_MASK) + +/**************************************************************************** + * name: eps_crc8 + ****************************************************************************/ + +unsigned char esp_crc8(unsigned char const *p, unsigned int len); + +#ifdef __cplusplus +} +#endif + +#endif /* __XTENSA_SRC_ESP32_ROM_ESP32_EFUSE_H */