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Don't waste vector slots if features disabled

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1194 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2008-11-11 19:34:44 +00:00
parent e0a1f6ef60
commit 23304550c4
1 changed files with 171 additions and 110 deletions
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281
arch/sh/include/sh1/irq.h
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@ -53,70 +53,70 @@
/* IRQ channels */
/* Illegal instructions / Address errors */
#define SH1_INVINSTR_IRQ (0) /* General invalid instruction */
#define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */
#define SH1_BUSERR_IRQ (2) /* CPU bus error */
#define SH1_DMAERR_IRQ (3) /* DMA bus error */
#define SH1_NMI_IRQ (4) /* NMI */
#define SH1_USRBRK_IRQ (6) /* User break */
/* Support for traps can be provided by simply enabling the following and
* implementing the stubs to catch the interrupts
/* In the current implementation, CMON catches the following IRQ.
* Support for traps can be provided by simply enabling the following, adding
* vectors in sh1_head.S and adding handlers in sh1_vector.S
*/
#if 0
# define SH1_TRAP_IRQ (7) /* TRAPA instruction (user break) */
# define SH1_TRAP0_IRQ (SH1_TRAP_IRQ+0) /* TRAPA instruction (user break) */
# define SH1_TRAP1_IRQ (SH1_TRAP_IRQ+1) /* " " " " " " " " */
# define SH1_TRAP2_IRQ (SH1_TRAP_IRQ+2) /* " " " " " " " " */
# define SH1_TRAP3_IRQ (SH1_TRAP_IRQ+3) /* " " " " " " " " */
# define SH1_TRAP4_IRQ (SH1_TRAP_IRQ+4) /* " " " " " " " " */
# define SH1_TRAP5_IRQ (SH1_TRAP_IRQ+5) /* " " " " " " " " */
# define SH1_TRAP6_IRQ (SH1_TRAP_IRQ+6) /* " " " " " " " " */
# define SH1_TRAP7_IRQ (SH1_TRAP_IRQ+7) /* " " " " " " " " */
# define SH1_TRAP8_IRQ (SH1_TRAP_IRQ+8) /* " " " " " " " " */
# define SH1_TRAP9_IRQ (SH1_TRAP_IRQ+9) /* " " " " " " " " */
# define SH1_TRAP10_IRQ (SH1_TRAP_IRQ+10) /* " " " " " " " " */
# define SH1_TRAP11_IRQ (SH1_TRAP_IRQ+11) /* " " " " " " " " */
# define SH1_TRAP12_IRQ (SH1_TRAP_IRQ+12) /* " " " " " " " " */
# define SH1_TRAP13_IRQ (SH1_TRAP_IRQ+13) /* " " " " " " " " */
# define SH1_TRAP14_IRQ (SH1_TRAP_IRQ+14) /* " " " " " " " " */
# define SH1_TRAP15_IRQ (SH1_TRAP_IRQ+15) /* " " " " " " " " */
# define SH1_TRAP16_IRQ (SH1_TRAP_IRQ+16) /* " " " " " " " " */
# define SH1_TRAP17_IRQ (SH1_TRAP_IRQ+17) /* " " " " " " " " */
# define SH1_TRAP18_IRQ (SH1_TRAP_IRQ+18) /* " " " " " " " " */
# define SH1_TRAP19_IRQ (SH1_TRAP_IRQ+19) /* " " " " " " " " */
# define SH1_TRAP20_IRQ (SH1_TRAP_IRQ+20) /* " " " " " " " " */
# define SH1_TRAP21_IRQ (SH1_TRAP_IRQ+21) /* " " " " " " " " */
# define SH1_TRAP22_IRQ (SH1_TRAP_IRQ+22) /* " " " " " " " " */
# define SH1_TRAP23_IRQ (SH1_TRAP_IRQ+23) /* " " " " " " " " */
# define SH1_TRAP24_IRQ (SH1_TRAP_IRQ+24) /* " " " " " " " " */
# define SH1_TRAP25_IRQ (SH1_TRAP_IRQ+25) /* " " " " " " " " */
# define SH1_TRAP26_IRQ (SH1_TRAP_IRQ+26) /* " " " " " " " " */
# define SH1_TRAP27_IRQ (SH1_TRAP_IRQ+27) /* " " " " " " " " */
# define SH1_TRAP28_IRQ (SH1_TRAP_IRQ+28) /* " " " " " " " " */
# define SH1_TRAP29_IRQ (SH1_TRAP_IRQ+29) /* " " " " " " " " */
# define SH1_TRAP30_IRQ (SH1_TRAP_IRQ+30) /* " " " " " " " " */
# define SH1_TRAP31_IRQ (SH1_TRAP_IRQ+31) /* " " " " " " " " */
# define SH1_LASTTRAP_IRQ SH1_TRAP31_IRQ
#else
# define SH1_LASTTRAP_IRQ (6)
#endif
/* Illegal instructions / Address errors */
#if 0 /* Handled by CMON */
# define SH1_INVINSTR_IRQ (0) /* General invalid instruction */
# define SH1_INVSLOT_IRQ (1) /* Invalid slot instruction */
# define SH1_BUSERR_IRQ (2) /* CPU bus error */
# define SH1_DMAERR_IRQ (3) /* DMA bus error */
# define SH1_NMI_IRQ (4) /* NMI */
# define SH1_USRBRK_IRQ (6) /* User break */
# define SH1_TRAP_IRQBASE (7)
# define SH1_TRAP0_IRQ SH1_TRAP_IRQBASE /* TRAPA instruction (user break) */
# define SH1_TRAP1_IRQ (SH1_TRAP_IRQBASE+1) /* " " " " " " " " */
# define SH1_TRAP2_IRQ (SH1_TRAP_IRQBASE+2) /* " " " " " " " " */
# define SH1_TRAP3_IRQ (SH1_TRAP_IRQBASE+3) /* " " " " " " " " */
# define SH1_TRAP4_IRQ (SH1_TRAP_IRQBASE+4) /* " " " " " " " " */
# define SH1_TRAP5_IRQ (SH1_TRAP_IRQBASE+5) /* " " " " " " " " */
# define SH1_TRAP6_IRQ (SH1_TRAP_IRQBASE+6) /* " " " " " " " " */
# define SH1_TRAP7_IRQ (SH1_TRAP_IRQBASE+7) /* " " " " " " " " */
# define SH1_TRAP8_IRQ (SH1_TRAP_IRQBASE+8) /* " " " " " " " " */
# define SH1_TRAP9_IRQ (SH1_TRAP_IRQBASE+9) /* " " " " " " " " */
# define SH1_TRAP10_IRQ (SH1_TRAP_IRQBASE+10) /* " " " " " " " " */
# define SH1_TRAP11_IRQ (SH1_TRAP_IRQBASE+11) /* " " " " " " " " */
# define SH1_TRAP12_IRQ (SH1_TRAP_IRQBASE+12) /* " " " " " " " " */
# define SH1_TRAP13_IRQ (SH1_TRAP_IRQBASE+13) /* " " " " " " " " */
# define SH1_TRAP14_IRQ (SH1_TRAP_IRQBASE+14) /* " " " " " " " " */
# define SH1_TRAP15_IRQ (SH1_TRAP_IRQBASE+15) /* " " " " " " " " */
# define SH1_TRAP16_IRQ (SH1_TRAP_IRQBASE+16) /* " " " " " " " " */
# define SH1_TRAP17_IRQ (SH1_TRAP_IRQBASE+17) /* " " " " " " " " */
# define SH1_TRAP18_IRQ (SH1_TRAP_IRQBASE+18) /* " " " " " " " " */
# define SH1_TRAP19_IRQ (SH1_TRAP_IRQBASE+19) /* " " " " " " " " */
# define SH1_TRAP20_IRQ (SH1_TRAP_IRQBASE+20) /* " " " " " " " " */
# define SH1_TRAP21_IRQ (SH1_TRAP_IRQBASE+21) /* " " " " " " " " */
# define SH1_TRAP22_IRQ (SH1_TRAP_IRQBASE+22) /* " " " " " " " " */
# define SH1_TRAP23_IRQ (SH1_TRAP_IRQBASE+23) /* " " " " " " " " */
# define SH1_TRAP24_IRQ (SH1_TRAP_IRQBASE+24) /* " " " " " " " " */
# define SH1_TRAP25_IRQ (SH1_TRAP_IRQBASE+25) /* " " " " " " " " */
# define SH1_TRAP26_IRQ (SH1_TRAP_IRQBASE+26) /* " " " " " " " " */
# define SH1_TRAP27_IRQ (SH1_TRAP_IRQBASE+27) /* " " " " " " " " */
# define SH1_TRAP28_IRQ (SH1_TRAP_IRQBASE+28) /* " " " " " " " " */
# define SH1_TRAP29_IRQ (SH1_TRAP_IRQBASE+29) /* " " " " " " " " */
# define SH1_TRAP30_IRQ (SH1_TRAP_IRQBASE+30) /* " " " " " " " " */
# define SH1_TRAP31_IRQ (SH1_TRAP_IRQBASE+31) /* " " " " " " " " */
# define SH1_IRQ_IRQBASE (SH1_TRAP_IRQBASE+32)
/* Interrupts */
#define SH1_IRQ_IRQ (SH1_LASTTRAP_IRQ+1) /* IRQ0-7 */
#define SH1_IRQ0_IRQ (SH1_IRQ_IRQ+0) /* IRQ0 */
#define SH1_IRQ1_IRQ (SH1_IRQ_IRQ+1) /* IRQ1 */
#define SH1_IRQ2_IRQ (SH1_IRQ_IRQ+2) /* IRQ2 */
#define SH1_IRQ3_IRQ (SH1_IRQ_IRQ+3) /* IRQ3 */
#define SH1_IRQ4_IRQ (SH1_IRQ_IRQ+4) /* IRQ4 */
#define SH1_IRQ5_IRQ (SH1_IRQ_IRQ+5) /* IRQ5 */
#define SH1_IRQ6_IRQ (SH1_IRQ_IRQ+6) /* IRQ6 */
#define SH1_IRQ7_IRQ (SH1_IRQ_IRQ+7) /* IRQ7 */
#define SH1_LASTIRQ_IRQ SH1_IRQ7_IRQ
# define SH1_IRQ0_IRQ SH1_IRQ_IRQBASE /* IRQ0 */
# define SH1_IRQ1_IRQ (SH1_IRQ_IRQBASE+1) /* IRQ1 */
# define SH1_IRQ2_IRQ (SH1_IRQ_IRQBASE+2) /* IRQ2 */
# define SH1_IRQ3_IRQ (SH1_IRQ_IRQBASE+3) /* IRQ3 */
# define SH1_IRQ4_IRQ (SH1_IRQ_IRQBASE+4) /* IRQ4 */
# define SH1_IRQ5_IRQ (SH1_IRQ_IRQBASE+5) /* IRQ5 */
# define SH1_IRQ6_IRQ (SH1_IRQ_IRQBASE+6) /* IRQ6 */
# define SH1_IRQ7_IRQ (SH1_IRQ_IRQBASE+7) /* IRQ7 */
# define SH1_CHIP_IRQBASE (SH1_IRQ_IRQBASE+8)
#else
# define SH1_CHIP_IRQBASE (0)
#endif
/* On-chip modules -- The following may be unique to the 7032 */
@ -124,75 +124,136 @@
/* DMAC */
#define SH1_DMAC0_IRQ (SH1_LASTIRQ_IRQ+1) /* DMAC0 */
#define SH1_DEI0_IRQ SH1_DMAC0_IRQ /* DEI0 */
#define SH1_DMAC1_IRQ (SH1_LASTIRQ_IRQ+2) /* DMAC1 */
#define SH1_DEI1_IRQ SH1_DMAC1_IRQ /* DEI1 */
#define SH1_DMAC2_IRQ (SH1_LASTIRQ_IRQ+3) /* DMAC2 */
#define SH1_DEI2_IRQ SH1_DMAC2_IRQ /* DEI2 */
#define SH1_DMAC3_IRQ (SH1_LASTIRQ_IRQ+4) /* DMAC3 */
#define SH1_DEI3_IRQ SH1_DMAC3_IRQ /* DEI3 */
#define SH1_LASTDMAC_IRQ SH1_DEI3_IRQ
#ifdef CONFIG_SH1_DMAC0 /* DMAC0 */
# define SH1_DEI0_IRQ SH1_CHIP_IRQBASE /* DEI0 */
# define SH1_DMAC1_IRQBASE (SH1_CHIP_IRQBASE+1)
#else
# define SH1_DMAC1_IRQBASE SH1_CHIP_IRQBASE
#endif
#ifdef CONFIG_SH1_DMAC1 /* DMAC1 */
# define SH1_DEI1_IRQ SH1_DMAC1_IRQBASE /* DEI1 */
# define SH1_DMAC2_IRQBASE (SH1_DMAC1_IRQBASE+1)
#else
# define SH1_DMAC2_IRQBASE SH1_DMAC1_IRQBASE
#endif
#ifdef CONFIG_SH1_DMAC2 /* DMAC2 */
# define SH1_DEI2_IRQ SH1_DMAC2_IRQBASE /* DEI2 */
# define SH1_DMAC3_IRQBASE (SH1_DMAC2_IRQBASE+1)
#else
# define SH1_DMAC3_IRQBASE SH1_DMAC2_IRQBASE
#endif
#ifdef CONFIG_SH1_DMAC3 /* DMAC3 */
# define SH1_DEI3_IRQ SH1_DMAC3_IRQBASE /* DEI3 */
# define SH1_ITU0_IRQBASE (SH1_DMAC3_IRQBASE+1)
#else
# define SH1_ITU0_IRQBASE SH1_DMAC3_IRQBASE
#endif
/* ITU */
#define SH1_ITU0_IRQ (SH1_LASTDMAC_IRQ+1) /* ITU0 */
#define SH1_IMIA0_IRQ (SH1_ITU0_IRQ+0) /* IMIA0 */
#define SH1_IMIB0_IRQ (SH1_ITU0_IRQ+1) /* IMIB0 */
#define SH1_OVI0_IRQ (SH1_ITU0_IRQ+2) /* OVI0 */
/* ITU0 is the system clock and is always defined */
#define SH1_ITU1_IRQ (SH1_LASTDMAC_IRQ+4) /* ITU1 */
#define SH1_IMIA1_IRQ (SH1_ITU1_IRQ+0) /* IMIA1 */
#define SH1_IMIB1_IRQ (SH1_ITU1_IRQ+1) /* IMIB1 */
#define SH1_OVI1_IRQ (SH1_ITU1_IRQ+2) /* OVI1 */
#define SH1_IMIA0_IRQ SH1_ITU0_IRQBASE /* IMIA0 */
#define SH1_IMIB0_IRQ (SH1_ITU0_IRQBASE+1) /* IMIB0 */
#define SH1_OVI0_IRQ (SH1_ITU0_IRQBASE+2) /* OVI0 */
#define SH1_ITU1_IRQBASE (SH1_ITU0_IRQBASE+3)
#define SH1_ITU2_IRQ (SH1_LASTDMAC_IRQ+7) /* ITU2 */
#define SH1_IMIA2_IRQ (SH1_ITU2_IRQ+0) /* IMIA2 */
#define SH1_IMIB2_IRQ (SH1_ITU2_IRQ+1) /* IMIB2 */
#define SH1_OVI2_IRQ (SH1_ITU2_IRQ+2) /* OVI2 */
#ifdef CONFIG_SH1_ITU1 /* ITU1 */
# define SH1_IMIA1_IRQ SH1_ITU1_IRQBASE /* IMIA1 */
# define SH1_IMIB1_IRQ (SH1_ITU1_IRQBASE+1) /* IMIB1 */
# define SH1_OVI1_IRQ (SH1_ITU1_IRQBASE+2) /* OVI1 */
# define SH1_ITU2_IRQBASE (SH1_ITU1_IRQBASE+3)
#else
# define SH1_ITU2_IRQBASE SH1_ITU1_IRQBASE
#endif
#define SH1_ITU3_IRQ (SH1_LASTDMAC_IRQ+10) /* ITU3 */
#define SH1_IMIA3_IRQ (SH1_ITU3_IRQ+0) /* IMIA3 */
#define SH1_IMIB3_IRQ (SH1_ITU3_IRQ+1) /* IMIB3 */
#define SH1_OVI3_IRQ (SH1_ITU3_IRQ+2) /* OVI3 */
#ifdef CONFIG_SH1_ITU2 /* ITU2 */
# define SH1_IMIA2_IRQ SH1_ITU2_IRQBASE /* IMIA2 */
# define SH1_IMIB2_IRQ (SH1_ITU2_IRQBASE+1) /* IMIB2 */
# define SH1_OVI2_IRQ (SH1_ITU2_IRQBASE+2) /* OVI2 */
# define SH1_ITU3_IRQBASE (SH1_ITU2_IRQBASE+3)
#else
# define SH1_ITU3_IRQBASE SH1_ITU2_IRQBASE
#endif
#define SH1_ITU4_IRQ (SH1_LASTDMAC_IRQ+13) /* ITU4 */
#define SH1_IMIA4_IRQ (SH1_ITU4_IRQ+0) /* IMIA4 */
#define SH1_IMIB4_IRQ (SH1_ITU4_IRQ+1) /* IMIB4 */
#define SH1_OVI4_IRQ (SH1_ITU4_IRQ+2) /* OVI4 */
#ifdef CONFIG_SH1_ITU3 /* ITU3 */
# define SH1_IMIA3_IRQ SH1_ITU3_IRQBASE /* IMIA3 */
# define SH1_IMIB3_IRQ (SH1_ITU3_IRQBASE+1) /* IMIB3 */
# define SH1_OVI3_IRQ (SH1_ITU3_IRQBASE+2) /* OVI3 */
# define SH1_ITU4_IRQBASE (SH1_ITU3_IRQBASE+3)
#else
# define SH1_ITU4_IRQBASE SH1_ITU3_IRQBASE
#endif
#define SH1_LASTITU_IRQ (SH1_LASTDMAC_IRQ+15)
#ifdef CONFIG_SH1_ITU4 /* ITU4 */
# define SH1_IMIA4_IRQ SH1_ITU4_IRQBASE /* IMIA4 */
# define SH1_IMIB4_IRQ (SH1_ITU4_IRQBASE+1) /* IMIB4 */
# define SH1_OVI4_IRQ (SH1_ITU4_IRQBASE+2) /* OVI4 */
# define SH1_SCI0_IRQBASE (SH1_ITU4_IRQBASE+3)
#else
# define SH1_SCI0_IRQBASE SH1_ITU4_IRQBASE
#endif
/* SCI */
#define SH1_ERI_IRQ_OFFSET (0) /* ERI0 */
#define SH1_RXI_IRQ_OFFSET (1) /* RxI0 */
#define SH1_TXI_IRQ_OFFSET (2) /* TxI0 */
#define SH1_TEI_IRQ_OFFSET (3) /* TEI0 */
#define SH1_ERI_IRQ_OFFSET (0) /* ERI0 */
#define SH1_RXI_IRQ_OFFSET (1) /* RxI0 */
#define SH1_TXI_IRQ_OFFSET (2) /* TxI0 */
#define SH1_TEI_IRQ_OFFSET (3) /* TEI0 */
#define SH1_SCI_NIRQS (4)
#define SH1_SCI0_IRQ (SH1_LASTITU_IRQ+1) /* SCI0 */
#define SH1_ERI0_IRQ (SH1_SCI0_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI0 */
#define SH1_RXI0_IRQ (SH1_SCI0_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI0 */
#define SH1_TXI0_IRQ (SH1_SCI0_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI0 */
#define SH1_TEI0_IRQ (SH1_SCI0_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI0 */
#ifdef CONFIG_SH1_SCI0 /* SCI0 */
# define SH1_ERI0_IRQ (SH1_SCI0_IRQBASE+SH1_ERI_IRQ_OFFSET) /* ERI0 */
# define SH1_RXI0_IRQ (SH1_SCI0_IRQBASE+SH1_RXI_IRQ_OFFSET) /* RxI0 */
# define SH1_TXI0_IRQ (SH1_SCI0_IRQBASE+SH1_TXI_IRQ_OFFSET) /* TxI0 */
# define SH1_TEI0_IRQ (SH1_SCI0_IRQBASE+SH1_TEI_IRQ_OFFSET) /* TEI0 */
# define SH1_SCI1_IRQBASE (SH1_SCI0_IRQBASE+SH1_SCI_NIRQS)
#else
# define SH1_SCI1_IRQBASE SH1_SCI0_IRQBASE
#endif
#define SH1_SCI1_IRQ (SH1_SCI0_IRQ+SH1_SCI_NIRQS) /* SCI1 */
#define SH1_ERI1_IRQ (SH1_SCI1_IRQ+SH1_ERI_IRQ_OFFSET) /* ERI1 */
#define SH1_RXI1_IRQ (SH1_SCI1_IRQ+SH1_RXI_IRQ_OFFSET) /* RxI1 */
#define SH1_TXI1_IRQ (SH1_SCI1_IRQ+SH1_TXI_IRQ_OFFSET) /* TxI1 */
#define SH1_TEI1_IRQ (SH1_SCI1_IRQ+SH1_TEI_IRQ_OFFSET) /* TEI1 */
#ifdef CONFIG_SH1_SCI1 /* SCI1 */
# define SH1_ERI1_IRQ (SH1_SCI1_IRQBASE+SH1_ERI_IRQ_OFFSET) /* ERI1 */
# define SH1_RXI1_IRQ (SH1_SCI1_IRQBASE+SH1_RXI_IRQ_OFFSET) /* RxI1 */
# define SH1_TXI1_IRQ (SH1_SCI1_IRQBASE+SH1_TXI_IRQ_OFFSET) /* TxI1 */
# define SH1_TEI1_IRQ (SH1_SCI1_IRQBASE+SH1_TEI_IRQ_OFFSET) /* TEI1 */
# define SH1_PEI_IRQBASE (SH1_SCI1_IRQBASE+SH1_SCI_NIRQS)
#else
# define SH1_PEI_IRQBASE SH1_SCI1_IRQBASE
#endif
#define SH1_LASTSCI_IRQ (SH1_SCI1_IRQ+SH1_SCI_NIRQS)
#ifdef CONFIG_SH1_PCU
# define SH1_PEI_IRQ SH1_PEI_IRQBASE /* Parity control unit PEI */
# define SH1_AD_IRQBASE (SH1_PEI_IRQBASE+1)
#else
# define SH1_AD_IRQBASE SH1_PEI_IRQBASE
#endif
#define SH1_PEI_IRQ (SH1_LASTSCI_IRQ+1) /* Parity control unit PEI */
#define SH1_ADITI_IRQ (SH1_LASTSCI_IRQ+2) /* A/D ITI */
#define SH1_WDTITI_IRQ (SH1_LASTSCI_IRQ+3) /* WDT ITI */
#define SH1_CMI_IRQ (SH1_LASTSCI_IRQ+4) /* REF CMI */
#ifdef CONFIG_SH1_AD
# define SH1_ADITI_IRQ SH1_AD_IRQBASE /* A/D ITI */
# define SH1_WDT_IRQBASE (SH1_AD_IRQBASE+1)
#else
# define SH1_WDT_IRQBASE SH1_AD_IRQBASE
#endif
#ifdef CONFIG_SH1_WDT
# define SH1_WDTITI_IRQ SH1_WDT_IRQBASE /* WDT ITI */
# define SH1_CMI_IRQBASE (SH1_WDT_IRQBASE+1)
#else
# define SH1_CMI_IRQBASE SH1_WDT_IRQBASE
#endif
#ifdef CONFIG_SH1_CMI
# define SH1_CMI_IRQ SH1_CMI_IRQBASE /* REF CMI */
# define NR_IRQS (SH1_CMI_IRQBASE+1) /* Total number of supported IRQs */
#else
# define NR_IRQS SH1_CMI_IRQBASE /* Total number of supported IRQs */
#endif
#define SH1_SYSTIMER_IRQ SH1_IMIA0_IRQ
#define NR_IRQS (SH1_CMI_IRQ+1)
#endif
/* Vector table offets **************************************************************/