Clean-up from last commit to make sure that all files have BSD licensed header with the correct authors and that the code conforms to the NuttX coding style
This commit is contained in:
Gregory Nutt
parent
7d59c21c2a
commit
23ed19c514
@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/include/moxart/irq.h
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*
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* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -33,8 +33,8 @@
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*
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****************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_MOXART_IRQ_H
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@ -1,5 +1,5 @@
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############################################################################
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# calypso/Make.defs
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# arch/arm/src/moxart/Make.defs
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#
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# Copyright (C) 2007, 2013-2015 Gregory Nutt. All rights reserved.
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# Author: Gregory Nutt <gnutt@nuttx.org>
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@ -56,4 +56,3 @@ CHIP_ASRCS = moxart_lowputc.S
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CHIP_CSRCS = moxart_16550.c moxart_irq.c moxart_timer.c moxart_idle.c
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CHIP_CSRCS += moxart_systemreset.c
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/moxa/chip.h
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* arch/arm/src/moxart/chip.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -42,38 +42,38 @@
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#include <nuttx/config.h>
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#define UART0_BASE 0x98200000
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#define UART0_BASE 0x98200000
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#define UART_THR 0x00
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#define UART_LSR 0x14
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#define UART_LSR_THRE 0x20
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#define UART_THR 0x00
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#define UART_LSR 0x14
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#define UART_LSR_THRE 0x20
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/* Common UART Registers. Expressed as offsets from the BASE address */
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#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */
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#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */
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#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */
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#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */
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#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */
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#define UART_SCR_OFFS 0x00000010 /* Status Control Register */
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#define UART_LCR_OFFS 0x00000003 /* Line Control Register */
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#define UART_LSR_OFFS 0x00000005 /* Line Status Register */
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#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */
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#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */
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#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */
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#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */
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#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */
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#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */
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#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */
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#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */
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#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */
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#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */
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#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */
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#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */
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#define UART_DIV_HIGH_OFFS 0x00000001
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#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */
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#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */
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#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */
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#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */
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#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */
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#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */
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#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */
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#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */
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#define UART_SCR_OFFS 0x00000010 /* Status Control Register */
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#define UART_LCR_OFFS 0x00000003 /* Line Control Register */
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#define UART_LSR_OFFS 0x00000005 /* Line Status Register */
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#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */
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#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */
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#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */
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#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */
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#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */
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#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */
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#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */
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#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */
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#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */
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#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */
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#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */
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#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */
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#define UART_DIV_HIGH_OFFS 0x00000001
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#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */
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#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */
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#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */
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/* UART Settings ************************************************************/
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@ -1,3 +1,39 @@
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/******************************************************************************
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* arch/arm/src/moxart/moxart_irq.c
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* Driver for MoxaRT IRQ controller
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Anton D. Kachalov <mouse@mayc.ru>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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@ -13,6 +49,10 @@
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#include "arm.h"
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#include "up_arch.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset)
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{
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return *((volatile uart_addrwidth_t *)base + offset);
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@ -1,11 +1,48 @@
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/******************************************************************************
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* arch/arm/src/moxart/moxart_head.S
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Anton D. Kachalov <mouse@mayc.ru>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/* Place a branch to the real head at the entry point */
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.section .text.start
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b __start
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/* Exception Vectors like they are needed for the exception vector
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indirection of the internal boot ROM. The following section must
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be liked to appear at 0x80001c */
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* indirection of the internal boot ROM. The following section must be
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* linked to appear at 0x80001c
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*/
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.section .text.exceptions
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_undef_instr:
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b up_vectorundefinsn
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/common/up_idle.c
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* arch/arm/src/common/moxart_idle.c
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*
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* Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -45,8 +45,9 @@
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define BEGIN_IDLE (*(volatile uint32_t *)0x98700000) &= ~0x10
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#define END_IDLE (*(volatile uint32_t *)0x98700000) |= 0x10
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#define BEGIN_IDLE (*(volatile uint32_t *)0x98700000) &= ~0x10
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#define END_IDLE (*(volatile uint32_t *)0x98700000) |= 0x10
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/****************************************************************************
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* Private Data
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@ -87,9 +88,15 @@ void up_idle(void)
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/* Sleep until an interrupt occurs to save power */
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BEGIN_IDLE;
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//asm("nop\nnop\nmcr p15, 0, r0, c7, c0, 4\n");
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for (i=0; i<0x40000; i++) asm("nop");
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for (i = 0; i < 0x40000; i++)
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{
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asm("nop");
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}
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END_IDLE;
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for (i=0; i<0x40000; i++) asm("nop");
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for (i = 0; i < 0x40000; i++)
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{
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asm("nop");
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}
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#endif
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}
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@ -2,11 +2,8 @@
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* arch/arm/src/moxart/moxart_irq.c
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* Driver for MoxaRT IRQ controller
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*
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* (C) 2010 by Harald Welte <laforge@gnumonks.org>
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* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
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*
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* This source code is derivated from Osmocom-BB project and was
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* relicensed as BSD with permission from original authors.
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Anton D. Kachalov <mouse@mayc.ru>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -56,15 +53,15 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define IRQ_ADDR 0x98800000
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#define IRQ_REG(x) (IRQ_ADDR + x)
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#define IRQ_ADDR 0x98800000
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#define IRQ_REG(x) (IRQ_ADDR + x)
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#define IRQ__SRC 0x00
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#define IRQ__MASK 0x04
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#define IRQ__CLEAR 0x08
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#define IRQ__MODE 0x0C
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#define IRQ__LEVEL 0x10
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#define IRQ__STATUS 0x14
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#define IRQ__SRC 0x00
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#define IRQ__MASK 0x04
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#define IRQ__CLEAR 0x08
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#define IRQ__MODE 0x0C
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#define IRQ__LEVEL 0x10
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#define IRQ__STATUS 0x14
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/****************************************************************************
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* Public Data
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@ -95,6 +92,7 @@ volatile uint32_t *current_regs;
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void up_irqinitialize(void)
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{
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/* Prepare hardware */
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(*(volatile uint32_t *)0x98100008) &= ~0x9;
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while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; }
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@ -104,12 +102,14 @@ void up_irqinitialize(void)
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(*(volatile uint32_t *)0x98800100) = 0xDFF8003F;
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/* Mask all interrupts off */
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putreg32(0, IRQ_REG(IRQ__MASK));
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putreg32(0, IRQ_REG(IRQ__MASK+0x20));
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putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR));
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putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR+0x20));
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/* Initial trigger mode and level */
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putreg32(0, IRQ_REG(IRQ__MODE));
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putreg32(0, IRQ_REG(IRQ__LEVEL));
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putreg32(0, IRQ_REG(IRQ__MODE+0x20));
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@ -124,9 +124,13 @@ void up_irqinitialize(void)
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#if 1
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#define REG(x) (*(volatile uint32_t *)(x))
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lldbg("\n=============================================================\n");
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lldbg("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004), REG(0x98400000), REG(0x98400008));
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lldbg("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010));
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lldbg("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020));
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lldbg("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n",
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REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004),
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REG(0x98400000), REG(0x98400008));
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lldbg("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010));
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lldbg("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n",
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REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020));
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lldbg("=============================================================\n");
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#endif
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@ -137,10 +141,10 @@ void up_irqinitialize(void)
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inline void ftintc010_mask_irq(int irq)
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{
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/*
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* 0: masked
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/* 0: masked
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* 1: unmasked
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*/
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uint32_t mask;
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mask = getreg32(IRQ_REG(IRQ__MASK));
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@ -150,10 +154,10 @@ inline void ftintc010_mask_irq(int irq)
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inline void ftintc010_unmask_irq(int irq)
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{
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/*
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* 0: masked
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/* 0: masked
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* 1: unmasked
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*/
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uint32_t mask;
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mask = getreg32(IRQ_REG(IRQ__MASK));
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@ -167,14 +171,18 @@ inline void ftintc010_set_trig_mode(int irq, int mode)
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irqmode = getreg32(IRQ_REG(IRQ__MODE));
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/*
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* 0: level trigger
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/* 0: level trigger
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* 1: edge trigger
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*/
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if (mode)
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irqmode |= (1 << irq);
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{
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irqmode |= (1 << irq);
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}
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else
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irqmode &= ~(1 << irq);
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{
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irqmode &= ~(1 << irq);
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}
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putreg32(irqmode, IRQ_REG(IRQ__MODE));
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}
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@ -185,14 +193,18 @@ inline void ftintc010_set_trig_level(int irq, int level)
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irqlevel = getreg32(IRQ_REG(IRQ__LEVEL));
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/*
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* 0: active-high level trigger / rising edge trigger
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/* 0: active-high level trigger / rising edge trigger
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* 1: active-low level trigger / falling edge trigger
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*/
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if (level)
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irqlevel |= (1 << irq);
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{
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irqlevel |= (1 << irq);
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}
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else
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irqlevel &= ~(1 << irq);
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{
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irqlevel &= ~(1 << irq);
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}
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putreg32(irqlevel, IRQ_REG(IRQ__LEVEL));
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}
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@ -238,7 +250,9 @@ static int ffs(uint32_t word)
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int t, r;
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if (word == 0)
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return 0;
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{
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return 0;
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}
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t = r = 1;
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@ -273,11 +287,15 @@ void up_decodeirq(uint32_t *regs)
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uint32_t num, status;
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/* Detect & deliver the IRQ */
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|
||||
status = getreg32(IRQ_REG(IRQ__STATUS));
|
||||
if (!status)
|
||||
return;
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* Ack IRQ */
|
||||
|
||||
num = ffs(status) - 1;
|
||||
up_ack_irq(num);
|
||||
|
||||
@ -285,6 +303,5 @@ void up_decodeirq(uint32_t *regs)
|
||||
current_regs = regs;
|
||||
|
||||
irq_dispatch(num, regs);
|
||||
|
||||
current_regs = NULL;
|
||||
}
|
||||
|
||||
@ -1,12 +1,8 @@
|
||||
/**************************************************************************
|
||||
* moxart/moxart_lowputc.S
|
||||
*
|
||||
* Copyright (C) 2011 Stefan Richter. All rights reserved.
|
||||
* Author: Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* based on: c5471/c5471_lowputc.S
|
||||
* Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Anton D. Kachalov <mouse@mayc.ru>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -126,4 +122,3 @@ up_lowputc:
|
||||
/* And return */
|
||||
|
||||
mov pc, lr
|
||||
|
||||
|
||||
@ -1,9 +1,8 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/moxart/moxart_systemreset.c
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Darcy Gong
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Anton D. Kachalov <mouse@mayc.ru>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -46,9 +45,13 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#define FTWDT010_LOAD 0x98500004
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define FTWDT010_LOAD 0x98500004
|
||||
#define FTWDT010_RESTART 0x98500008
|
||||
#define FTWDT010_CR 0x9850000C
|
||||
#define FTWDT010_CR 0x9850000C
|
||||
|
||||
/****************************************************************************
|
||||
* Public functions
|
||||
@ -76,7 +79,6 @@ void up_systemreset(void)
|
||||
for (;;);
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_reset
|
||||
*
|
||||
|
||||
@ -2,11 +2,8 @@
|
||||
* arch/arm/src/moxart/moxart_timer.c
|
||||
* MoxaRT internal Timer Driver
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Anton D. Kachalov <mouse@mayc.ru>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -35,7 +32,7 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
@ -46,73 +43,89 @@
|
||||
#include "arm.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#define TM1_ADDR 0x98400000
|
||||
/****************************************************************************
|
||||
* {re-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
enum timer_reg {
|
||||
COUNTER_TIMER = 0x00,
|
||||
CNTL_TIMER = 0x30,
|
||||
LOAD_TIMER = 0x04,
|
||||
MATCH1_TIMER = 0x08,
|
||||
MATCH2_TIMER = 0x0C,
|
||||
INTR_STATE_TIMER= 0x34,
|
||||
INTR_MASK_TIMER = 0x38,
|
||||
#define TM1_ADDR 0x98400000
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
enum timer_reg
|
||||
{
|
||||
COUNTER_TIMER = 0x00,
|
||||
CNTL_TIMER = 0x30,
|
||||
LOAD_TIMER = 0x04,
|
||||
MATCH1_TIMER = 0x08,
|
||||
MATCH2_TIMER = 0x0C,
|
||||
INTR_STATE_TIMER = 0x34,
|
||||
INTR_MASK_TIMER = 0x38,
|
||||
};
|
||||
|
||||
enum timer_ctl {
|
||||
TM1_ENABLE = (1 << 0),
|
||||
TM1_CLOCK = (1 << 1),
|
||||
TM1_OFENABLE = (1 << 5),
|
||||
TM1_UPDOWN = (1 << 9),
|
||||
enum timer_ctl
|
||||
{
|
||||
TM1_ENABLE = (1 << 0),
|
||||
TM1_CLOCK = (1 << 1),
|
||||
TM1_OFENABLE = (1 << 5),
|
||||
TM1_UPDOWN = (1 << 9),
|
||||
};
|
||||
|
||||
enum timer_int {
|
||||
TM1_MATCH1 = (1 << 0),
|
||||
TM1_MATCH2 = (1 << 1),
|
||||
TM1_OVERFLOW = (1 << 2),
|
||||
enum timer_int
|
||||
{
|
||||
TM1_MATCH1 = (1 << 0),
|
||||
TM1_MATCH2 = (1 << 1),
|
||||
TM1_OVERFLOW = (1 << 2),
|
||||
};
|
||||
|
||||
/************************************************************
|
||||
* Global Functions
|
||||
************************************************************/
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************
|
||||
static uint32_t cmp = BOARD_32KOSC_FREQUENCY / 100;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for
|
||||
* various portions of the systems.
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
************************************************************/
|
||||
|
||||
static uint32_t cmp = BOARD_32KOSC_FREQUENCY / 100;
|
||||
****************************************************************************/
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
uint32_t state;
|
||||
|
||||
/* Process timer interrupt */
|
||||
|
||||
state = getreg32(TM1_ADDR + INTR_STATE_TIMER);
|
||||
state &= ~0x7;
|
||||
putreg32(state, TM1_ADDR + INTR_STATE_TIMER);
|
||||
|
||||
/* Ready for the next interrupt */
|
||||
|
||||
putreg32(cmp, TM1_ADDR + COUNTER_TIMER);
|
||||
|
||||
sched_process_timer();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/************************************************************
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Setup MoxaRT timer 0 to cause system ticks.
|
||||
*
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
* This function is called during start-up to initialize the timer
|
||||
* interrupt.
|
||||
*
|
||||
************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
@ -127,15 +140,18 @@ void up_timer_initialize(void)
|
||||
putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER);
|
||||
|
||||
/* Initialize to a known state */
|
||||
|
||||
putreg32(cmp, TM1_ADDR + COUNTER_TIMER);
|
||||
putreg32(0, TM1_ADDR + LOAD_TIMER);
|
||||
putreg32(0, TM1_ADDR + MATCH1_TIMER);
|
||||
|
||||
/* Attach and enable the timer interrupt */
|
||||
|
||||
irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
|
||||
up_enable_irq(IRQ_SYSTIMER);
|
||||
|
||||
/* Unmask IRQ */
|
||||
|
||||
tmp = getreg32(TM1_ADDR + INTR_MASK_TIMER);
|
||||
tmp &= ~TM1_MATCH1;
|
||||
putreg32(tmp, TM1_ADDR + INTR_MASK_TIMER);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user