From 23ed19c51444369d817b2b809e6a3fb470949fab Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 29 Jul 2015 13:52:23 -0600 Subject: [PATCH] Clean-up from last commit to make sure that all files have BSD licensed header with the correct authors and that the code conforms to the NuttX coding style --- arch/arm/include/moxart/irq.h | 6 +- arch/arm/src/moxart/Make.defs | 3 +- arch/arm/src/moxart/chip.h | 60 ++++++++-------- arch/arm/src/moxart/moxart_16550.c | 40 +++++++++++ arch/arm/src/moxart/moxart_head.S | 43 ++++++++++- arch/arm/src/moxart/moxart_idle.c | 21 ++++-- arch/arm/src/moxart/moxart_irq.c | 79 ++++++++++++-------- arch/arm/src/moxart/moxart_lowputc.S | 9 +-- arch/arm/src/moxart/moxart_systemreset.c | 14 ++-- arch/arm/src/moxart/moxart_timer.c | 92 ++++++++++++++---------- 10 files changed, 240 insertions(+), 127 deletions(-) diff --git a/arch/arm/include/moxart/irq.h b/arch/arm/include/moxart/irq.h index f5a0443612..31c92ed5d3 100644 --- a/arch/arm/include/moxart/irq.h +++ b/arch/arm/include/moxart/irq.h @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/include/moxart/irq.h * - * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************/ -/* This file should never be included directed but, rather, - * only indirectly through nuttx/irq.h +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h */ #ifndef __ARCH_ARM_INCLUDE_MOXART_IRQ_H diff --git a/arch/arm/src/moxart/Make.defs b/arch/arm/src/moxart/Make.defs index 42d1dc7084..1752223114 100644 --- a/arch/arm/src/moxart/Make.defs +++ b/arch/arm/src/moxart/Make.defs @@ -1,5 +1,5 @@ ############################################################################ -# calypso/Make.defs +# arch/arm/src/moxart/Make.defs # # Copyright (C) 2007, 2013-2015 Gregory Nutt. All rights reserved. # Author: Gregory Nutt @@ -56,4 +56,3 @@ CHIP_ASRCS = moxart_lowputc.S CHIP_CSRCS = moxart_16550.c moxart_irq.c moxart_timer.c moxart_idle.c CHIP_CSRCS += moxart_systemreset.c - diff --git a/arch/arm/src/moxart/chip.h b/arch/arm/src/moxart/chip.h index d9a70112b7..e1e57ea5e0 100644 --- a/arch/arm/src/moxart/chip.h +++ b/arch/arm/src/moxart/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/moxa/chip.h + * arch/arm/src/moxart/chip.h * - * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -42,38 +42,38 @@ #include -#define UART0_BASE 0x98200000 +#define UART0_BASE 0x98200000 -#define UART_THR 0x00 -#define UART_LSR 0x14 -#define UART_LSR_THRE 0x20 +#define UART_THR 0x00 +#define UART_LSR 0x14 +#define UART_LSR_THRE 0x20 /* Common UART Registers. Expressed as offsets from the BASE address */ -#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */ -#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */ -#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */ -#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */ -#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */ -#define UART_SCR_OFFS 0x00000010 /* Status Control Register */ -#define UART_LCR_OFFS 0x00000003 /* Line Control Register */ -#define UART_LSR_OFFS 0x00000005 /* Line Status Register */ -#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */ -#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */ -#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */ -#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */ -#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */ -#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */ -#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */ -#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */ -#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */ -#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */ -#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */ -#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */ -#define UART_DIV_HIGH_OFFS 0x00000001 -#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */ -#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */ -#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */ +#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */ +#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */ +#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */ +#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */ +#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */ +#define UART_SCR_OFFS 0x00000010 /* Status Control Register */ +#define UART_LCR_OFFS 0x00000003 /* Line Control Register */ +#define UART_LSR_OFFS 0x00000005 /* Line Status Register */ +#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */ +#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */ +#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */ +#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */ +#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */ +#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */ +#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */ +#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */ +#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */ +#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */ +#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */ +#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */ +#define UART_DIV_HIGH_OFFS 0x00000001 +#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */ +#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */ +#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */ /* UART Settings ************************************************************/ diff --git a/arch/arm/src/moxart/moxart_16550.c b/arch/arm/src/moxart/moxart_16550.c index fb943db0b8..0152b6010f 100644 --- a/arch/arm/src/moxart/moxart_16550.c +++ b/arch/arm/src/moxart/moxart_16550.c @@ -1,3 +1,39 @@ +/****************************************************************************** + * arch/arm/src/moxart/moxart_irq.c + * Driver for MoxaRT IRQ controller + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + /**************************************************************************** * Included Files ****************************************************************************/ @@ -13,6 +49,10 @@ #include "arm.h" #include "up_arch.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset) { return *((volatile uart_addrwidth_t *)base + offset); diff --git a/arch/arm/src/moxart/moxart_head.S b/arch/arm/src/moxart/moxart_head.S index eb83b68516..c67ac08566 100644 --- a/arch/arm/src/moxart/moxart_head.S +++ b/arch/arm/src/moxart/moxart_head.S @@ -1,11 +1,48 @@ +/****************************************************************************** + * arch/arm/src/moxart/moxart_head.S + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + /* Place a branch to the real head at the entry point */ + .section .text.start b __start - /* Exception Vectors like they are needed for the exception vector - indirection of the internal boot ROM. The following section must - be liked to appear at 0x80001c */ + * indirection of the internal boot ROM. The following section must be + * linked to appear at 0x80001c + */ + .section .text.exceptions _undef_instr: b up_vectorundefinsn diff --git a/arch/arm/src/moxart/moxart_idle.c b/arch/arm/src/moxart/moxart_idle.c index ca6d848a79..8659bac501 100644 --- a/arch/arm/src/moxart/moxart_idle.c +++ b/arch/arm/src/moxart/moxart_idle.c @@ -1,7 +1,7 @@ /**************************************************************************** - * arch/arm/src/common/up_idle.c + * arch/arm/src/common/moxart_idle.c * - * Copyright (C) 2007-2009, 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,8 +45,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#define BEGIN_IDLE (*(volatile uint32_t *)0x98700000) &= ~0x10 -#define END_IDLE (*(volatile uint32_t *)0x98700000) |= 0x10 + +#define BEGIN_IDLE (*(volatile uint32_t *)0x98700000) &= ~0x10 +#define END_IDLE (*(volatile uint32_t *)0x98700000) |= 0x10 /**************************************************************************** * Private Data @@ -87,9 +88,15 @@ void up_idle(void) /* Sleep until an interrupt occurs to save power */ BEGIN_IDLE; - //asm("nop\nnop\nmcr p15, 0, r0, c7, c0, 4\n"); - for (i=0; i<0x40000; i++) asm("nop"); + for (i = 0; i < 0x40000; i++) + { + asm("nop"); + } + END_IDLE; - for (i=0; i<0x40000; i++) asm("nop"); + for (i = 0; i < 0x40000; i++) + { + asm("nop"); + } #endif } diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c index f024d53db2..9707767698 100644 --- a/arch/arm/src/moxart/moxart_irq.c +++ b/arch/arm/src/moxart/moxart_irq.c @@ -2,11 +2,8 @@ * arch/arm/src/moxart/moxart_irq.c * Driver for MoxaRT IRQ controller * - * (C) 2010 by Harald Welte - * (C) 2011 by Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -56,15 +53,15 @@ * Pre-processor Definitions ****************************************************************************/ -#define IRQ_ADDR 0x98800000 -#define IRQ_REG(x) (IRQ_ADDR + x) +#define IRQ_ADDR 0x98800000 +#define IRQ_REG(x) (IRQ_ADDR + x) -#define IRQ__SRC 0x00 -#define IRQ__MASK 0x04 -#define IRQ__CLEAR 0x08 -#define IRQ__MODE 0x0C -#define IRQ__LEVEL 0x10 -#define IRQ__STATUS 0x14 +#define IRQ__SRC 0x00 +#define IRQ__MASK 0x04 +#define IRQ__CLEAR 0x08 +#define IRQ__MODE 0x0C +#define IRQ__LEVEL 0x10 +#define IRQ__STATUS 0x14 /**************************************************************************** * Public Data @@ -95,6 +92,7 @@ volatile uint32_t *current_regs; void up_irqinitialize(void) { /* Prepare hardware */ + (*(volatile uint32_t *)0x98100008) &= ~0x9; while (!((*(volatile uint32_t *)0x98100008) & 0x2)) { ; } @@ -104,12 +102,14 @@ void up_irqinitialize(void) (*(volatile uint32_t *)0x98800100) = 0xDFF8003F; /* Mask all interrupts off */ + putreg32(0, IRQ_REG(IRQ__MASK)); putreg32(0, IRQ_REG(IRQ__MASK+0x20)); putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR)); putreg32(0xffffffff, IRQ_REG(IRQ__CLEAR+0x20)); /* Initial trigger mode and level */ + putreg32(0, IRQ_REG(IRQ__MODE)); putreg32(0, IRQ_REG(IRQ__LEVEL)); putreg32(0, IRQ_REG(IRQ__MODE+0x20)); @@ -124,9 +124,13 @@ void up_irqinitialize(void) #if 1 #define REG(x) (*(volatile uint32_t *)(x)) lldbg("\n=============================================================\n"); - lldbg("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004), REG(0x98400000), REG(0x98400008)); - lldbg("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010)); - lldbg("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020)); + lldbg("TM CNTL=%08x INTRS=%08x MASK=%08x LOAD=%08x COUNT=%08x M1=%08x\n", + REG(0x98400030), REG(0x98400034), REG(0x98400038), REG(0x98400004), + REG(0x98400000), REG(0x98400008)); + lldbg("IRQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + REG(0x98800014), REG(0x98800004), REG(0x9880000C), REG(0x98800010)); + lldbg("FIQ STATUS=%08x MASK=%08x MODE=%08x LEVEL=%08x\n", + REG(0x98800034), REG(0x98800024), REG(0x9880002C), REG(0x98800020)); lldbg("=============================================================\n"); #endif @@ -137,10 +141,10 @@ void up_irqinitialize(void) inline void ftintc010_mask_irq(int irq) { - /* - * 0: masked + /* 0: masked * 1: unmasked */ + uint32_t mask; mask = getreg32(IRQ_REG(IRQ__MASK)); @@ -150,10 +154,10 @@ inline void ftintc010_mask_irq(int irq) inline void ftintc010_unmask_irq(int irq) { - /* - * 0: masked + /* 0: masked * 1: unmasked */ + uint32_t mask; mask = getreg32(IRQ_REG(IRQ__MASK)); @@ -167,14 +171,18 @@ inline void ftintc010_set_trig_mode(int irq, int mode) irqmode = getreg32(IRQ_REG(IRQ__MODE)); - /* - * 0: level trigger + /* 0: level trigger * 1: edge trigger */ + if (mode) - irqmode |= (1 << irq); + { + irqmode |= (1 << irq); + } else - irqmode &= ~(1 << irq); + { + irqmode &= ~(1 << irq); + } putreg32(irqmode, IRQ_REG(IRQ__MODE)); } @@ -185,14 +193,18 @@ inline void ftintc010_set_trig_level(int irq, int level) irqlevel = getreg32(IRQ_REG(IRQ__LEVEL)); - /* - * 0: active-high level trigger / rising edge trigger + /* 0: active-high level trigger / rising edge trigger * 1: active-low level trigger / falling edge trigger */ + if (level) - irqlevel |= (1 << irq); + { + irqlevel |= (1 << irq); + } else - irqlevel &= ~(1 << irq); + { + irqlevel &= ~(1 << irq); + } putreg32(irqlevel, IRQ_REG(IRQ__LEVEL)); } @@ -238,7 +250,9 @@ static int ffs(uint32_t word) int t, r; if (word == 0) - return 0; + { + return 0; + } t = r = 1; @@ -273,11 +287,15 @@ void up_decodeirq(uint32_t *regs) uint32_t num, status; /* Detect & deliver the IRQ */ + status = getreg32(IRQ_REG(IRQ__STATUS)); if (!status) - return; + { + return; + } /* Ack IRQ */ + num = ffs(status) - 1; up_ack_irq(num); @@ -285,6 +303,5 @@ void up_decodeirq(uint32_t *regs) current_regs = regs; irq_dispatch(num, regs); - current_regs = NULL; } diff --git a/arch/arm/src/moxart/moxart_lowputc.S b/arch/arm/src/moxart/moxart_lowputc.S index 7ae6f217d5..d57328a17e 100644 --- a/arch/arm/src/moxart/moxart_lowputc.S +++ b/arch/arm/src/moxart/moxart_lowputc.S @@ -1,12 +1,8 @@ /************************************************************************** * moxart/moxart_lowputc.S * - * Copyright (C) 2011 Stefan Richter. All rights reserved. - * Author: Stefan Richter - * - * based on: c5471/c5471_lowputc.S - * Copyright (C) 2007, 2008 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -126,4 +122,3 @@ up_lowputc: /* And return */ mov pc, lr - diff --git a/arch/arm/src/moxart/moxart_systemreset.c b/arch/arm/src/moxart/moxart_systemreset.c index 160e19e517..eeee5456c9 100644 --- a/arch/arm/src/moxart/moxart_systemreset.c +++ b/arch/arm/src/moxart/moxart_systemreset.c @@ -1,9 +1,8 @@ /**************************************************************************** * arch/arm/src/moxart/moxart_systemreset.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * Darcy Gong + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -46,9 +45,13 @@ #include "up_arch.h" -#define FTWDT010_LOAD 0x98500004 +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define FTWDT010_LOAD 0x98500004 #define FTWDT010_RESTART 0x98500008 -#define FTWDT010_CR 0x9850000C +#define FTWDT010_CR 0x9850000C /**************************************************************************** * Public functions @@ -76,7 +79,6 @@ void up_systemreset(void) for (;;); } - /**************************************************************************** * Name: board_reset * diff --git a/arch/arm/src/moxart/moxart_timer.c b/arch/arm/src/moxart/moxart_timer.c index 06e2374054..9998cd3c5f 100644 --- a/arch/arm/src/moxart/moxart_timer.c +++ b/arch/arm/src/moxart/moxart_timer.c @@ -2,11 +2,8 @@ * arch/arm/src/moxart/moxart_timer.c * MoxaRT internal Timer Driver * - * (C) 2010 by Harald Welte - * (C) 2011 by Stefan Richter - * - * This source code is derivated from Osmocom-BB project and was - * relicensed as BSD with permission from original authors. + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Anton D. Kachalov * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -35,7 +32,7 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - **************************************************************************/ + ****************************************************************************/ #include #include @@ -46,73 +43,89 @@ #include "arm.h" #include "up_arch.h" -#define TM1_ADDR 0x98400000 +/**************************************************************************** + * {re-processor Definitions + ****************************************************************************/ -enum timer_reg { - COUNTER_TIMER = 0x00, - CNTL_TIMER = 0x30, - LOAD_TIMER = 0x04, - MATCH1_TIMER = 0x08, - MATCH2_TIMER = 0x0C, - INTR_STATE_TIMER= 0x34, - INTR_MASK_TIMER = 0x38, +#define TM1_ADDR 0x98400000 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +enum timer_reg +{ + COUNTER_TIMER = 0x00, + CNTL_TIMER = 0x30, + LOAD_TIMER = 0x04, + MATCH1_TIMER = 0x08, + MATCH2_TIMER = 0x0C, + INTR_STATE_TIMER = 0x34, + INTR_MASK_TIMER = 0x38, }; -enum timer_ctl { - TM1_ENABLE = (1 << 0), - TM1_CLOCK = (1 << 1), - TM1_OFENABLE = (1 << 5), - TM1_UPDOWN = (1 << 9), +enum timer_ctl +{ + TM1_ENABLE = (1 << 0), + TM1_CLOCK = (1 << 1), + TM1_OFENABLE = (1 << 5), + TM1_UPDOWN = (1 << 9), }; -enum timer_int { - TM1_MATCH1 = (1 << 0), - TM1_MATCH2 = (1 << 1), - TM1_OVERFLOW = (1 << 2), +enum timer_int +{ + TM1_MATCH1 = (1 << 0), + TM1_MATCH2 = (1 << 1), + TM1_OVERFLOW = (1 << 2), }; -/************************************************************ - * Global Functions - ************************************************************/ +/**************************************************************************** + * Private Data + ****************************************************************************/ -/************************************************************ +static uint32_t cmp = BOARD_32KOSC_FREQUENCY / 100; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** * Function: up_timerisr * * Description: - * The timer ISR will perform a variety of services for - * various portions of the systems. + * The timer ISR will perform a variety of services for various portions + * of the systems. * - ************************************************************/ - -static uint32_t cmp = BOARD_32KOSC_FREQUENCY / 100; + ****************************************************************************/ int up_timerisr(int irq, uint32_t *regs) { uint32_t state; /* Process timer interrupt */ + state = getreg32(TM1_ADDR + INTR_STATE_TIMER); state &= ~0x7; putreg32(state, TM1_ADDR + INTR_STATE_TIMER); /* Ready for the next interrupt */ + putreg32(cmp, TM1_ADDR + COUNTER_TIMER); sched_process_timer(); - return 0; } -/************************************************************ +/**************************************************************************** * Function: up_timer_initialize * * Description: * Setup MoxaRT timer 0 to cause system ticks. * - * This function is called during start-up to initialize - * the timer interrupt. + * This function is called during start-up to initialize the timer + * interrupt. * - ************************************************************/ + ****************************************************************************/ void up_timer_initialize(void) { @@ -127,15 +140,18 @@ void up_timer_initialize(void) putreg32(0x1ff, TM1_ADDR + INTR_MASK_TIMER); /* Initialize to a known state */ + putreg32(cmp, TM1_ADDR + COUNTER_TIMER); putreg32(0, TM1_ADDR + LOAD_TIMER); putreg32(0, TM1_ADDR + MATCH1_TIMER); /* Attach and enable the timer interrupt */ + irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr); up_enable_irq(IRQ_SYSTIMER); /* Unmask IRQ */ + tmp = getreg32(TM1_ADDR + INTR_MASK_TIMER); tmp &= ~TM1_MATCH1; putreg32(tmp, TM1_ADDR + INTR_MASK_TIMER);