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Fix an error introduced into stm32_pwr_enablebkp(). That function must preserve the previous state of backup domain access on return.

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This commit is contained in:
Gregory Nutt 2015-04-18 07:31:20 -06:00
parent 9f0a9824bc
commit 244a30b6a9
7 changed files with 56 additions and 130 deletions
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6
arch/arm/src/stm32/stm32_bbsram.c
View File

@ -246,9 +246,9 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
*
****************************************************************************/
static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_unlock(void)
{
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
}
/****************************************************************************
@ -268,7 +268,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
}
/****************************************************************************

11
arch/arm/src/stm32/stm32_lse.c
View File

@ -74,12 +74,14 @@
void stm32_rcc_enablelse(void)
{
bool bkpenabled;
/* The LSE is in the RTC domain and write access is denied to this domain
* after reset, you have to enable write access using DBP bit in the PWR CR
* register before to configuring the LSE.
*/
stm32_pwr_enablebkp(true);
bkpenabled = stm32_pwr_enablebkp(true);
#if defined(CONFIG_STM32_STM32L15XX)
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON bit
@ -111,5 +113,10 @@ void stm32_rcc_enablelse(void)
#endif
stm32_pwr_enablebkp(false);
/* Disable backup domain access if it was disabled on entry */
if (!bkpenabled)
{
(void)stm32_pwr_enablebkp(false);
}
}

33
arch/arm/src/stm32/stm32_pwr.c
View File

@ -88,28 +88,43 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
* Input Parameters:
* protect - sets the write protections
*
* Returned Values:
* None
* Returned Value:
* True: The backup domain was previously writable.
*
************************************************************************************/
void stm32_pwr_enablebkp(bool writable)
bool stm32_pwr_enablebkp(bool writable)
{
uint16_t regval;
bool waswritable;
/* Enable or disable the ability to write*/
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
regval &= ~PWR_CR_DBP;
regval |= writable ? PWR_CR_DBP : 0;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
waswritable = ((regval & PWR_CR_DBP) != 0);
if (writable)
/* Enable or disable the ability to write */
if (waswritable && !writable)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
else if (!waswritable && writable)
{
/* Enable backup domain access */
regval |= PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
/* Enable does not happen right away */
up_udelay(4);
}
return waswritable;
}
/************************************************************************************

6
arch/arm/src/stm32/stm32_pwr.h
View File

@ -76,12 +76,12 @@ extern "C"
* Input Parameters:
* writable - sets the write protections
*
* Returned Values:
* None
* Returned Value:
* True: The backup domain was previously writable.
*
************************************************************************************/
void stm32_pwr_enablebkp(bool writable);
bool stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg

12
arch/arm/src/stm32/stm32_rtcc.c
View File

@ -253,7 +253,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@ -292,7 +292,7 @@ static inline void rtc_wprlock(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
}
/************************************************************************************
@ -627,7 +627,7 @@ int up_rtcinitialize(void)
regval = getreg32(RTC_MAGIC_REG);
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@ -705,7 +705,7 @@ int up_rtcinitialize(void)
}
}
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the RTC
@ -756,7 +756,7 @@ int up_rtcinitialize(void)
* backup data registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
@ -776,7 +776,7 @@ int up_rtcinitialize(void)
* data registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
if (ret != OK && nretry > 0)
{

4
arch/arm/src/stm32/stm32_rtcounter.c
View File

@ -370,7 +370,7 @@ int up_rtcinitialize(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(true);
(void)stm32_pwr_enablebkp(true);
/* Set access to the peripheral, enable the backup domain (BKP) and the lower
* power external 32,768Hz (Low-Speed External, LSE) oscillator. Configure the
@ -421,7 +421,7 @@ int up_rtcinitialize(void)
* registers and backup SRAM).
*/
stm32_pwr_enablebkp(false);
(void)stm32_pwr_enablebkp(false);
return OK;
}

114
configs/cloudctrl/nsh/defconfig
View File

@ -129,6 +129,7 @@ CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set
# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW is not set
# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set
CONFIG_ARMV7M_HAVE_STACKCHECK=y
# CONFIG_ARMV7M_STACKCHECK is not set
# CONFIG_ARMV7M_ITMSYSLOG is not set
# CONFIG_NET_MULTICAST is not set
@ -334,6 +335,7 @@ CONFIG_STM32_USART2=y
# CONFIG_STM32_IWDG is not set
# CONFIG_STM32_WWDG is not set
CONFIG_STM32_SPI=y
# CONFIG_STM32_NOEXT_VECTORS is not set
#
# Alternate Pin Mapping
@ -363,6 +365,7 @@ CONFIG_STM32_USART=y
#
# CONFIG_STM32_SPI_INTERRUPTS is not set
# CONFIG_STM32_SPI_DMA is not set
CONFIG_STM32_HAVE_RTC_COUNTER=y
# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set
CONFIG_RTC_LSECLOCK=y
# CONFIG_RTC_LSICLOCK is not set
@ -486,6 +489,7 @@ CONFIG_NSH_MMCSDSPIPORTNO=1
CONFIG_LIB_BOARDCTL=y
# CONFIG_BOARDCTL_TSCTEST is not set
# CONFIG_BOARDCTL_ADCTEST is not set
# CONFIG_BOARDCTL_PWMTEST is not set
# CONFIG_BOARDCTL_GRAPHICS is not set
# CONFIG_BOARDCTL_IOCTL is not set
@ -716,6 +720,7 @@ CONFIG_ARCH_HAVE_USART2=y
CONFIG_USART2_ISUART=y
CONFIG_MCU_SERIAL=y
CONFIG_STANDARD_SERIAL=y
CONFIG_SERIAL_NPOLLWAITERS=2
# CONFIG_SERIAL_IFLOWCONTROL is not set
# CONFIG_SERIAL_OFLOWCONTROL is not set
CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y
@ -960,6 +965,7 @@ CONFIG_LIBC_TMPDIR="/tmp"
CONFIG_LIBC_MAX_TMPFILE=32
CONFIG_ARCH_LOWPUTC=y
# CONFIG_LIBC_LOCALTIME is not set
# CONFIG_TIME_EXTENDED is not set
CONFIG_LIB_SENDFILE_BUFSIZE=512
# CONFIG_ARCH_ROMGETC is not set
# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set
@ -1027,10 +1033,10 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_NXTEXT is not set
# CONFIG_EXAMPLES_OSTEST is not set
# CONFIG_EXAMPLES_PIPE is not set
# CONFIG_EXAMPLES_PPPD is not set
# CONFIG_EXAMPLES_POSIXSPAWN is not set
# CONFIG_EXAMPLES_QENCODER is not set
# CONFIG_EXAMPLES_RGMP is not set
# CONFIG_EXAMPLES_ROMFS is not set
# CONFIG_EXAMPLES_SENDMAIL is not set
# CONFIG_EXAMPLES_SERIALBLASTER is not set
# CONFIG_EXAMPLES_SERIALRX is not set
@ -1049,6 +1055,7 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_EXAMPLES_USBSERIAL is not set
# CONFIG_EXAMPLES_USBTERM is not set
# CONFIG_EXAMPLES_WATCHDOG is not set
# CONFIG_EXAMPLES_XMLRPC is not set
#
# Graphics Support
@ -1074,6 +1081,7 @@ CONFIG_EXAMPLES_NSH=y
# CONFIG_NETUTILS_CODECS is not set
# CONFIG_NETUTILS_DHCPD is not set
# CONFIG_NETUTILS_FTPC is not set
# CONFIG_NETUTILS_FTPD is not set
# CONFIG_NETUTILS_JSON is not set
CONFIG_NETUTILS_DNSCLIENT=y
CONFIG_NETUTILS_DNSCLIENT_IPv4=y
@ -1231,123 +1239,19 @@ CONFIG_NSH_IOBUFFER_SIZE=512
#
# System Libraries and NSH Add-Ons
#
#
# Custom Free Memory Command
#
# CONFIG_SYSTEM_FREE is not set
#
# EMACS-like Command Line Editor
#
# CONFIG_SYSTEM_CLE is not set
#
# CU Minimal Terminal
#
# CONFIG_SYSTEM_CUTERM is not set
#
# FLASH Program Installation
#
# CONFIG_SYSTEM_INSTALL is not set
#
# FLASH Erase-all Command
#
#
# Intel HEX to binary conversion
#
# CONFIG_SYSTEM_HEX2BIN is not set
#
# I2C tool
#
#
# INI File Parser
#
# CONFIG_SYSTEM_INIFILE is not set
#
# NxPlayer media player library / command Line
#
#
# RAM test
#
# CONFIG_SYSTEM_RAMTEST is not set
#
# readline()
#
CONFIG_SYSTEM_READLINE=y
CONFIG_READLINE_ECHO=y
#
# P-Code Support
#
#
# PHY Tool
#
#
# Power Off
#
# CONFIG_SYSTEM_POWEROFF is not set
#
# RAMTRON
#
# CONFIG_SYSTEM_RAMTRON is not set
#
# SD Card
#
# CONFIG_SYSTEM_SDCARD is not set
#
# Sudoku
#
# CONFIG_SYSTEM_SUDOKU is not set
#
# Sysinfo
#
# CONFIG_SYSTEM_SYSINFO is not set
#
# Temperature
#
#
# VI Work-Alike Editor
#
# CONFIG_SYSTEM_VI is not set
#
# Stack Monitor
#
#
# USB CDC/ACM Device Commands
#
#
# USB Composite Device Commands
#
#
# USB Mass Storage Device Commands
#
#
# USB Monitor
#
#
# Zmodem Commands
#
# CONFIG_SYSTEM_ZMODEM is not set