SAML21: Clean up a few more compilation issues
This commit is contained in:
Gregory Nutt
parent
a0b9e26aba
commit
2478184c22
@ -79,15 +79,16 @@
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/* Status register */
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#define GCLK_SYNCHBUSY_SWRST (1 << 0) /* Bit 0: SWRST synchronization busy */
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#define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */
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#define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */
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#define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */
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#define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */
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#define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */
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#define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */
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#define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */
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#define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */
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#define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
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#define GCLK_SYNCHBUSY_GENCTRL(n) (1 << ((n) + 2)) /* Bit n+2: Generator control n busy */
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# define GCLK_SYNCHBUSY_GENCTRL0 (1 << 2) /* Bit 2: Generator control 0 busy */
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# define GCLK_SYNCHBUSY_GENCTRL1 (1 << 3) /* Bit 3: Generator control 1 busy */
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# define GCLK_SYNCHBUSY_GENCTRL2 (1 << 4) /* Bit 4: Generator control 2 busy */
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# define GCLK_SYNCHBUSY_GENCTRL3 (1 << 5) /* Bit 5: Generator control 3 busy */
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# define GCLK_SYNCHBUSY_GENCTRL4 (1 << 6) /* Bit 6: Generator control 4 busy */
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# define GCLK_SYNCHBUSY_GENCTRL5 (1 << 7) /* Bit 7: Generator control 5 busy */
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# define GCLK_SYNCHBUSY_GENCTRL6 (1 << 8) /* Bit 8: Generator control 6 busy */
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# define GCLK_SYNCHBUSY_GENCTRL7 (1 << 9) /* Bit 9: Generator control 7 busy */
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# define GCLK_SYNCHBUSY_GENCTRL8 (1 << 10) /* Bit 10: Generator control 8 busy */
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/* General clock generator n */
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@ -63,22 +63,31 @@
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* Name: sam_gclck_waitsyncbusy
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*
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* Description:
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* What until the SYNCBUSY bit is cleared. This bit is cleared when the
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* synchronization of registers between the clock domains is complete.
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* This bit is set when the synchronization of registers between clock
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* domains is started.
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* What until the SYNCBUSY bit is cleared. The SYNCBUSY bit was set when
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* the synchronization of registers between clock domains is started. The
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* SYNCBUSY bit is cleared when the synchronization of registers between
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* the clock domains is complete.
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*
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* Input Parameters:
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* None
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* glck - GCLK clock index
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void sam_gclck_waitsyncbusy(void)
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static void sam_gclck_waitsyncbusy(uint8_t gclk)
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{
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#if defined(CONFIG_ARCH_FAMILY_SAMD20)
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while ((getreg8(SAM_GCLK_STATUS) & GCLK_STATUS_SYNCBUSY) != 0);
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#elif defined(CONFIG_ARCH_FAMILY_SAML21)
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uintptr_t gclkbit = GCLK_SYNCHBUSY_GENCTRL(gclk);
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while ((getreg8(SAM_GCLK_SYNCHBUSY) & gclkbit) != 0);
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#else
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# error Unrecognized SAMD/L architecture
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#endif
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}
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/****************************************************************************
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@ -174,7 +183,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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/* Wait for synchronization */
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sam_gclck_waitsyncbusy();
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sam_gclck_waitsyncbusy(config->gclk);
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/* Select the generator */
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@ -183,7 +192,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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/* Wait for synchronization */
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sam_gclck_waitsyncbusy();
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sam_gclck_waitsyncbusy(config->gclk);
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/* Write the new generator configuration */
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@ -191,7 +200,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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/* Wait for synchronization */
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sam_gclck_waitsyncbusy();
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sam_gclck_waitsyncbusy(config->gclk);
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/* Enable the clock generator */
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@ -200,7 +209,7 @@ void sam_gclk_config(FAR const struct sam_gclkconfig_s *config)
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/* Wait for synchronization */
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sam_gclck_waitsyncbusy();
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sam_gclck_waitsyncbusy(config->gclk);
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}
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/****************************************************************************
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@ -63,6 +63,8 @@
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* This structure describes the configuration of one GCLK */
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struct sam_gclkconfig_s
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@ -78,8 +80,6 @@ struct sam_gclkconfig_s
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* Inline Functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/****************************************************************************
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* Public Data
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****************************************************************************/
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@ -787,7 +787,7 @@ static inline void sam_osc16m_config(void)
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* BOARD_DFLL48M_FINEVALUE - Value
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*
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* Closed loop mode only:
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* BOARD_DFLL48M_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions
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* BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
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* BOARD_DFLL48M_MULTIPLIER - Value
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* BOARD_DFLL48M_MAXCOARSESTEP - Value
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* BOARD_DFLL48M_MAXFINESTEP - Value
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@ -936,7 +936,7 @@ static inline void sam_dfll48m_enable(void)
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* Enable DFLL reference clock if in closed loop mode.
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* Depends on:
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*
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* BOARD_DFLL48M_SRCGCLKGEN - See GCLK_CLKCTRL_GEN* definitions
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* BOARD_DFLL48M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
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*
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* Input Parameters:
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* None
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@ -950,37 +950,7 @@ static inline void sam_dfll48m_enable(void)
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!defined(BOARD_DFLL48M_OPENLOOP)
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static inline void sam_dfll48m_refclk(void)
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{
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uint16_t regval;
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/* Disabled the DFLL reference clock */
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regval = GCLK_CLKCTRL_ID_DFLL48M;
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Wait for the clock to become disabled */
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) != 0);
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/* Select the configured clock generator as the source for the DFLL
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* reference clock.
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*
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* NOTE: We could enable write lock here to prevent further modification
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*/
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regval = (BOARD_DFLL48M_SRCGCLKGEN | GCLK_CLKCTRL_ID_DFLL48M);
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* Enable the DFLL reference clock */
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regval |= GCLK_CLKCTRL_CLKEN;
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putreg16(regval, SAM_GCLK_CLKCTRL);
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/* The CLKCTRL.CLKEN bit must be synchronized to the generic clock domain.
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* CLKCTRL.CLKEN will continue to read as its previous state until the
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* synchronization is complete.
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*/
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while ((getreg16(SAM_GCLK_CLKCTRL) & GCLK_CLKCTRL_CLKEN) == 0);
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sam_gclk_chan_enable(GCLK_CHAN_DFLL48M_REF, BOARD_DFLL48M_REFCLK_CLKGEN);
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}
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#else
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# define sam_dfll48m_refclk()
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@ -1123,9 +1093,9 @@ static inline void sam_fdpll96m_config(void)
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*
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* BOARD_FDPLL96M_ENABLE - Boolean (defined / not defined)
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* BOARD_FDPLL96M_REFCLK - See OSCCTRL_DPLLCTRLB_REFLCK_* definitions
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* BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_CLKCTRL_GEN* definitions
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* BOARD_FDPLL96M_REFCLK_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
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* BOARD_FDPLL96M_LOCKTIME_ENABLE - Boolean (defined / not defined)
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* BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_CLKCTRL_GEN* definitions
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* BOARD_FDPLL96M_LOCKTIME_CLKGEN - See GCLK_PCHCTRL_GEN* definitions
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*
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* Input Parameters:
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* None
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