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More lpc17xx port files

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2735 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-08 03:16:46 +00:00
parent 2b120a3269
commit 247dc3181a
10 changed files with 1894 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/src/lpc17xx/Make.defs
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@ -51,7 +51,7 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
# Required LPC17xx files
CHIP_ASRCS =
CHIP_CSRCS = lpc17_irq.c lpc17_gpio.c lpc17_start.c
CHIP_CSRCS = lpc17_allocateheap.c lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_gpioint.c lpc17_serial.c lpc17_start.c
#CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpioirq.c \
# lpc17_irq.c lpc17_lowputc.c lpc17_gpio.c lpc17_serial.c \
# lpc17_start.c lpc17_timerisr.c

22
arch/arm/src/lpc17xx/chip.h
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@ -51,6 +51,8 @@
#if defined(CONFIG_ARCH_CHIP_LPC1769) || defined(CONFIG_ARCH_CHIP_LPC1768)
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -61,6 +63,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1767)
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
@ -71,6 +75,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1766)
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -81,6 +87,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1765)
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -91,6 +99,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1764)
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
@ -101,6 +111,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1759)
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -111,6 +123,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1758)
# define LPC17_FLASH_SIZE (512*1024) /* 512Kb */
# define LPC17_SRAM_SIZE (64*1024) /* 64Kb */
# define LPC17_HAVE_BANK0 1 /* Have AHB SRAM bank 0 */
# define LPC17_HAVE_BANK1 1 /* Have AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -121,6 +135,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1756)
# define LPC17_FLASH_SIZE (256*1024) /* 256Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -131,6 +147,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1754)
# define LPC17_FLASH_SIZE (128*1024) /* 128Kb */
# define LPC17_SRAM_SIZE (32*1024) /* 32Kb */
# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 1 /* One USB host controller */
# define LPC17_NUSBOTG 1 /* One USB OTG controller */
@ -141,6 +159,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1752)
# define LPC17_FLASH_SIZE (64*1024) /* 65Kb */
# define LPC17_SRAM_SIZE (16*1024) /* 16Kb */
# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */
@ -151,6 +171,8 @@
#elif defined(CONFIG_ARCH_CHIP_LPC1751)
# define LPC17_FLASH_SIZE (32*1024) /* 32Kb */
# define LPC17_SRAM_SIZE (8*1024) /* 8Kb */
# undef LPC17_HAVE_BANK0 1 /* No AHB SRAM bank 0 */
# undef LPC17_HAVE_BANK1 1 /* No AHB SRAM bank 1 */
# define LPC17_NETHCONTROLLERS 0 /* No Ethernet controller */
# define LPC17_NUSBHOST 0 /* No USB host controller */
# define LPC17_NUSBOTG 0 /* No USB OTG controller */

132
arch/arm/src/lpc17xx/lpc17_allocateheap.c Executable file
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@ -0,0 +1,132 @@
/****************************************************************************
* arch/arm/src/lpc17xx/lpc17_allocateheap.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include "chip.h"
#include "up_arch.h"
#include "up_internal.h"
/****************************************************************************
* Private Definitions
****************************************************************************/
#if CONFIG_DRAM_END > (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
# error "CONFIG_DRAM_END is beyond the end of CPU SRAM"
# undef CONFIG_DRAM_END
# define CONFIG_DRAM_END (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
#elif CONFIG_DRAM_END < (LPC17_SRAM_BASE+LPC17_SRAM_SIZE)
# warning "CONFIG_DRAM_END is before end of CPU SRAM... not all of CPU SRAM used"
#endif
#ifdef LPC17_HAVE_BANK0
# if CONFIG_MM_REGIONS < 2
# warning "CONFIG_MM_REGIONS < 2: AHB SRAM Bank0 not included in HEAP"
# endif
#else
# if CONFIG_MM_REGIONS > 1
# warning "CONFIG_MM_REGIONS > 1: This MCH has no AHB SRAM Bank0"
# endif
#endif
#ifdef LPC17_HAVE_BANK1
# if CONFIG_MM_REGIONS < 3
# warning "CONFIG_MM_REGIONS < 3: AHB SRAM Bank1 not included in HEAP"
# endif
#else
# if CONFIG_MM_REGIONS > 2
# warning "CONFIG_MM_REGIONS > 2: This MCH has no AHB SRAM Bank1"
# endif
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* The heap may be statically allocated by
* defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE. If these
* are not defined, then this function will be called to
* dynamically set aside the heap region.
*
****************************************************************************/
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
up_ledon(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_heapbase;
*heap_size = CONFIG_DRAM_END - g_heapbase;
}
/************************************************************************
* Name: up_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
************************************************************************/
#if CONFIG_MM_REGIONS > 1
void up_addregion(void)
{
mm_addregion((FAR void*)LPC17_HAVE_BANK0, 16*1024);
#if CONFIG_MM_REGIONS > 2
mm_addregion((FAR void*)LPC17_HAVE_BANK1, 16*1024);
#endif
}
#endif

2
arch/arm/src/lpc17xx/lpc17_internal.h
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@ -331,7 +331,7 @@
#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28)
#define GPIO_TXMCLK (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
#define GPIO_MAT2p1_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
#define GPIO_UART3_RXD (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
/************************************************************************************
* Public Types

293
arch/arm/src/lpc17xx/lpc17_lowputc.c Executable file
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@ -0,0 +1,293 @@
/**************************************************************************
* arch/arm/src/lpc17xx/lpc17_lowputc.c
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
**************************************************************************/
/**************************************************************************
* Included Files
**************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include <arch/board/board.h>
#include "up_internal.h"
#include "up_arch.h"
#include "lpc17_internal.h"
#include "lpc17_uart.h"
#include "lpc17_serial.h"
/**************************************************************************
* Private Definitions
**************************************************************************/
/* Baud calculations
BAUD = PCLK / (16 x (256 x DLM + DLL) x (1 + DIVADDVAL/MULVAL))
Where PCLK is the peripheral clock, DLM and DLL are the standard
UART baud rate divider registers, and DIVADDVAL and MULVAL are UART
fractional baud rate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 <= MULVAL <= 15
2. 0 <= DIVADDVAL <= 14
3. DIVADDVAL < MULVAL
The peripheral clock is controlled by:
#define SYSCON_PCLKSET_CCLK4 PCLK_peripheral = CCLK/4
#define SYSCON_PCLKSET_CCLK PCLK_peripheral = CCLK
#define SYSCON_PCLKSET_CCLK2 PCLK_peripheral = CCLK/2
#define SYSCON_PCLKSET_CCLK6 PCLK_peripheral = CCLK/8 (except CAN1, CAN2, and CAN)
#define SYSCON_PCLKSET_CCLK8 PCLK_peripheral = CCLK/6 (CAN1, CAN2, and CAN)
*/
/**************************************************************************
* Private Types
**************************************************************************/
/**************************************************************************
* Private Function Prototypes
**************************************************************************/
/**************************************************************************
* Global Variables
**************************************************************************/
/**************************************************************************
* Private Variables
**************************************************************************/
/**************************************************************************
* Private Functions
**************************************************************************/
/**************************************************************************
* Public Functions
**************************************************************************/
/**************************************************************************
* Name: up_lowputc
*
* Description:
* Output one byte on the serial console
*
**************************************************************************/
void up_lowputc(char ch)
{
/* Wait for the transmitter to be available */
while ((getreg32(CONSOLE_BASE+LPC17_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
/* Send the character */
putreg32((uint32_t)ch, CONSOLE_BASE+LPC17_UART_THR_OFFSET);
}
/**************************************************************************
* Name: lpc17_lowsetup
*
* Description:
* This performs basic initialization of the UART used for the serial
* console. Its purpose is to get the console output availabe as soon
* as possible.
*
* The UART0/2/3 peripherals are configured using the following registers:
* 1. Power: In the PCONP register, set bits PCUART0/1/2/3.
* On reset, UART0 and UART 1 are enabled (PCUART0 = 1 and PCUART1 = 1)
* and UART2/3 are disabled (PCUART1 = 0 and PCUART3 = 0).
* 2. Peripheral clock: In the PCLKSEL0 register, select PCLK_UART0 and
* PCLK_UART1; in the PCLKSEL1 register, select PCLK_UART2 and PCLK_UART3.
* 3. Baud rate: In the LCR register, set bit DLAB = 1. This enables access
* to registers DLL and DLM for setting the baud rate. Also, if needed,
* set the fractional baud rate in the fractional divider
* 4. UART FIFO: Use bit FIFO enable (bit 0) in FCR register to
* enable FIFO.
* 5. Pins: Select UART pins through the PINSEL registers and pin modes
* through the PINMODE registers. UART receive pins should not have
* pull-down resistors enabled.
* 6. Interrupts: To enable UART interrupts set bit DLAB = 0 in the LCRF
* register. This enables access to IER. Interrupts are enabled
* in the NVIC using the appropriate Interrupt Set Enable register.
* 7. DMA: UART transmit and receive functions can operate with the
* GPDMA controller.
*
**************************************************************************/
void lpc17_lowsetup(void)
{
#if 0
uint32_t regval;
/* Step 1: Enable power for all selected UARTs */
regval = getreg32(LPC17_SYSCON_PCONP);
regval &= ~(SYSCON_PCONP_PCUART0|SYSCON_PCONP_PCUART1|SYSCON_PCONP_PCUART2|SYSCON_PCONP_PCUART3)
#ifdef CONFIG_LPC17_UART0
regval |= SYSCON_PCONP_PCUART0;
#endif
#ifdef CONFIG_LPC17_UART1
regval |= SYSCON_PCONP_PCUART1;
#endif
#ifdef CONFIG_LPC17_UART2
regval |= SYSCON_PCONP_PCUART2;
#endif
#ifdef CONFIG_LPC17_UART3
regval |= SYSCON_PCONP_PCUART3;
#endif
putreg32(regval, LPC17_SYSCON_PCONP);
/* Step 2: Enable peripheral clocking for all selected UARTs */
#define SYSCON_PCLKSET_MASK (3)
#define SYSCON_PCLKSEL0_UART0_SHIFT (6) /* Bits 6-7: Peripheral clock UART0 */
#define SYSCON_PCLKSEL0_UART0_MASK (3 << SYSCON_PCLKSEL0_UART0_MASK)
#define SYSCON_PCLKSEL0_UART1_SHIFT (8) /* Bits 8-9: Peripheral clock UART1 */
#define SYSCON_PCLKSEL0_UART1_MASK (3 << SYSCON_PCLKSEL0_UART1_SHIFT)
#define SYSCON_PCLKSEL1_UART2_SHIFT (16) /* Bits 16-17: Peripheral clock UART2 */
#define SYSCON_PCLKSEL1_UART2_MASK (3 << SYSCON_PCLKSEL1_UART2_SHIFT)
#define SYSCON_PCLKSEL1_UART3_SHIFT (18) /* Bits 18-19: Peripheral clock UART3 */
#define SYSCON_PCLKSEL1_UART3_MASK (3 << SYSCON_PCLKSEL1_UART3_SHIFT)
/* Configure UART pins for all selected UARTs */
#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN3
#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
#define GPIO_UART1_DTR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN20)
#define GPIO_UART1_RI_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN21)
#define GPIO_UART1_RTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN22)
#define GPIO_UART1_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0)
#define GPIO_UART1_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN1)
#define GPIO_UART1_CTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN2)
#define GPIO_UART1_DCD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN3)
#define GPIO_UART1_DSR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN4)
#define GPIO_UART1_DTR_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN5)
#define GPIO_UART1_RI_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN6)
#define GPIO_UART1_RTS_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN7)
#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
#define GPIO_UART2_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
#define GPIO_UART2_TXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN8)
#define GPIO_UART2_RXD_2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN9)
#define GPIO_UART3_TXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN0)
#define GPIO_UART3_RXD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
#define GPIO_UART3_TXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN25)
#define GPIO_UART3_RXD_2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN26)
#define GPIO_UART3_TXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN28)
#define GPIO_UART3_RXD_3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT4 | GPIO_PIN29)
#ifdef CONFIG_LPC17_UART0
(void)lpc17_configgpio(GPIO_UART0_RXD);
(void)lpc17_configgpio(GPIO_UART0_TXD);
(void)lpc17_configgpio(GPIO_UART0_CTS);
(void)lpc17_configgpio(GPIO_UART0_RTS);
#endif
#ifdef CONFIG_LPC17_UART1
(void)lpc17_configgpio(GPIO_UART1_RXD);
(void)lpc17_configgpio(GPIO_UART1_TXD);
(void)lpc17_configgpio(GPIO_UART1_CTS);
(void)lpc17_configgpio(GPIO_UART1_RTS);
#endif
#ifdef CONFIG_LPC17_UART2
(void)lpc17_configgpio(GPIO_UART2_RXD);
(void)lpc17_configgpio(GPIO_UART2_TXD);
(void)lpc17_configgpio(GPIO_UART2_CTS);
(void)lpc17_configgpio(GPIO_UART2_RTS);
#endif
#ifdef CONFIG_LPC17_UART3
(void)lpc17_configgpio(GPIO_UART3_RXD);
(void)lpc17_configgpio(GPIO_UART3_TXD);
(void)lpc17_configgpio(GPIO_UART3_CTS);
(void)lpc17_configgpio(GPIO_UART3_RTS);
#endif
#ifdef GPIO_CONSOLE_RXD
#endif
#ifdef GPIO_CONSOLE_TXD
(void)lpc17_configgpio(GPIO_CONSOLE_TXD);
#endif
#ifdef GPIO_CONSOLE_CTS
(void)lpc17_configgpio(GPIO_CONSOLE_CTS);
#endif
#ifdef GPIO_CONSOLE_RTS
(void)lpc17_configgpio(GPIO_CONSOLE_RTS);
#endif
/* Configure the console (only) */
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Reset and disable receiver and transmitter */
putreg32((UART_CR_RSTRX|UART_CR_RSTTX|UART_CR_RXDIS|UART_CR_TXDIS),
CONSOLE_BASE+LPC17_UART_CR_OFFSET);
/* Disable all interrupts */
putreg32(0xffffffff, CONSOLE_BASE+LPC17_UART_IDR_OFFSET);
/* Set up the mode register */
putreg32(MR_VALUE, CONSOLE_BASE+LPC17_UART_MR_OFFSET);
/* Configure the console baud */
putreg32(((LPC17_MCK_FREQUENCY + (LPC17_CONSOLE_BAUD << 3))/(LPC17_CONSOLE_BAUD << 4)),
CONSOLE_BASE+LPC17_UART_BRGR_OFFSET);
/* Enable receiver & transmitter */
putreg32((UART_CR_RXEN|UART_CR_TXEN),
CONSOLE_BASE+LPC17_UART_CR_OFFSET);
#endif
#endif /* 0 */
}

1066
arch/arm/src/lpc17xx/lpc17_serial.c Executable file
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327
arch/arm/src/lpc17xx/lpc17_serial.h Executable file
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@ -0,0 +1,327 @@
/************************************************************************************
* arch/arm/src/lpc17xx/lpc17_serial.h
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H
#define __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration *********************************************************************/
/* Is there a serial console? It could be on any UARTn, n=0,1,2,3 */
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART0)
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART1)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART2_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART2)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#elif defined(CONFIG_UART3_SERIAL_CONSOLE) && defined(CONFIG_LPC17_UART3)
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# define HAVE_CONSOLE 1
#else
# undef CONFIG_UART0_SERIAL_CONSOLE
# undef CONFIG_UART1_SERIAL_CONSOLE
# undef CONFIG_UART2_SERIAL_CONSOLE
# undef CONFIG_UART3_SERIAL_CONSOLE
# undef HAVE_CONSOLE
#endif
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC17_UART0_BASE
# define CONSOLE_BAUD CONFIG_UART0_BAUD
# define CONSOLE_BITS CONFIG_UART0_BITS
# define CONSOLE_PARITY CONFIG_UART0_PARITY
# define CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC17_UART1_BASE
# define CONSOLE_BAUD CONFIG_UART1_BAUD
# define CONSOLE_BITS CONFIG_UART1_BITS
# define CONSOLE_PARITY CONFIG_UART1_PARITY
# define CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC17_UART2_BASE
# define CONSOLE_BAUD CONFIG_UART2_BAUD
# define CONSOLE_BITS CONFIG_UART2_BITS
# define CONSOLE_PARITY CONFIG_UART2_PARITY
# define CONSOLE_2STOP CONFIG_UART2_2STOP
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
# define CONSOLE_BASE LPC17_UART3_BASE
# define CONSOLE_BAUD CONFIG_UART3_BAUD
# define CONSOLE_BITS CONFIG_UART3_BITS
# define CONSOLE_PARITY CONFIG_UART3_PARITY
# define CONSOLE_2STOP CONFIG_UART3_2STOP
#else
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
/* Get word length setting for the console UART and UART0-3 */
#if CONSOLE_BITS == 5
# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
#elif CONSOLE_BITS == 6
# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
#elif CONSOLE_BITS == 7
# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
#elif CONSOLE_BITS == 8
# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
#else
# error "Invalid CONFIG_UARTn_BITS setting for console "
#endif
#ifdef CONFIG_LPC17_UART0
# if CONFIG_UART0_BITS == 5
# define UART0_LCR_WLS UART_LCR_WLS_5BIT
# elif CONFIG_UART0_BITS == 6
# define UART0_LCR_WLS UART_LCR_WLS_6BIT
# elif CONFIG_UART0_BITS == 7
# define UART0_LCR_WLS UART_LCR_WLS_7BIT
# elif CONFIG_UART0_BITS == 8
# define UART0_LCR_WLS UART_LCR_WLS_8BIT
# else
# error "Invalid CONFIG_UARTn_BITS setting for UART0 "
# endif
#endif
#ifdef CONFIG_LPC17_UART1
# if CONFIG_UART1_BITS == 5
# define UART1_LCR_WLS UART_LCR_WLS_5BIT
# elif CONFIG_UART1_BITS == 6
# define UART1_LCR_WLS UART_LCR_WLS_6BIT
# elif CONFIG_UART1_BITS == 7
# define UART1_LCR_WLS UART_LCR_WLS_7BIT
# elif CONFIG_UART1_BITS == 8
# define UART1_LCR_WLS UART_LCR_WLS_8BIT
# else
# error "Invalid CONFIG_UARTn_BITS setting for UART1 "
# endif
#endif
#ifdef CONFIG_LPC17_UART2
# if CONFIG_UART2_BITS == 5
# define UART2_LCR_WLS UART_LCR_WLS_5BIT
# elif CONFIG_UART2_BITS == 6
# define UART2_LCR_WLS UART_LCR_WLS_6BIT
# elif CONFIG_UART2_BITS == 7
# define UART2_LCR_WLS UART_LCR_WLS_7BIT
# elif CONFIG_UART2_BITS == 8
# define UART2_LCR_WLS UART_LCR_WLS_8BIT
# else
# error "Invalid CONFIG_UARTn_BITS setting for UART2 "
# endif
#endif
#ifdef CONFIG_LPC17_UART3
# if CONFIG_UART3_BITS == 5
# define UART3_LCR_WLS UART_LCR_WLS_5BIT
# elif CONFIG_UART3_BITS == 6
# define UART3_LCR_WLS UART_LCR_WLS_6BIT
# elif CONFIG_UART3_BITS == 7
# define UART3_LCR_WLS UART_LCR_WLS_7BIT
# elif CONFIG_UART3_BITS == 8
# define UART3_LCR_WLS UART_LCR_WLS_8BIT
# else
# error "Invalid CONFIG_UARTn_BITS setting for UART3 "
# endif
#endif
/* Get parity setting for the console UART and UART0-3 */
#if CONSOLE_PARITY == 0
# define CONSOLE_LCR_PAR 0
#elif CONSOLE_PARITY == 1
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
#elif CONSOLE_PARITY == 2
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
#elif CONSOLE_PARITY == 3
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
#elif CONSOLE_PARITY == 4
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
#else
# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
#endif
#ifdef CONFIG_LPC17_UART0
# if CONFIG_UART0_PARITY == 0
# define UART0_LCR_PAR 0
# elif CONFIG_UART0_PARITY == 1
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
# elif CONFIG_UART0_PARITY == 2
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
# elif CONFIG_UART0_PARITY == 3
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
# elif CONFIG_UART0_PARITY == 4
# define UART0_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
# else
# error "Invalid CONFIG_UARTn_PARITY setting for UART0"
# endif
#endif
#ifdef CONFIG_LPC17_UART1
# if CONFIG_UART1_PARITY == 0
# define UART1_LCR_PAR 0
# elif CONFIG_UART1_PARITY == 1
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
# elif CONFIG_UART1_PARITY == 2
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
# elif CONFIG_UART1_PARITY == 3
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
# elif CONFIG_UART1_PARITY == 4
# define UART1_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
# else
# error "Invalid CONFIG_UARTn_PARITY setting for UART1"
# endif
#endif
#ifdef CONFIG_LPC17_UART2
# if CONFIG_UART2_PARITY == 0
# define UART2_LCR_PAR 0
# elif CONFIG_UART2_PARITY == 1
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
# elif CONFIG_UART2_PARITY == 2
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
# elif CONFIG_UART2_PARITY == 3
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
# elif CONFIG_UART2_PARITY == 4
# define UART2_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
# else
# error "Invalid CONFIG_UARTn_PARITY setting for UART2"
# endif
#endif
#ifdef CONFIG_LPC17_UART3
# if CONFIG_UART3_PARITY == 0
# define UART3_LCR_PAR 0
# elif CONFIG_UART3_PARITY == 1
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
# elif CONFIG_UART3_PARITY == 2
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
# elif CONFIG_UART3_PARITY == 3
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
# elif CONFIG_UART3_PARITY == 4
# define UART3_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
# else
# error "Invalid CONFIG_UARTn_PARITY setting for UART3"
# endif
#endif
/* Get stop-bit setting for the console UART and UART0-3 */
#if CONSOLE_2STOP != 0
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_2
#else
# define CONSOLE_LCR_STOP LPC214X_LCR_STOP_1
#endif
#if CONFIG_UART0_2STOP != 0
# define UART0_LCR_STOP LPC214X_LCR_STOP_2
#else
# define UART0_LCR_STOP LPC214X_LCR_STOP_1
#endif
#if CONFIG_UART1_2STOP != 0
# define UART1_LCR_STOP LPC214X_LCR_STOP_2
#else
# define UART1_LCR_STOP LPC214X_LCR_STOP_1
#endif
#if CONFIG_UART2_2STOP != 0
# define UART2_LCR_STOP LPC214X_LCR_STOP_2
#else
# define UART2_LCR_STOP LPC214X_LCR_STOP_1
#endif
#if CONFIG_UART3_2STOP != 0
# define UART3_LCR_STOP LPC214X_LCR_STOP_2
#else
# define UART3_LCR_STOP LPC214X_LCR_STOP_1
#endif
/* LCR and FCR values */
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
UART_FCR_RXRST | UART_FCR_FIFOEN)
#define UART0_LCR_VALUE (UART0_LCR_WLS | UART0_LCR_PAR | UART0_LCR_STOP)
#define UART0_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
UART_FCR_RXRST | UART_FCR_FIFOEN)
#define UART1_LCR_VALUE (UART1_LCR_WLS | UART1_LCR_PAR | UART1_LCR_STOP)
#define UART1_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
UART_FCR_RXRST | UART_FCR_FIFOEN)
#define UART2_LCR_VALUE (UART2_LCR_WLS | UART2_LCR_PAR | UART2_LCR_STOP)
#define UART2_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
UART_FCR_RXRST | UART_FCR_FIFOEN)
#define UART3_LCR_VALUE (UART3_LCR_WLS | UART3_LCR_PAR | UART3_LCR_STOP)
#define UART3_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
UART_FCR_RXRST | UART_FCR_FIFOEN)
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/************************************************************************************
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_SERIAL_H */

18
arch/arm/src/lpc17xx/lpc17_uart.h
View File

@ -175,19 +175,21 @@
#define UART_IER_ABEOIE (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
#define UART_IER_ABTOIE (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
/* Bits 10-31: Reserved */
#define UART_IER_ALLIE (0x038f)
/* IIR Interrupt ID Register (all) */
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
#define UART_IIR_INTID_MASK (7 < UART_IIR_INTID_SHIFT)
# define UART_IIR_INTID_MSI (0 < UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */
# define UART_IIR_INTID_THRE (1 < UART_IIR_INTID_SHIFT) /* THRE Interrupt */
# define UART_IIR_INTID_RDA (2 < UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA */
# define UART_IIR_INTID_RLS (3 < UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
# define UART_IIR_INTID_CTI (6 < UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Status (UART1 only) */
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA */
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
/* Bits 4-5: Reserved */
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */
#define UART_IIR_FIFOEN_MASK (3 < UART_IIR_FIFOEN_SHIFT)
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
/* Bits 10-31: Reserved */
@ -243,7 +245,7 @@
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE)
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
/* Bits 8-31: Reserved */
/* MSR Modem Status Register (UART1 only) */

6
arch/arm/src/sam3u/sam3u_serial.c
View File

@ -212,7 +212,7 @@
# ifdef CONFIG_SAM3U_USART3
# define TTYS2_DEV g_usart3port /* UART=ttyS0;USART2=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */
# else
# undef TTYS3_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# undef TTYS2_DEV /* UART=ttyS0;USART2=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# endif
# else
# ifdef CONFIG_SAM3U_USART3
@ -449,7 +449,7 @@
# ifdef CONFIG_SAM3U_USART3
# define TTYS2_DEV g_usart3port /* USART2=ttyS0;USART1=ttyS1;USART3=ttyS2;No ttyS3;No ttyS4 */
# else
# undef TTYS3_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# undef TTYS2_DEV /* USART2=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# endif
# else
# ifdef CONFIG_SAM3U_USART3
@ -528,7 +528,7 @@
# ifdef CONFIG_SAM3U_USART2
# define TTYS2_DEV g_EEEEport /* USART3=ttyS0;USART1=ttyS1;USART2=ttyS2;No ttyS3;No ttyS4 */
# else
# undef TTYS3_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# undef TTYS2_DEV /* USART3=ttyS0;USART1=ttyS1;No ttyS2;No ttyS3;No ttyS4 */
# endif
# else
# ifdef CONFIG_SAM3U_USART2

74
configs/nucleus2g/ostest/defconfig
View File

@ -102,31 +102,35 @@ CONFIG_LPC17_BUILDROOT=y
# Individual subsystems can be enabled:
#
# Individual subsystems can be enabled:
CONFIG_LP17_ETHERNET=n
CONFIG_LP17_USBHOST=n
CONFIG_LP17_USBOTG=n
CONFIG_LP17_USBDEV=n
CONFIG_LP17_CAN1=n
CONFIG_LP17_CAN2=n
CONFIG_LP17_SPI=n
CONFIG_LP17_SSP0=n
CONFIG_LP17_SSP1=n
CONFIG_LP17_I2C0=n
CONFIG_LP17_I2C1=n
CONFIG_LP17_I2S=n
CONFIG_LP17_TMR0=n
CONFIG_LP17_TMR1=n
CONFIG_LP17_TMR2=n
CONFIG_LP17_TMR3=n
CONFIG_LP17_RIT=n
CONFIG_LP17_PWM=n
CONFIG_LP17_MCPWM=n
CONFIG_LP17_QEI=n
CONFIG_LP17_RTC=n
CONFIG_LP17_WDT=n
CONFIG_LP17_ADC=n
CONFIG_LP17_DAC=n
CONFIG_LP17_GPDMA=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
CONFIG_LPC17_USBDEV=n
CONFIG_LPC17_UART0=y
CONFIG_LPC17_UART1=n
CONFIG_LPC17_UART2=n
CONFIG_LPC17_UART3=n
CONFIG_LPC17_CAN1=n
CONFIG_LPC17_CAN2=n
CONFIG_LPC17_SPI=n
CONFIG_LPC17_SSP0=n
CONFIG_LPC17_SSP1=n
CONFIG_LPC17_I2C0=n
CONFIG_LPC17_I2C1=n
CONFIG_LPC17_I2S=n
CONFIG_LPC17_TMR0=n
CONFIG_LPC17_TMR1=n
CONFIG_LPC17_TMR2=n
CONFIG_LPC17_TMR3=n
CONFIG_LPC17_RIT=n
CONFIG_LPC17_PWM=n
CONFIG_LPC17_MCPWM=n
CONFIG_LPC17_QEI=n
CONFIG_LPC17_RTC=n
CONFIG_LPC17_WDT=n
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
#
# LPC17xx specific serial device driver settings
@ -142,40 +146,40 @@ CONFIG_LP17_GPDMA=n
# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
# CONFIG_UARTn_2STOP - Two stop bits
#
CONFIG_UART1_SERIAL_CONSOLE=y
CONFIG_UART0_SERIAL_CONSOLE=y
CONFIG_UART1_SERIAL_CONSOLE=n
CONFIG_UART2_SERIAL_CONSOLE=n
CONFIG_UART3_SERIAL_CONSOLE=n
CONFIG_UART4_SERIAL_CONSOLE=n
CONFIG_UART0_TXBUFSIZE=256
CONFIG_UART1_TXBUFSIZE=256
CONFIG_UART2_TXBUFSIZE=256
CONFIG_UART3_TXBUFSIZE=256
CONFIG_UART4_TXBUFSIZE=256
CONFIG_UART0_RXBUFSIZE=256
CONFIG_UART1_RXBUFSIZE=256
CONFIG_UART2_RXBUFSIZE=256
CONFIG_UART3_RXBUFSIZE=256
CONFIG_UART4_RXBUFSIZE=256
CONFIG_UART1_BAUD=115200
CONFIG_UART0_BAUD=115200
CONFIG_UART2_BAUD=115200
CONFIG_UART3_BAUD=115200
CONFIG_UART4_BAUD=115200
CONFIG_UART1_BAUD=115200
CONFIG_UART0_BITS=8
CONFIG_UART1_BITS=8
CONFIG_UART2_BITS=8
CONFIG_UART3_BITS=8
CONFIG_UART4_BITS=8
CONFIG_UART0_PARITY=0
CONFIG_UART1_PARITY=0
CONFIG_UART2_PARITY=0
CONFIG_UART3_PARITY=0
CONFIG_UART4_PARITY=0
CONFIG_UART0_2STOP=0
CONFIG_UART1_2STOP=0
CONFIG_UART2_2STOP=0
CONFIG_UART3_2STOP=0
CONFIG_UART4_2STOP=0
#
# General build options
@ -295,7 +299,7 @@ CONFIG_EXAMPLE=ostest
CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_SYMBOLS=n
CONFIG_MM_REGIONS=1
CONFIG_MM_REGIONS=3
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_INSTRUMENTATION=n