From 24a2f8a0a427d59252de1ae70125045e26bafc08 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Fri, 19 Dec 2014 13:30:58 -0600 Subject: [PATCH] stm32: configure PLLSAI clock to enable ltdc register access Signed-off-by: Marco Krahl --- arch/arm/src/stm32/stm32f40xxx_rcc.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c index 0f8847f101..b15b383fc6 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c @@ -746,6 +746,32 @@ static void stm32_stdclockconfig(void) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) { } + +#ifdef CONFIG_STM32_LTDC + /* Configure PLLSAI */ + + regval = getreg32(STM32_RCC_PLLSAICFGR); + regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN + | STM32_RCC_PLLSAICFGR_PLLSAIR + | STM32_RCC_PLLSAICFGR_PLLSAIQ); + putreg32(regval, STM32_RCC_PLLSAICFGR); + + regval = getreg32(STM32_RCC_DCKCFGR); + regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR; + putreg32(regval, STM32_RCC_DCKCFGR); + + /* Enable PLLSAI */ + + regval = getreg32(STM32_RCC_CR); + regval |= RCC_CR_PLLSAION; + putreg32(regval, STM32_RCC_CR); + + /* Wait until the PLLSAI is ready */ + + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0) + { + } +#endif } } #endif