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stm32: configure PLLSAI clock to enable ltdc register access

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Signed-off-by: Marco Krahl <ocram.lhark@gmail.com>
This commit is contained in:
Gregory Nutt 2014-12-19 13:30:58 -06:00
parent 7999e7519c
commit 24a2f8a0a4
1 changed files with 26 additions and 0 deletions
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26
arch/arm/src/stm32/stm32f40xxx_rcc.c
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@ -746,6 +746,32 @@ static void stm32_stdclockconfig(void)
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL)
{ {
} }
#ifdef CONFIG_STM32_LTDC
/* Configure PLLSAI */
regval = getreg32(STM32_RCC_PLLSAICFGR);
regval |= (STM32_RCC_PLLSAICFGR_PLLSAIN
| STM32_RCC_PLLSAICFGR_PLLSAIR
| STM32_RCC_PLLSAICFGR_PLLSAIQ);
putreg32(regval, STM32_RCC_PLLSAICFGR);
regval = getreg32(STM32_RCC_DCKCFGR);
regval |= STM32_RCC_DCKCFGR_PLLSAIDIVR;
putreg32(regval, STM32_RCC_DCKCFGR);
/* Enable PLLSAI */
regval = getreg32(STM32_RCC_CR);
regval |= RCC_CR_PLLSAION;
putreg32(regval, STM32_RCC_CR);
/* Wait until the PLLSAI is ready */
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAIRDY) == 0)
{
}
#endif
} }
} }
#endif #endif