sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

RISC-V: Fix system crash when FPU is in use

Browse Source 
FPU registers need to be written prior to updating CSR_STATUS
This commit is contained in:
Ville Juven 2022-04-22 14:19:10 +03:00 committed by Xiang Xiao
parent 25d819253b
commit 2580520828
2 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/risc-v/src/common/riscv_exception_common.S
View File

@ -127,6 +127,8 @@ exception_common:
mv sp, a0
riscv_loadfpu sp
REGLOAD s0, REG_EPC(sp) /* restore sepc */
csrw CSR_EPC, s0
@ -134,7 +136,6 @@ exception_common:
csrw CSR_STATUS, s0
load_ctx sp
riscv_loadfpu sp
REGLOAD sp, REG_SP(sp) /* restore original sp */

3
arch/risc-v/src/common/supervisor/riscv_dispatch_syscall.S
View File

@ -109,6 +109,8 @@ riscv_dispatch_syscall:
mv sp, a0 /* use sp, as a0 gets wiped */
riscv_loadfpu sp
REGLOAD s0, REG_EPC(sp) /* restore epc */
csrw CSR_EPC, s0
@ -127,7 +129,6 @@ riscv_dispatch_syscall:
csrw CSR_STATUS, s0
load_ctx sp
riscv_loadfpu sp
REGLOAD sp, REG_SP(sp) /* restore original sp */