sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

stm32_dac: add support for DAC3

Browse Source
This commit is contained in:
Daniel P. Carvalho 2021-07-29 17:53:45 -03:00 committed by Mateusz Szafoni
parent 4fc5b62ec3
commit 2593089f84
3 changed files with 345 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

195
arch/arm/src/stm32/Kconfig
View File

@ -2000,7 +2000,7 @@ config STM32_STM32G43XX
select STM32_HAVE_CORDIC
select STM32_HAVE_CRS
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_DAC3
select STM32_HAVE_FMAC
select STM32_HAVE_FDCAN1
select STM32_HAVE_I2C2
@ -2866,12 +2866,36 @@ config STM32_DAC3
depends on STM32_HAVE_DAC3
select STM32_DAC
if STM32_DAC3
config STM32_DAC3CH1
bool "DAC3CH1 Internal"
default n
config STM32_DAC3CH2
bool "DAC3CH2 Internal"
default n
endif #STM32_DAC3
config STM32_DAC4
bool "DAC4"
default n
depends on STM32_HAVE_DAC4
select STM32_DAC
if STM32_DAC4
config STM32_DAC4CH1
bool "DAC4CH1 Internal"
default n
config STM32_DAC4CH2
bool "DAC4CH2 Internal"
default n
endif #STM32_DAC4
config STM32_DCMI
bool "DCMI"
default n
@ -8957,7 +8981,24 @@ config STM32_SDADC3_DMA
endmenu
menu "DAC Configuration"
depends on STM32_DAC1 || STM32_DAC2
depends on STM32_DAC1 || STM32_DAC2 || STM32_DAC3 || STM32_DAC4
config STM32_DAC1CH1_MODE
int "DAC1CH1 channel mode"
depends on STM32_DAC1CH1 && STM32_HAVE_IP_DAC_V2
default 0
range 0 7
---help---
– DAC channel in Normal mode
0: DAC channel is connected to external pin with Buffer enabled
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
2: DAC channel2 is connected to external pin with buffer disabled
3: DAC channel is connected to on chip peripherals with Buffer disabled
- DAC channel in Sample and hold mode
4: DAC channel is connected to external pin with Buffer enabled
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
7: DAC channel is connected to on chip peripherals with Buffer disabled
config STM32_DAC1CH1_DMA
bool "DAC1CH1 DMA"
@ -9003,6 +9044,23 @@ config STM32_DAC1CH1_TIMER_FREQUENCY
endif
config STM32_DAC1CH2_MODE
int "DAC1CH2 channel mode"
depends on STM32_DAC1CH2 && STM32_HAVE_IP_DAC_V2
default 0
range 0 7
---help---
– DAC channel in Normal mode
0: DAC channel is connected to external pin with Buffer enabled
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
2: DAC channel2 is connected to external pin with buffer disabled
3: DAC channel is connected to on chip peripherals with Buffer disabled
- DAC channel in Sample and hold mode
4: DAC channel is connected to external pin with Buffer enabled
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
7: DAC channel is connected to on chip peripherals with Buffer disabled
config STM32_DAC1CH2_DMA
bool "DAC1CH2 DMA"
depends on STM32_DAC1CH2
@ -9047,6 +9105,23 @@ config STM32_DAC1CH2_TIMER_FREQUENCY
endif
config STM32_DAC2CH1_MODE
int "DAC2CH1 channel mode"
depends on STM32_DAC2CH1 && STM32_HAVE_IP_DAC_V2
default 0
range 0 7
---help---
– DAC channel in Normal mode
0: DAC channel is connected to external pin with Buffer enabled
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
2: DAC channel2 is connected to external pin with buffer disabled
3: DAC channel is connected to on chip peripherals with Buffer disabled
- DAC channel in Sample and hold mode
4: DAC channel is connected to external pin with Buffer enabled
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
7: DAC channel is connected to on chip peripherals with Buffer disabled
config STM32_DAC2CH1_DMA
bool "DAC2CH1 DMA"
depends on STM32_DAC2CH1
@ -9088,6 +9163,122 @@ config STM32_DAC2CH1_TIMER_FREQUENCY
endif
config STM32_DAC3CH1_MODE
int "DAC3CH1 channel mode"
depends on STM32_DAC3CH1 && STM32_HAVE_IP_DAC_V2
default 0
range 0 7
---help---
– DAC channel in Normal mode
0: DAC channel is connected to external pin with Buffer enabled
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
2: DAC channel is connected to external pin with buffer disabled
3: DAC channel is connected to on chip peripherals with Buffer disabled
- DAC channel in Sample and hold mode
4: DAC channel is connected to external pin with Buffer enabled
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
7: DAC channel is connected to on chip peripherals with Buffer disabled
config STM32_DAC3CH1_DMA
bool "DAC3CH1 DMA"
depends on STM32_DAC3CH1
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by an EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC3CH1_DMA
config STM32_DAC3CH1_DMA_BUFFER_SIZE
int "DAC3CH1 DMA buffer size"
default 256
config STM32_DAC3CH1_DMA_EXTERNAL
bool "DAC3CH1 DMA External Trigger"
default n
if STM32_HRTIM_DAC
config STM32_DAC3CH1_HRTIM_TRG3
bool "DAC3CH1 HRTIM Trigger 3"
default n
endif # STM32_HRTIM_DAC
config STM32_DAC3CH1_TIMER
int "DAC3CH1 timer"
depends on !STM32_DAC3CH1_DMA_EXTERNAL
default 0
range 2 8
config STM32_DAC3CH1_TIMER_FREQUENCY
int "DAC3CH1 timer frequency"
depends on !STM32_DAC3CH1_DMA_EXTERNAL
default 0
endif
config STM32_DAC3CH2_MODE
int "DAC3CH2 channel mode"
depends on STM32_DAC3CH2 && STM32_HAVE_IP_DAC_V2
default 0
range 0 7
---help---
– DAC channel in Normal mode
0: DAC channel is connected to external pin with Buffer enabled
1: DAC channel is connected to external pin and to on chip peripherals with buffer enabled
2: DAC channel2 is connected to external pin with buffer disabled
3: DAC channel is connected to on chip peripherals with Buffer disabled
- DAC channel in Sample and hold mode
4: DAC channel is connected to external pin with Buffer enabled
5: DAC channel is connected to external pin and to on chip peripherals with Buffer enabled
6: DAC channel is connected to external pin and to on chip peripherals with Buffer disabled
7: DAC channel is connected to on chip peripherals with Buffer disabled
config STM32_DAC3CH2_DMA
bool "DAC3CH2 DMA"
depends on STM32_DAC3CH2
default n
---help---
If DMA is selected, then a timer and output frequency must also be
provided to support the DMA transfer. The DMA transfer could be
supported by an EXTI trigger, but this feature is not currently
supported by the driver.
if STM32_DAC3CH2_DMA
config STM32_DAC3CH2_DMA_BUFFER_SIZE
int "DAC3CH2 DMA buffer size"
default 256
config STM32_DAC3CH2_DMA_EXTERNAL
bool "DAC3CH1 DMA External Trigger"
default n
if STM32_HRTIM_DAC
config STM32_DAC3CH2_HRTIM_TRG3
bool "DAC3CH2 HRTIM Trigger 3"
default n
endif # STM32_HRTIM_DAC
config STM32_DAC3CH2_TIMER
int "DAC3CH2 timer"
depends on !STM32_DAC3CH2_DMA_EXTERNAL
default 0
range 2 8
config STM32_DAC3CH2_TIMER_FREQUENCY
int "DAC3CH2 timer frequency"
depends on !STM32_DAC3CH2_DMA_EXTERNAL
default 0
endif
endmenu
config STM32_USART

37
arch/arm/src/stm32/hardware/stm32gxxxxx_dac.h
View File

@ -65,7 +65,7 @@
/* Register Addresses *******************************************************/
#if STM32_NDAC > 0
#ifdef CONFIG_STM32_HAVE_DAC1
/* DAC1 */
# define STM32_DAC1_CR (STM32_DAC1_BASE + STM32_DAC_CR_OFFSET)
@ -92,9 +92,9 @@
# define STM32_DAC1_STR2 (STM32_DAC1_BASE + STM32_DAC_STR2_OFFSET)
# define STM32_DAC1_STMODR (STM32_DAC1_BASE + STM32_DAC_STMODR_OFFSET)
#endif
#endif /* CONFIG_STM32_HAVE_DAC1 */
#if STM32_NDAC > 1
#ifdef CONFIG_STM32_HAVE_DAC2
/* DAC2 */
# define STM32_DAC2_CR (STM32_DAC2_BASE + STM32_DAC_CR_OFFSET)
@ -121,7 +121,36 @@
# define STM32_DAC2_STR2 (STM32_DAC2_BASE + STM32_DAC_STR2_OFFSET)
# define STM32_DAC2_STMODR (STM32_DAC2_BASE + STM32_DAC_STMODR_OFFSET)
#endif
#endif /* CONFIG_STM32_HAVE_DAC2 */
#ifdef CONFIG_STM32_HAVE_DAC3
/* DAC3 */
# define STM32_DAC3_CR (STM32_DAC3_BASE + STM32_DAC_CR_OFFSET)
# define STM32_DAC3_SWTRIGR (STM32_DAC3_BASE + STM32_DAC_SWTRIGR_OFFSET)
# define STM32_DAC3_DHR12R1 (STM32_DAC3_BASE + STM32_DAC_DHR12R1_OFFSET)
# define STM32_DAC3_DHR12L1 (STM32_DAC3_BASE + STM32_DAC_DHR12L1_OFFSET)
# define STM32_DAC3_DHR8R1 (STM32_DAC3_BASE + STM32_DAC_DHR8R1_OFFSET)
# define STM32_DAC3_DHR12R2 (STM32_DAC3_BASE + STM32_DAC_DHR12R2_OFFSET)
# define STM32_DAC3_DHR12L2 (STM32_DAC3_BASE + STM32_DAC_DHR12L2_OFFSET)
# define STM32_DAC3_DHR8R2 (STM32_DAC3_BASE + STM32_DAC_DHR8R2_OFFSET)
# define STM32_DAC3_DHR12RD (STM32_DAC3_BASE + STM32_DAC_DHR12RD_OFFSET)
# define STM32_DAC3_DHR12LD (STM32_DAC3_BASE + STM32_DAC_DHR12LD_OFFSET)
# define STM32_DAC3_DHR8RD (STM32_DAC3_BASE + STM32_DAC_DHR8RD_OFFSET)
# define STM32_DAC3_DOR1 (STM32_DAC3_BASE + STM32_DAC_DOR1_OFFSET)
# define STM32_DAC3_DOR2 (STM32_DAC3_BASE + STM32_DAC_DOR2_OFFSET)
# define STM32_DAC3_SR (STM32_DAC3_BASE + STM32_DAC_SR_OFFSET)
# define STM32_DAC3_CCR (STM32_DAC3_BASE + STM32_DAC_CCR_OFFSET)
# define STM32_DAC3_MCR (STM32_DAC3_BASE + STM32_DAC_MCR_OFFSET)
# define STM32_DAC3_SHSR1 (STM32_DAC3_BASE + STM32_DAC_SHSR1_OFFSET)
# define STM32_DAC3_SHSR2 (STM32_DAC3_BASE + STM32_DAC_SHSR2_OFFSET)
# define STM32_DAC3_SHHR (STM32_DAC3_BASE + STM32_DAC_SHHR_OFFSET)
# define STM32_DAC3_SHRR (STM32_DAC3_BASE + STM32_DAC_SHRR_OFFSET)
# define STM32_DAC3_STR1 (STM32_DAC3_BASE + STM32_DAC_STR1_OFFSET)
# define STM32_DAC3_STR2 (STM32_DAC3_BASE + STM32_DAC_STR2_OFFSET)
# define STM32_DAC3_STMODR (STM32_DAC3_BASE + STM32_DAC_STMODR_OFFSET)
#endif /* CONFIG_STM32_HAVE_DAC3 */
/* Register Bitfield Definitions ********************************************/

126
arch/arm/src/stm32/stm32_dac.c
View File

@ -101,8 +101,6 @@
# undef CONFIG_STM32_DAC1CH1_TIMER_FREQUENCY
#endif
#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
/* Sanity checking */
#ifdef CONFIG_STM32_DAC1
@ -117,6 +115,18 @@
# endif
#endif
#ifdef CONFIG_STM32_DAC3
# if !defined(CONFIG_STM32_DAC3CH1) && !defined(CONFIG_STM32_DAC3CH2)
# error "DAC3 enabled but no channel was selected"
# endif
#endif
#ifdef CONFIG_STM32_DAC4
# if !defined(CONFIG_STM32_DAC4CH1) && !defined(CONFIG_STM32_DAC4CH2)
# error "DAC4 enabled but no channel was selected"
# endif
#endif
/* DMA configuration. */
#if defined(CONFIG_STM32_DAC1CH1_DMA) || defined(CONFIG_STM32_DAC1CH2_DMA) || \
@ -555,6 +565,9 @@ struct stm32_chan_s
#endif
uint8_t intf; /* DAC zero-based interface number (0 or 1) */
uint32_t pin; /* Pin configuration */
#ifdef HAVE_IP_DAC_V2
uint32_t mode; /* DAC channel mode */
#endif
uint32_t dro; /* Data output register */
uint32_t cr; /* Control register */
uint32_t tsel; /* CR trigger select value */
@ -642,6 +655,9 @@ static struct stm32_chan_s g_dac1ch1priv =
{
.intf = 0,
.pin = GPIO_DAC1_OUT1,
#ifdef HAVE_IP_DAC_V2
.mode = CONFIG_STM32_DAC1CH1_MODE;
#endif
.dro = STM32_DAC1_DHR12R1,
.cr = STM32_DAC1_CR,
#ifdef HAVE_IP_DAC_V2
@ -687,6 +703,9 @@ static struct stm32_chan_s g_dac1ch2priv =
{
.intf = 1,
.pin = GPIO_DAC1_OUT2,
#ifdef HAVE_IP_DAC_V2
.mode = CONFIG_STM32_DAC1CH2_MODE << 16;
#endif
.dro = STM32_DAC1_DHR12R2,
.cr = STM32_DAC1_CR,
#ifdef HAVE_IP_DAC_V2
@ -735,6 +754,9 @@ static struct stm32_chan_s g_dac2ch1priv =
{
.intf = 2,
.pin = GPIO_DAC2_OUT1,
#ifdef HAVE_IP_DAC_V2
.mode = CONFIG_STM32_DAC2CH1_MODE;
#endif
.dro = STM32_DAC2_DHR12R1,
.cr = STM32_DAC2_CR,
#ifdef HAVE_IP_DAC_V2
@ -770,6 +792,64 @@ static struct dac_dev_s g_dac2ch1dev =
#endif /* CONFIG_STM32_DAC2CH1 */
#endif /* CONFIG_STM32_DAC2 */
#ifdef CONFIG_STM32_DAC3
#ifdef CONFIG_STM32_DAC3CH1
/* Channel 4: DAC3 channel 1 */
#ifdef CONFIG_STM32_DAC3CH1_DMA
# error "STM32_DAC3 DMA not supported"
#endif
static struct stm32_chan_s g_dac3ch1priv =
{
.intf = 4,
.dro = STM32_DAC3_DHR12R1,
#ifdef HAVE_IP_DAC_V2
.mode = CONFIG_STM32_DAC3CH1_MODE;
#endif
.cr = STM32_DAC3_CR,
#ifdef HAVE_IP_DAC_V2
.sr = STM32_DAC3_SR,
.mcr = STM32_DAC3_MCR,
#endif
};
static struct dac_dev_s g_dac3ch1dev =
{
.ad_ops = &g_dacops,
.ad_priv = &g_dac3ch1priv,
};
#endif /* CONFIG_STM32_DAC3CH1 */
#ifdef CONFIG_STM32_DAC3CH2
/* Channel 5: DAC3 channel 1 */
#ifdef CONFIG_STM32_DAC3CH2_DMA
# error "STM32_DAC3 DMA not supported"
#endif
static struct stm32_chan_s g_dac3ch2priv =
{
.intf = 5,
.dro = STM32_DAC3_DHR12R2,
#ifdef HAVE_IP_DAC_V2
.mode = CONFIG_STM32_DAC3CH2_MODE << 16,
#endif
.cr = STM32_DAC3_CR,
#ifdef HAVE_IP_DAC_V2
.sr = STM32_DAC3_SR,
.mcr = STM32_DAC3_MCR,
#endif
};
static struct dac_dev_s g_dac3ch2dev =
{
.ad_ops = &g_dacops,
.ad_priv = &g_dac3ch2priv,
};
#endif /* CONFIG_STM32_DAC3CH2 */
#endif /* CONFIG_STM32_DAC3 */
static struct stm32_dac_s g_dacblock;
/****************************************************************************
@ -1051,7 +1131,7 @@ static int dac_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
{
regval = getreg32(chan->sr);
}
while (!(regval & DAC_SR_DACRDY(dac + 1)));
while (!(regval & DAC_SR_DACRDY(dac)));
#endif
#ifdef HAVE_DMA
@ -1425,6 +1505,9 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
{
uint16_t clearbits;
uint16_t setbits;
#if defined(HAVE_IP_DAC_V2)
uint32_t regval;
#endif
#ifdef HAVE_TIMER
int ret;
#endif
@ -1446,7 +1529,12 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
* should first be configured to analog (AIN)".
*/
stm32_configgpio(chan->pin);
/* Only DAC1 and DAC2 have external pins */
if (chan->intf < 4)
{
stm32_configgpio(chan->pin);
}
/* DAC channel configuration:
*
@ -1479,7 +1567,6 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
#if defined(HAVE_IP_DAC_V2)
/* High frequency interface mode selection */
uint32_t regval;
if (STM32_SYSCLK_FREQUENCY > 160000000)
{
regval = DAC_MCR_HFSEL_AHB_160MHz;
@ -1493,7 +1580,11 @@ static int dac_chaninit(FAR struct stm32_chan_s *chan)
regval = DAC_MCR_HFSEL_DISABLED;
}
putreg32(regval, STM32_DAC1_MCR);
/* DAC mode selection */
regval |= chan->mode;
putreg32(regval, chan->mcr);
#endif
#ifdef HAVE_DMA
@ -1582,6 +1673,9 @@ static int dac_blockinit(void)
#endif
#ifdef CONFIG_STM32_DAC2
regval |= RCC_RSTR_DAC2RST;
#endif
#ifdef CONFIG_STM32_DAC3
regval |= RCC_RSTR_DAC3RST;
#endif
putreg32(regval, STM32_RCC_RSTR);
@ -1592,6 +1686,9 @@ static int dac_blockinit(void)
#endif
#ifdef CONFIG_STM32_DAC2
regval &= ~RCC_RSTR_DAC2RST;
#endif
#ifdef CONFIG_STM32_DAC3
regval &= ~RCC_RSTR_DAC3RST;
#endif
putreg32(regval, STM32_RCC_RSTR);
leave_critical_section(flags);
@ -1654,6 +1751,22 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
}
else
#endif /* CONFIG_STM32_DAC2CH1 */
#ifdef CONFIG_STM32_DAC3CH1
if (intf == 4)
{
ainfo("DAC3-1 Selected\n");
dev = &g_dac3ch1dev;
}
else
#endif /* CONFIG_STM32_DAC3CH1 */
#ifdef CONFIG_STM32_DAC3CH2
if (intf == 5)
{
ainfo("DAC3-2 Selected\n");
dev = &g_dac3ch2dev;
}
else
#endif /* CONFIG_STM32_DAC3CH2 */
{
aerr("ERROR: No such DAC interface: %d\n", intf);
return NULL;
@ -1681,5 +1794,4 @@ FAR struct dac_dev_s *stm32_dacinitialize(int intf)
return dev;
}
#endif /* CONFIG_STM32_DAC1 || CONFIG_STM32_DAC2 */
#endif /* CONFIG_DAC */