diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
old mode 100644
new mode 100755
index abbc74ccac..fe41d4eb9d
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -409,6 +409,7 @@ __start:
 	bic		r0, r0, #(SCTLR_SW | SCTLR_I   | SCTLR_V   | SCTLR_RR | SCTLR_HA)
 	bic		r0, r0, #(SCTLR_EE | SCTLR_TRE | SCTLR_AFE | SCTLR_TE)
 
+#ifndef CONFIG_SMP
 	/* Set bits to enable the MMU
 	 *
 	 *   SCTLR_M     Bit 0:  Enable the MMU
@@ -416,6 +417,8 @@ __start:
 	 */
 
 	orr		r0, r0, #(SCTLR_M)
+#endif
+
 #ifndef CONFIG_ARCH_CORTEXA5
 	orr		r0, r0, #(SCTLR_Z)
 #endif
diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c
old mode 100644
new mode 100755
index ad3329b1b6..9f889ecfbf
--- a/arch/arm/src/armv7-a/arm_scu.c
+++ b/arch/arm/src/armv7-a/arm_scu.c
@@ -203,6 +203,6 @@ void arm_enable_smp(int cpu)
   arm_set_actlr(regval);
 
   regval  = arm_get_sctlr();
-  regval |= SCTLR_C | SCTLR_I;
+  regval |= SCTLR_C | SCTLR_I | SCTLR_M;
   arm_set_sctlr(regval);
 }