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arch/arm/src/samd5e5/: Combine some duplicated GCLK configuration logic

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This commit is contained in:
Gregory Nutt 2018-08-31 13:34:09 -06:00
parent b699bdef3b
commit 25dce66483
7 changed files with 185 additions and 290 deletions
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4
arch/arm/src/samd5e5/chip/sam_gclk.h
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@ -110,10 +110,10 @@
#define GCLK_GENCTRL_OE (1 << 11) /* Bit 11: Clock output enable */ #define GCLK_GENCTRL_OE (1 << 11) /* Bit 11: Clock output enable */
#define GCLK_GENCTRL_DIVSEL (1 << 12) /* Bit 12: Clock source divider */ #define GCLK_GENCTRL_DIVSEL (1 << 12) /* Bit 12: Clock source divider */
#define GCLK_GENCTRL_RUNSTDBY (1 << 13) /* Bit 13: Run in standby */ #define GCLK_GENCTRL_RUNSTDBY (1 << 13) /* Bit 13: Run in standby */
#define GCLK_GENCTRL_DIV_SHIFT (16) /* Bits 16-31: Generator 0,2-11 Division factor */ #define GCLK_GENCTRL_DIV_SHIFT (16) /* Bits 16-23: Generator 0,2-11 Division factor */
#define GCLK_GENCTRL_DIV_MASK (0xff << GCLK_GENCTRL_DIV_SHIFT) #define GCLK_GENCTRL_DIV_MASK (0xff << GCLK_GENCTRL_DIV_SHIFT)
# define GCLK_GENCTRL_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL_DIV_SHIFT) # define GCLK_GENCTRL_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL_DIV_SHIFT)
#define GCLK_GENCTRL1_DIV_SHIFT (16) /* Bits 16-23: Generator 1 Division factor **/ #define GCLK_GENCTRL1_DIV_SHIFT (16) /* Bits 16-31: Generator 1 Division factor **/
#define GCLK_GENCTRL1_DIV_MASK (0xffff << GCLK_GENCTRL1_DIV_SHIFT) #define GCLK_GENCTRL1_DIV_MASK (0xffff << GCLK_GENCTRL1_DIV_SHIFT)
# define GCLK_GENCTRL1_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL1_DIV_SHIFT) # define GCLK_GENCTRL1_DIV(n) ((uint32_t)(n) << GCLK_GENCTRL1_DIV_SHIFT)

231
arch/arm/src/samd5e5/sam_clockconfig.c
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@ -149,7 +149,7 @@ static const struct sam_clockconfig_s g_initial_clocking =
.gclk = BOARD_DFLL_GCLK, .gclk = BOARD_DFLL_GCLK,
.mul = BOARD_DFLL_MUL .mul = BOARD_DFLL_MUL
}, },
.dpll = .dpll =
{ {
{ {
.enable = BOARD_DPLL0_ENABLE, .enable = BOARD_DPLL0_ENABLE,
@ -189,124 +189,100 @@ static const struct sam_clockconfig_s g_initial_clocking =
.gclk = .gclk =
{ {
{ {
.enable = BOARD_GCLK0_ENABLE, .enable = BOARD_GCLK0_ENABLE,
.idc = BOARD_GCLK0_IDC, .oov = BOARD_GCLK0_OOV,
.oov = BOARD_GCLK0_OOV, .oe = BOARD_GCLK0_OE,
.oe = BOARD_GCLK0_OE, .runstdby = BOARD_GCLK0_RUNSTDBY,
.divsel = BOARD_GCLK0_DIVSEL, .source = BOARD_GCLK0_SOURCE,
.runstdby = BOARD_GCLK0_RUNSTDBY, .div = BOARD_GCLK0_DIV
.source = BOARD_GCLK0_SOURCE,
.div = BOARD_GCLK0_DIV
}, },
{ {
.enable = BOARD_GCLK1_ENABLE, .enable = BOARD_GCLK1_ENABLE,
.idc = BOARD_GCLK1_IDC, .oov = BOARD_GCLK1_OOV,
.oov = BOARD_GCLK1_OOV, .oe = BOARD_GCLK1_OE,
.oe = BOARD_GCLK1_OE, .runstdby = BOARD_GCLK1_RUNSTDBY,
.divsel = BOARD_GCLK1_DIVSEL, .source = BOARD_GCLK1_SOURCE,
.runstdby = BOARD_GCLK1_RUNSTDBY, .div = BOARD_GCLK1_DIV
.source = BOARD_GCLK1_SOURCE,
.div = BOARD_GCLK1_DIV
}, },
{ {
.enable = BOARD_GCLK2_ENABLE, .enable = BOARD_GCLK2_ENABLE,
.idc = BOARD_GCLK2_IDC, .oov = BOARD_GCLK2_OOV,
.oov = BOARD_GCLK2_OOV, .oe = BOARD_GCLK2_OE,
.oe = BOARD_GCLK2_OE, .runstdby = BOARD_GCLK2_RUNSTDBY,
.divsel = BOARD_GCLK2_DIVSEL, .source = BOARD_GCLK2_SOURCE,
.runstdby = BOARD_GCLK2_RUNSTDBY, .div = BOARD_GCLK2_DIV
.source = BOARD_GCLK2_SOURCE,
.div = BOARD_GCLK2_DIV
}, },
{ {
.enable = BOARD_GCLK3_ENABLE, .enable = BOARD_GCLK3_ENABLE,
.idc = BOARD_GCLK3_IDC, .oov = BOARD_GCLK3_OOV,
.oov = BOARD_GCLK3_OOV, .oe = BOARD_GCLK3_OE,
.oe = BOARD_GCLK3_OE, .runstdby = BOARD_GCLK3_RUNSTDBY,
.divsel = BOARD_GCLK3_DIVSEL, .source = BOARD_GCLK3_SOURCE,
.runstdby = BOARD_GCLK3_RUNSTDBY, .div = BOARD_GCLK3_DIV
.source = BOARD_GCLK3_SOURCE,
.div = BOARD_GCLK3_DIV
}, },
{ {
.enable = BOARD_GCLK4_ENABLE, .enable = BOARD_GCLK4_ENABLE,
.idc = BOARD_GCLK4_IDC, .oov = BOARD_GCLK4_OOV,
.oov = BOARD_GCLK4_OOV, .oe = BOARD_GCLK4_OE,
.oe = BOARD_GCLK4_OE, .runstdby = BOARD_GCLK4_RUNSTDBY,
.divsel = BOARD_GCLK4_DIVSEL, .source = BOARD_GCLK4_SOURCE,
.runstdby = BOARD_GCLK4_RUNSTDBY, .div = BOARD_GCLK4_DIV
.source = BOARD_GCLK4_SOURCE,
.div = BOARD_GCLK4_DIV
}, },
{ {
.enable = BOARD_GCLK5_ENABLE, .enable = BOARD_GCLK5_ENABLE,
.idc = BOARD_GCLK5_IDC, .oov = BOARD_GCLK5_OOV,
.oov = BOARD_GCLK5_OOV, .oe = BOARD_GCLK5_OE,
.oe = BOARD_GCLK5_OE, .runstdby = BOARD_GCLK5_RUNSTDBY,
.divsel = BOARD_GCLK5_DIVSEL, .source = BOARD_GCLK5_SOURCE,
.runstdby = BOARD_GCLK5_RUNSTDBY, .div = BOARD_GCLK5_DIV
.source = BOARD_GCLK5_SOURCE,
.div = BOARD_GCLK5_DIV
}, },
{ {
.enable = BOARD_GCLK6_ENABLE, .enable = BOARD_GCLK6_ENABLE,
.idc = BOARD_GCLK6_IDC, .oov = BOARD_GCLK6_OOV,
.oov = BOARD_GCLK6_OOV, .oe = BOARD_GCLK6_OE,
.oe = BOARD_GCLK6_OE, .runstdby = BOARD_GCLK6_RUNSTDBY,
.divsel = BOARD_GCLK6_DIVSEL, .source = BOARD_GCLK6_SOURCE,
.runstdby = BOARD_GCLK6_RUNSTDBY, .div = BOARD_GCLK6_DIV
.source = BOARD_GCLK6_SOURCE,
.div = BOARD_GCLK6_DIV
}, },
{ {
.enable = BOARD_GCLK7_ENABLE, .enable = BOARD_GCLK7_ENABLE,
.idc = BOARD_GCLK7_IDC, .oov = BOARD_GCLK7_OOV,
.oov = BOARD_GCLK7_OOV, .oe = BOARD_GCLK7_OE,
.oe = BOARD_GCLK7_OE, .runstdby = BOARD_GCLK7_RUNSTDBY,
.divsel = BOARD_GCLK7_DIVSEL, .source = BOARD_GCLK7_SOURCE,
.runstdby = BOARD_GCLK7_RUNSTDBY, .div = BOARD_GCLK7_DIV
.source = BOARD_GCLK7_SOURCE,
.div = BOARD_GCLK7_DIV
}, },
{ {
.enable = BOARD_GCLK8_ENABLE, .enable = BOARD_GCLK8_ENABLE,
.idc = BOARD_GCLK8_IDC, .oov = BOARD_GCLK8_OOV,
.oov = BOARD_GCLK8_OOV, .oe = BOARD_GCLK8_OE,
.oe = BOARD_GCLK8_OE, .runstdby = BOARD_GCLK8_RUNSTDBY,
.divsel = BOARD_GCLK8_DIVSEL, .source = BOARD_GCLK8_SOURCE,
.runstdby = BOARD_GCLK8_RUNSTDBY, .div = BOARD_GCLK8_DIV
.source = BOARD_GCLK8_SOURCE,
.div = BOARD_GCLK8_DIV
}, },
{ {
.enable = BOARD_GCLK9_ENABLE, .enable = BOARD_GCLK9_ENABLE,
.idc = BOARD_GCLK9_IDC, .oov = BOARD_GCLK9_OOV,
.oov = BOARD_GCLK9_OOV, .oe = BOARD_GCLK9_OE,
.oe = BOARD_GCLK9_OE, .runstdby = BOARD_GCLK9_RUNSTDBY,
.divsel = BOARD_GCLK9_DIVSEL, .source = BOARD_GCLK9_SOURCE,
.runstdby = BOARD_GCLK9_RUNSTDBY, .div = BOARD_GCLK9_DIV
.source = BOARD_GCLK9_SOURCE,
.div = BOARD_GCLK9_DIV
}, },
{ {
.enable = BOARD_GCLK10_ENABLE, .enable = BOARD_GCLK10_ENABLE,
.idc = BOARD_GCLK10_IDC, .oov = BOARD_GCLK10_OOV,
.oov = BOARD_GCLK10_OOV, .oe = BOARD_GCLK10_OE,
.oe = BOARD_GCLK10_OE, .runstdby = BOARD_GCLK10_RUNSTDBY,
.divsel = BOARD_GCLK10_DIVSEL, .source = BOARD_GCLK10_SOURCE,
.runstdby = BOARD_GCLK10_RUNSTDBY, .div = BOARD_GCLK10_DIV
.source = BOARD_GCLK10_SOURCE,
.div = BOARD_GCLK10_DIV
}, },
{ {
.enable = BOARD_GCLK11_ENABLE, .enable = BOARD_GCLK11_ENABLE,
.idc = BOARD_GCLK11_IDC, .oov = BOARD_GCLK11_OOV,
.oov = BOARD_GCLK11_OOV, .oe = BOARD_GCLK11_OE,
.oe = BOARD_GCLK11_OE, .runstdby = BOARD_GCLK11_RUNSTDBY,
.divsel = BOARD_GCLK11_DIVSEL, .source = BOARD_GCLK11_SOURCE,
.runstdby = BOARD_GCLK11_RUNSTDBY, .div = BOARD_GCLK11_DIV
.source = BOARD_GCLK11_SOURCE,
.div = BOARD_GCLK11_DIV
} }
} }
}; };
@ -608,65 +584,6 @@ static inline void sam_mclk_configure(uint8_t cpudiv)
putreg8(cpudiv, SAM_MCLK_CPUDIV); putreg8(cpudiv, SAM_MCLK_CPUDIV);
} }
/****************************************************************************
* Name: sam_gclk_configure
*
* Description:
* Configure one GCLK
*
****************************************************************************/
static void sam_gclk_configure(uintptr_t regaddr,
const struct sam_gclk_config_s *config)
{
uint32_t regval;
/* Are we enabling or disabling the GCLK? */
if (config->enable)
{
/* Get the GCLK configuration */
regval = GCLK_GENCTRL_SRC(config->source) | GCLK_GENCTRL_GENEN |
GCLK_GENCTRL1_DIV(config->div);
if (config->idc)
{
regval |= GCLK_GENCTRL_IDC;
}
if (config->oov)
{
regval |= GCLK_GENCTRL_OOV;
}
if (config->oe)
{
regval |= GCLK_GENCTRL_OE;
}
if (config->divsel)
{
regval |= GCLK_GENCTRL_DIVSEL;
}
if (config->runstdby)
{
regval |= GCLK_GENCTRL_RUNSTDBY;
}
}
else
{
/* Disable the GCLK */
regval = 0;
}
/* Write the GCLK configuration */
putreg32(regval, regaddr);
}
/**************************************************************************** /****************************************************************************
* Name: sam_gclkset_configure * Name: sam_gclkset_configure
* *
@ -693,7 +610,7 @@ static void sam_gclkset_configure(uint16_t gclkset,
/* Yes.. Remove it from the set and configure it */ /* Yes.. Remove it from the set and configure it */
gclkset &= ~mask; gclkset &= ~mask;
sam_gclk_configure(SAM_GCLK_GENCTRL(gclk), &config[gclk]); sam_gclk_configure(gclk, &config[gclk]);
} }
} }
} }

24
arch/arm/src/samd5e5/sam_clockconfig.h
View File

@ -41,6 +41,7 @@
************************************************************************************/ ************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include "sam_gclk.h"
/************************************************************************************ /************************************************************************************
* Pre-processor Definitions * Pre-processor Definitions
@ -182,29 +183,6 @@ struct sam_dpll_config_s
uint16_t div; /* Clock divider */ uint16_t div; /* Clock divider */
}; };
/* This structure defines the configuration of a GCLK */
struct sam_gclk_config_s
{
uint8_t enable : 1; /* True: Enable GCLK */
uint8_t idc : 1; /* True: Improve duty cycle */
uint8_t oov : 1; /* True: Clock output selection */
uint8_t oe : 1; /* True: Output enable */
uint8_t divsel : 1; /* True: Clock source divider */
uint8_t runstdby : 1; /* Run in standby */
uint8_t source; /* GCLK clock source:
* 0 XOSC 0 oscillator input
* 1 XOSC 1 oscillator input
* 2 Generator input pad
* 3 Generic clock generator 1 output
* 4 OSCULP32K oscillator output
* 5 XOSC32K oscillator output
* 6 DFLL oscillator output
* 7 DPLL0 output
* 8 DPLL1 output */
uint16_t div; /* Division factor: 8-bits for all but GCLK1 */
};
/* This structure defines the configuration of the clock sus-system */ /* This structure defines the configuration of the clock sus-system */
struct sam_clockconfig_s struct sam_clockconfig_s

154
arch/arm/src/samd5e5/sam_gclk.c
View File

@ -71,7 +71,9 @@
static void sam_gclck_waitsyncbusy(uint8_t gclk) static void sam_gclck_waitsyncbusy(uint8_t gclk)
{ {
uintptr_t gclkbit = GCLK_SYNCHBUSY_GENCTRL(gclk); uintptr_t gclkbit = GCLK_SYNCHBUSY_GENCTRL(gclk);
while ((getreg8(SAM_GCLK_SYNCHBUSY) & gclkbit) != 0); while ((getreg8(SAM_GCLK_SYNCHBUSY) & gclkbit) != 0)
{
}
} }
/**************************************************************************** /****************************************************************************
@ -79,12 +81,13 @@ static void sam_gclck_waitsyncbusy(uint8_t gclk)
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: sam_gclk_config * Name: sam_gclk_configure
* *
* Description: * Description:
* Configure a single GCLK(s) based on settings in the config structure. * Configure a single GCLK(s) based on settings in the config structure.
* *
* Input Parameters: * Input Parameters:
* gclk - GCLK index
* config - An instance of struct sam_gclkconfig describing the GCLK * config - An instance of struct sam_gclkconfig describing the GCLK
* configuration. * configuration.
* *
@ -93,111 +96,114 @@ static void sam_gclck_waitsyncbusy(uint8_t gclk)
* *
****************************************************************************/ ****************************************************************************/
void sam_gclk_config(FAR const struct sam_gclkconfig_s *config) void sam_gclk_configure(int gclk, FAR const struct sam_gclk_config_s *config)
{ {
irqstate_t flags; irqstate_t flags;
uintptr_t regaddr; uintptr_t regaddr;
uint32_t regval; uint32_t regval;
uint32_t genctrl;
/* Select the requested source clock for the generator */ /* Are we enabling or disabling the GCLK? */
genctrl = ((uint32_t)config->clksrc << GCLK_GENCTRL_SRC_SHIFT); regval = 0;
regaddr = SAM_GCLK_GENCTRL(gclk);
#if 0 /* Not yet supported */ if (config->enable)
/* Configure the clock to be either high or low when disabled */
if (config->level)
{ {
genctrl |= GCLK_GENCTRL_OOV; /* Select the requested source clock for the generator */
}
#endif
/* Configure if the clock output to I/O pin should be enabled */ regval = GCLK_GENCTRL_SRC(config->source);
if (config->output) /* Clock output selection */
{
genctrl |= GCLK_GENCTRL_OE;
}
/* Set the prescaler division factor */ if (config->oov)
if (config->prescaler > 1)
{
/* Check if division is a power of two */
if (((config->prescaler & (config->prescaler - 1)) == 0))
{ {
/* Determine the index of the highest bit set to get the regval |= GCLK_GENCTRL_OOV;
* division factor that must be loaded into the division }
* register.
*/
uint32_t count = 0; /* Output enable */
uint32_t mask;
for (mask = 2; mask < (uint32_t)config->prescaler; mask <<= 1) if (config->oe)
{
regval |= GCLK_GENCTRL_OE;
}
/* Run in standby */
if (config->runstdby)
{
regval |= GCLK_GENCTRL_RUNSTDBY;
}
/* Set the prescaler division factor */
if (config->div > 1)
{
/* Check if division is a power of two */
if (((config->div & (config->div - 1)) == 0))
{ {
count++; /* Determine the index of the highest bit set to get the
* division factor that must be loaded into the division
* register.
*/
uint32_t count = 0;
uint32_t mask;
for (mask = 2; mask < (uint32_t)config->div; mask <<= 1)
{
count++;
}
/* Set binary divider power of 2 division factor */
regval |= GCLK_GENCTRL1_DIV(count);
regval |= GCLK_GENCTRL_DIVSEL;
} }
else
{
/* Set integer division factor */
/* Set binary divider power of 2 division factor */ regval |= GCLK_GENCTRL1_DIV((uint32_t)config->div);
genctrl |= count << GCLK_GENCTRL_DIV_SHIFT; /* Enable non-binary division with increased duty cycle accuracy */
genctrl |= GCLK_GENCTRL_DIVSEL;
regval |= GCLK_GENCTRL_IDC;
}
} }
else
/* Don't disable GCLK0 */
if (gclk == 0)
{ {
/* Set integer division factor */ regval |= GCLK_GENCTRL_GENEN;
genctrl |= GCLK_GENCTRL_DIV((uint32_t)config->prescaler);
/* Enable non-binary division with increased duty cycle accuracy */
genctrl |= GCLK_GENCTRL_IDC;
} }
} }
/* Enable or disable the clock in standby mode */
if (config->runstandby)
{
genctrl |= GCLK_GENCTRL_RUNSTDBY;
}
/* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk);
/* Preserve the GENEN bit */
regaddr = SAM_GCLK_GENCTRL(config->gclk);
flags = enter_critical_section();
regval = getreg32(regaddr);
regval &= GCLK_GENCTRL_GENEN;
genctrl |= regval;
/* Configure the generator */ /* Configure the generator */
putreg32(genctrl, regaddr); flags = enter_critical_section();
putreg32(regval, regaddr);
/* Wait for synchronization */ /* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk); sam_gclck_waitsyncbusy(gclk);
leave_critical_section(flags); leave_critical_section(flags);
sam_gclck_waitsyncbusy(config->gclk); sam_gclck_waitsyncbusy(gclk);
/* Enable the clock generator */ if (config->enable)
{
/* Enable the clock generator */
flags = enter_critical_section(); flags = enter_critical_section();
genctrl |= GCLK_GENCTRL_GENEN; regval |= GCLK_GENCTRL_GENEN;
putreg32(genctrl, regaddr); putreg32(regval, regaddr);
/* Wait for synchronization */ /* Wait for synchronization */
sam_gclck_waitsyncbusy(config->gclk); sam_gclck_waitsyncbusy(gclk);
leave_critical_section(flags); leave_critical_section(flags);
}
} }
/**************************************************************************** /****************************************************************************

27
arch/arm/src/samd5e5/sam_gclk.h
View File

@ -61,13 +61,23 @@
/* This structure describes the configuration of one GCLK */ /* This structure describes the configuration of one GCLK */
struct sam_gclkconfig_s struct sam_gclk_config_s
{ {
uint8_t gclk; /* Clock generator */ uint8_t enable : 1; /* True: Enable GCLK */
bool runstandby; /* Run clock in standby */ uint8_t oov : 1; /* True: Clock output selection */
bool output; /* Output enable */ uint8_t oe : 1; /* True: Output enable */
uint8_t clksrc; /* Encoded clock source */ uint8_t runstdby : 1; /* True: Run in standby */
uint16_t prescaler; /* Prescaler value */ uint8_t source; /* GCLK clock source:
* 0 XOSC 0 oscillator input
* 1 XOSC 1 oscillator input
* 2 Generator input pad
* 3 Generic clock generator 1 output
* 4 OSCULP32K oscillator output
* 5 XOSC32K oscillator output
* 6 DFLL oscillator output
* 7 DPLL0 output
* 8 DPLL1 output */
uint16_t div; /* Division factor: 8-bits for all but GCLK1 */
}; };
/**************************************************************************** /****************************************************************************
@ -92,12 +102,13 @@ extern "C"
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: sam_gclk_config * Name: sam_gclk_configure
* *
* Description: * Description:
* Configure a single GCLK(s) based on settings in the config structure. * Configure a single GCLK(s) based on settings in the config structure.
* *
* Input Parameters: * Input Parameters:
* gclk - GCLK index
* config - An instance of struct sam_gclkconfig describing the GCLK * config - An instance of struct sam_gclkconfig describing the GCLK
* configuration. * configuration.
* *
@ -106,7 +117,7 @@ extern "C"
* *
****************************************************************************/ ****************************************************************************/
void sam_gclk_config(FAR const struct sam_gclkconfig_s *config); void sam_gclk_configure(int gclk, FAR const struct sam_gclk_config_s *config);
/**************************************************************************** /****************************************************************************
* Name: sam_gclk_chan_enable * Name: sam_gclk_chan_enable

7
configs/metro-m4/README.txt
View File

@ -59,13 +59,18 @@ STATUS
to halt the CPU. to halt the CPU.
This is most likely a consequence of something happening in the NuttX This is most likely a consequence of something happening in the NuttX
boot-up sequence that interferes with JTAG operation. boot-up sequence that interferes with JTAG operation. There must be
be some way around this, but I don't know what it is.
Future me: This boot-up failure was do to bad clock initialization Future me: This boot-up failure was do to bad clock initialization
logic that caused infinite loops during clock configuration. Unlocking logic that caused infinite loops during clock configuration. Unlocking
and erasing the FLASH is innocuous, but the JTAG will apparently not and erasing the FLASH is innocuous, but the JTAG will apparently not
work if the clocks are not in a good state. work if the clocks are not in a good state.
I would say that as a general practice, any changes to the clock
configuration should be testing in SRAM first before risking the
write to FLASH.
2018-08-03: Added a configuration option to run out of SRAM vs FLASH. 2018-08-03: Added a configuration option to run out of SRAM vs FLASH.
This should be a safer way to do the initial board bring-up since This should be a safer way to do the initial board bring-up since
it does not modify the FLASH image nor does it require unlocking it does not modify the FLASH image nor does it require unlocking

28
configs/metro-m4/include/board.h
View File

@ -98,8 +98,8 @@
/* XOSC32 */ /* XOSC32 */
#define BOARD_HAVE_XOSC32K 1 /* 32.768KHz XOSC32 crystal installed */ #define BOARD_HAVE_XOSC32K 1 /* 32.768 KHz XOSC32 crystal installed */
#define BOARD_XOSC32K_ENABLE false /* Don't enable XOSC32 */ #define BOARD_XOSC32K_ENABLE true /* Enable XOSC32 */
#define BOARD_XOSC32K_XTALEN false /* External clock connected on XIN32 */ #define BOARD_XOSC32K_XTALEN false /* External clock connected on XIN32 */
#define BOARD_XOSC32K_EN32K false /* No 32KHz output */ #define BOARD_XOSC32K_EN32K false /* No 32KHz output */
#define BOARD_XOSC32K_EN1K false /* No 1KHz output */ #define BOARD_XOSC32K_EN1K false /* No 1KHz output */
@ -154,100 +154,78 @@
#define BOARD_GCLK0_DIV 1 /* Division factor */ #define BOARD_GCLK0_DIV 1 /* Division factor */
#define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */ #define BOARD_GCLK1_ENABLE true /* Enable GCLK1 */
#define BOARD_GCLK1_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK1_OOV false /* Clock output will be LOW */ #define BOARD_GCLK1_OOV false /* Clock output will be LOW */
#define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK1_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK1_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK1_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */ #define BOARD_GCLK1_SOURCE 6 /* Select DFLL output as GCLK1 source */
#define BOARD_GCLK1_DIV 1 /* Division factor */ #define BOARD_GCLK1_DIV 1 /* Division factor */
#define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */ #define BOARD_GCLK2_ENABLE false /* Don't enable GCLK2 */
#define BOARD_GCLK2_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK2_OOV false /* Clock output will be LOW */ #define BOARD_GCLK2_OOV false /* Clock output will be LOW */
#define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK2_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK2_DIVSEL 1 /* GCLK frequency is source/(2^(N+1) */
#define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK2_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */ #define BOARD_GCLK2_SOURCE 5 /* Select XOSC32K as GCLK2 source */
#define BOARD_GCLK2_DIV 1 /* Division factor */ #define BOARD_GCLK2_DIV 1 /* Division factor */
#define BOARD_GCLK3_ENABLE false /* Don't enable GCLK3 */ #define BOARD_GCLK3_ENABLE true /* Enable GCLK3 */
#define BOARD_GCLK3_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK3_OOV false /* Clock output will be LOW */ #define BOARD_GCLK3_OOV false /* Clock output will be LOW */
#define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK3_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK3_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK3_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */ #define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
#define BOARD_GCLK3_DIV 1 /* Division factor */ #define BOARD_GCLK3_DIV 1 /* Division factor */
#define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */ #define BOARD_GCLK4_ENABLE true /* Enable GCLK4 */
#define BOARD_GCLK4_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK4_OOV false /* Clock output will be LOW */ #define BOARD_GCLK4_OOV false /* Clock output will be LOW */
#define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK4_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK4_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK4_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */ #define BOARD_GCLK4_SOURCE 7 /* Select DPLL0 output as GCLK4 source */
#define BOARD_GCLK4_DIV 1 /* Division factor */ #define BOARD_GCLK4_DIV 1 /* Division factor */
#define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */ #define BOARD_GCLK5_ENABLE true /* Enable GCLK5 */
#define BOARD_GCLK5_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK5_OOV false /* Clock output will be LOW */ #define BOARD_GCLK5_OOV false /* Clock output will be LOW */
#define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */ #define BOARD_GCLK5_OE true /* Generate output on GCLK_IO */
#define BOARD_GCLK5_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK5_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */ #define BOARD_GCLK5_SOURCE 6 /* Select DFLL output as GCLK5 source */
#define BOARD_GCLK5_DIV 24 /* Division factor */ #define BOARD_GCLK5_DIV 24 /* Division factor */
#define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */ #define BOARD_GCLK6_ENABLE false /* Don't enable GCLK6 */
#define BOARD_GCLK6_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK6_OOV false /* Clock output will be LOW */ #define BOARD_GCLK6_OOV false /* Clock output will be LOW */
#define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK6_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK6_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK6_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */ #define BOARD_GCLK6_SOURCE 1 /* Select XOSC1 as GCLK6 source */
#define BOARD_GCLK6_DIV 1 /* Division factor */ #define BOARD_GCLK6_DIV 1 /* Division factor */
#define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */ #define BOARD_GCLK7_ENABLE false /* Don't enable GCLK7 */
#define BOARD_GCLK7_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK7_OOV false /* Clock output will be LOW */ #define BOARD_GCLK7_OOV false /* Clock output will be LOW */
#define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK7_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK7_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK7_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */ #define BOARD_GCLK7_SOURCE 1 /* Select XOSC1 as GCLK7 source */
#define BOARD_GCLK7_DIV 1 /* Division factor */ #define BOARD_GCLK7_DIV 1 /* Division factor */
#define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */ #define BOARD_GCLK8_ENABLE false /* Don't enable GCLK8 */
#define BOARD_GCLK8_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK8_OOV false /* Clock output will be LOW */ #define BOARD_GCLK8_OOV false /* Clock output will be LOW */
#define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK8_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK8_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK8_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */ #define BOARD_GCLK8_SOURCE 1 /* Select XOSC1 as GCLK8 source */
#define BOARD_GCLK8_DIV 1 /* Division factor */ #define BOARD_GCLK8_DIV 1 /* Division factor */
#define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */ #define BOARD_GCLK9_ENABLE false /* Don't enable GCLK9 */
#define BOARD_GCLK9_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK9_OOV false /* Clock output will be LOW */ #define BOARD_GCLK9_OOV false /* Clock output will be LOW */
#define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK9_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK9_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK9_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */ #define BOARD_GCLK9_SOURCE 1 /* Select XOSC1 as GCLK9 source */
#define BOARD_GCLK9_DIV 1 /* Division factor */ #define BOARD_GCLK9_DIV 1 /* Division factor */
#define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */ #define BOARD_GCLK10_ENABLE false /* Don't enable GCLK10 */
#define BOARD_GCLK10_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK10_OOV false /* Clock output will be LOW */ #define BOARD_GCLK10_OOV false /* Clock output will be LOW */
#define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK10_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK10_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK10_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */ #define BOARD_GCLK10_SOURCE 1 /* Select XOSC1 as GCLK10 source */
#define BOARD_GCLK10_DIV 1 /* Division factor */ #define BOARD_GCLK10_DIV 1 /* Division factor */
#define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */ #define BOARD_GCLK11_ENABLE false /* Don't enable GCLK11 */
#define BOARD_GCLK11_IDC false /* Don't improve duty cycle */
#define BOARD_GCLK11_OOV false /* Clock output will be LOW */ #define BOARD_GCLK11_OOV false /* Clock output will be LOW */
#define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */ #define BOARD_GCLK11_OE false /* No generator output of GCLK_IO */
#define BOARD_GCLK11_DIVSEL 0 /* GCLK frequency is source/DIV */
#define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */ #define BOARD_GCLK11_RUNSTDBY false /* Don't run in standby */
#define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */ #define BOARD_GCLK11_SOURCE 1 /* Select XOSC1 as GCLK11 source */
#define BOARD_GCLK11_DIV 1 /* Division factor */ #define BOARD_GCLK11_DIV 1 /* Division factor */