From 26560cb9e1916252b3d35aad6f9aa4e02ba670ae Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 13 Dec 2016 16:59:50 -0600 Subject: [PATCH] i.MX6: Remove non-cached, inter-cpu memory region. Not a useful concept. --- arch/arm/include/armv7-a/spinlock.h | 21 ------ arch/arm/src/armv7-a/mmu.h | 3 - arch/arm/src/common/up_internal.h | 10 --- arch/arm/src/imx6/chip/imx_memorymap.h | 88 +++---------------------- arch/arm/src/imx6/imx_boot.c | 88 ++++--------------------- configs/sabre-6quad/scripts/dramboot.ld | 9 +-- 6 files changed, 22 insertions(+), 197 deletions(-) diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h index f43df337b8..764a96ecef 100644 --- a/arch/arm/include/armv7-a/spinlock.h +++ b/arch/arm/include/armv7-a/spinlock.h @@ -36,25 +36,4 @@ #ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H #define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ -/* Not a useful feature */ - -#undef SMP_INTERCPU_NONCACHED - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* In SMP configurations, save spinlocks and other inter-CPU communications - * data in a non-cached memory region. - */ - -# define SP_SECTION __attribute__((section(".nocache"))) -#endif - #endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */ diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h index 6440657242..c6338d3337 100644 --- a/arch/arm/src/armv7-a/mmu.h +++ b/arch/arm/src/armv7-a/mmu.h @@ -605,9 +605,6 @@ #define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1) #define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS -#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0)) -#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1) - /* Mapped section size */ #define SECTION_SHIFT (20) diff --git a/arch/arm/src/common/up_internal.h b/arch/arm/src/common/up_internal.h index 7318a70caa..36095a87a4 100644 --- a/arch/arm/src/common/up_internal.h +++ b/arch/arm/src/common/up_internal.h @@ -191,11 +191,6 @@ # define _DATA_INIT &_eronly # define _START_DATA &_sdata # define _END_DATA &_edata - -#ifdef CONFIG_SMP -# define _START_NOCACHE &_snocache -# define _END_NOCACHE &_enocache -#endif #endif /* This is the value used to mark the stack for subsequent stack monitoring @@ -284,11 +279,6 @@ EXTERN uint32_t _edata; /* End+1 of .data */ EXTERN uint32_t _sbss; /* Start of .bss */ EXTERN uint32_t _ebss; /* End+1 of .bss */ -#ifdef CONFIG_SMP -EXTERN uint32_t _snocache; /* Start of .nocache */ -EXTERN uint32_t _enocache; /* End+1 of .nocache */ -#endif - /* Sometimes, functions must be executed from RAM. In this case, the following * macro may be used (with GCC!) to specify a function that will execute from * RAM. For example, diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 17304c2474..c9ad19dfdf 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -126,9 +126,7 @@ * address in the top-level memory map are candidates for other mapping uses: * * 00018000-000fffff Reserved -- Not used - * 00400000-007fffff Reserved -- Used as the virtual address an inter-CPU, - * un-cached memory region in SMP - * configurations + * 00400000-007fffff Reserved -- Not used * 00d00000-00ffffff Reserved -- Not used * 0220c000-023fffff Reserved -- Not used * 80000000-efffffff Reserved -- Level 2 page table (See below) @@ -929,8 +927,6 @@ * the address space. */ -#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */ - #ifndef CONFIG_ARCH_LOWVECTORS /* Memory map * VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION @@ -938,10 +934,6 @@ * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB) * 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB) - * - * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES - * pages are taken from the end of the Paging L2 page table to hold non- - * cacheable, inter-processor communication data. */ /* Vector L2 page table offset/size */ @@ -959,18 +951,10 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) -# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Paging L2 page table offset/size */ + /* Paging L2 page table offset/size */ -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001400 - -# else - /* Paging L2 page table offset/size */ - -# define PGTABLE_L2_OFFSET 0x000002400 -# define PGTABLE_L2_SIZE 0x000001800 -# endif +# define PGTABLE_L2_OFFSET 0x000002400 +# define PGTABLE_L2_SIZE 0x000001800 #else /* Memory map @@ -978,24 +962,12 @@ * START END OFFSET SIZE * ---------- ---------- ------------ ---------------------------- * 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB) - * - * If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES - * pages are taken from the end of the Paging L2 page table to hold non- - * cacheable, inter-processor communication data. */ -# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Paging L2 page table offset/size */ -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001800 - -# else - /* Paging L2 page table offset/size */ - -# define PGTABLE_L2_OFFSET 0x000002000 -# define PGTABLE_L2_SIZE 0x000001c00 -# endif +# define PGTABLE_L2_OFFSET 0x000002000 +# define PGTABLE_L2_SIZE 0x000001c00 #endif @@ -1013,23 +985,6 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Non-cached inter-processor communication data */ - -# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) -# define INTERCPU_L2_SIZE (0x00000400) - -/* Non-cached inter-processor communication page table base addresses */ - -# define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET) -# define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET) - -/* Non-cached inter-processor communication end addresses */ - -# define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE) -# define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE) -#endif - /* Base address of the interrupt vector table. * * IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM @@ -1052,8 +1007,7 @@ * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE) - * 0x00010000 0x00011000 Inter-CPU communications - * 0x00011000 0x0003c000 Unused + * 0x00010000 0x0003c000 Unused * 0x0003c000 0x00004000 Page table (PGTABLE_SIZE) */ @@ -1061,27 +1015,13 @@ # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Inter-processor communications. - * - * NOTICE that we use the unused virtual address space at 0x00400000 for - * the inter-CPU virtual communication area. - */ - -# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE) -# define INTERCPU_VADDR (0x00400000) -# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) -# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE) -#endif - #else /* Vectors located at 0xffff:0000 -- this probably does not work */ /* OCRAM Memory Map: * ---------- ---------- --------------------------- * START END CONTENT * ---------- ---------- --------------------------- * 0x00000000 0x00004000 Page table (PGTABLE_SIZE) - * 0x00004000 0x0002f000 Unused - * 0x0002f000 0x00030000 Inter-CPU communications + * 0x00004000 0x00030000 Unused * 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE) */ @@ -1089,18 +1029,6 @@ # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -/* Inter-processor communications - * - * NOTICE that we use the unused virtual address space at 0x00400000 for - * the inter-CPU virtual communication area. - */ - -# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE) -# define INTERCPU_VADDR (0x00400000) -# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12) -# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE) -#endif #endif /************************************************************************************ diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 888baf53ae..6abc6f8b15 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -235,48 +235,6 @@ static void imx_vectormapping(void) # define imx_vectormapping() #endif -/**************************************************************************** - * Name: imx_intercpu_mapping - * - * Description: - * Setup a special mapping for the non-cached, inter-cpu communications - * area. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) -static void imx_intercpu_mapping(void) -{ - uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; - uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK; - uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE; - - DEBUGASSERT(intercpu_vaddr == (uint32_t)&_snocache); - - /* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The - * i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000. - */ - - while (intercpu_paddr < end_paddr) - { - mmu_l2_setentry(INTERCPU_L2_VBASE, intercpu_paddr, intercpu_vaddr, - MMU_L2_INTERCPUFLAGS); - intercpu_paddr += 4096; - intercpu_vaddr += 4096; - } - - /* Now set the level 1 descriptor to refer to the level 2 page table. */ - - mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK, - INTERCPU_VADDR & PMD_PTE_PADDR_MASK, - MMU_L1_INTERCPUFLAGS); -} -#else - /* No inter-cpu communications area */ - -# define imx_intercpu_mapping() -#endif - /**************************************************************************** * Name: imx_copyvectorblock * @@ -477,15 +435,6 @@ void arm_boot(void) imx_vectormapping(); PROGRESS('D'); -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Provide a special mapping for the OCRAM interrupt vector positioned in - * high memory. - */ - - imx_intercpu_mapping(); - PROGRESS('E'); -#endif - #ifdef CONFIG_ARCH_RAMFUNCS /* Copy any necessary code sections from FLASH to RAM. The correct * destination in OCRAM is given by _sramfuncs and _eramfuncs. The @@ -498,14 +447,14 @@ void arm_boot(void) *dest++ = *src++; } - PROGRESS('F'); + PROGRESS('E'); /* Flush the copied RAM functions into physical RAM so that will * be available when fetched into the I-Cache. */ arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs) - PROGRESS('G'); + PROGRESS('F'); #endif /* Setup up vector block. _vector_start and _vector_end are exported from @@ -513,23 +462,23 @@ void arm_boot(void) */ imx_copyvectorblock(); - PROGRESS('H'); + PROGRESS('G'); /* Disable the watchdog timer */ imx_wdtdisable(); - PROGRESS('I'); + PROGRESS('H'); /* Initialize clocking to settings provided by board-specific logic */ imx_clockconfig(); - PROGRESS('J'); + PROGRESS('I'); #ifdef CONFIG_ARCH_FPU /* Initialize the FPU */ arm_fpuconfig(); - PROGRESS('K'); + PROGRESS('J'); #endif /* Perform board-specific memroy initialization, This must include @@ -541,7 +490,7 @@ void arm_boot(void) */ imx_memory_initialize(); - PROGRESS('L'); + PROGRESS('K'); #ifdef NEED_SDRAM_REMAPPING /* SDRAM was configured in a temporary state to support low-level @@ -550,7 +499,7 @@ void arm_boot(void) */ imx_remap(); - PROGRESS('M'); + PROGRESS('L'); #endif #ifdef CONFIG_BOOT_SDRAM_DATA @@ -559,7 +508,7 @@ void arm_boot(void) */ arm_data_initialize(); - PROGRESS('N'); + PROGRESS('M'); #endif /* Perform board-specific device initialization. This would include @@ -567,23 +516,12 @@ void arm_boot(void) */ imx_board_initialize(); - PROGRESS('O'); - -#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) - /* Initialize the uncached, inter-CPU communications area */ - - for (dest = &_snocache; dest < &_enocache; ) - { - *dest++ = 0; - } - - PROGRESS('P'); -#endif + PROGRESS('N'); /* Perform common, low-level chip initialization (might do nothing) */ imx_lowsetup(); - PROGRESS('Q'); + PROGRESS('O'); #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization if we are going to use the serial @@ -591,7 +529,7 @@ void arm_boot(void) */ imx_earlyserialinit(); - PROGRESS('R'); + PROGRESS('P'); #endif /* Now we can enable all other CPUs. The enabled CPUs will start execution @@ -600,6 +538,6 @@ void arm_boot(void) */ imx_cpu_enable(); - PROGRESS('S'); + PROGRESS('Q'); PROGRESS('\n'); } diff --git a/configs/sabre-6quad/scripts/dramboot.ld b/configs/sabre-6quad/scripts/dramboot.ld index da35b396aa..a5d696c5ce 100644 --- a/configs/sabre-6quad/scripts/dramboot.ld +++ b/configs/sabre-6quad/scripts/dramboot.ld @@ -44,7 +44,6 @@ MEMORY { - nocache (WR) : ORIGIN = 0x00400000, LENGTH = 4K oscram (W!RX) : ORIGIN = 0x00900000, LENGTH = 256K - 16K ddr3 (W!RX) : ORIGIN = 0x10800000, LENGTH = 1024M - 8M } @@ -123,14 +122,8 @@ SECTIONS _enoinit = ABSOLUTE(.); } > ddr3 - .nocache : - { - _snocache = ABSOLUTE(.); - *(.nocache) - _enocache = ABSOLUTE(.); - } > nocache - /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } .stabstr 0 : { *(.stabstr) } .stab.excl 0 : { *(.stab.excl) }