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The M3 Wildfire port is code complete and ready for test

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5125 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-09-10 22:26:37 +00:00
parent 4f6b756bc2
commit 267eb76ea9
6 changed files with 75 additions and 17 deletions
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4
arch/Kconfig
View File

@ -107,6 +107,10 @@ config ARCH_NOINTC
bool
default n
config ARCH_DMA
bool
default n
config ARCH_STACKDUMP
bool "Dump stack on assertions"
default n

77
arch/arm/src/stm32/Kconfig
View File

@ -10,20 +10,64 @@ choice
default ARCH_CHIP_STM32F103ZET6
depends on ARCH_CHIP_STM32
config ARCH_CHIP_STM32F103ZET6
bool "STM32F103ZET6"
config ARCH_CHIP_STM32F100C8
bool "STM32F100C8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100CB
bool "STM32F100CB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100R8
bool "STM32F100R8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100RB
bool "STM32F100RB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100V8
bool "STM32F100V8"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F100VB
bool "STM32F100VB"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_VALUELINE
config ARCH_CHIP_STM32F103RET6
bool "STM32F103RET6"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103VCT6
bool "STM32F103VCT6"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103VET6
bool "STM32F103VET6"
select ARCH_CORTEXM3
select STM32_STM32F10XX
select STM32_HIGHDENSITY
config ARCH_CHIP_STM32F103ZET6
bool "STM32F103ZET6"
select ARCH_CORTEXM3
select STM32_STM32F10XX
config ARCH_CHIP_STM32F105VBT7
bool "STM32F105VBT7"
@ -92,6 +136,12 @@ endchoice
config STM32_STM32F10XX
bool
config STM32_VALUELINE
bool
config STM32_HIGHDENSITY
bool
config STM32_CONNECTIVITYLINE
bool
@ -157,10 +207,12 @@ config STM32_CRC
config STM32_DMA1
bool "DMA1"
default n
select ARCH_DMA
config STM32_DMA2
bool "DMA2"
default n
select ARCH_DMA
config STM32_BKP
bool "BKP"
@ -408,10 +460,6 @@ config STM32_SPI
bool
default y if STM32_SPI1 || STM32_SPI2 || STM32_SPI3 || STM32_SPI4
config STM32_DMA
bool
default y if STM32_DMA1 || STM32_DMA2
config STM32_CAN
bool
default y if STM32_CAN1 || STM32_CAN2
@ -580,7 +628,7 @@ config ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
config STM32_CCMEXCLUDE
bool "Exclude CCM SRAM from the heap"
depends on STM32_STM32F20XX || STM32_STM32F40XX
default y if STM32_DMA1 || STM32_DMA2
default y if ARCH_DMA
---help---
Exclude CCM SRAM from the HEAP because it cannot be used for DMA.
@ -1485,42 +1533,42 @@ endchoice
config USART1_RXDMA
bool "USART1 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA2
depends on STM32_STM32F40XX && STM32_DMA2
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART2_RXDMA
bool "USART2 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA1
depends on STM32_STM32F40XX && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART3_RXDMA
bool "USART3 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA1
depends on STM32_STM32F40XX && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART4_RXDMA
bool "UART4 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA1
depends on STM32_STM32F40XX && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config UART5_RXDMA
bool "UART5 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA1
depends on STM32_STM32F40XX && STM32_DMA1
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
config USART6_RXDMA
bool "USART6 Rx DMA"
default n
depends on STM32_STM32F40XX && ARCH_DMA && STM32_DMA2
depends on STM32_STM32F40XX && STM32_DMA2
---help---
In high data rate usage, Rx DMA may eliminate Rx overrun errors
@ -1587,8 +1635,9 @@ menu "Ethernet MAC configuration"
config STM32_PHYADDR
int "PHY address"
default 1
---help---
The 5-bit address of the PHY on the board
The 5-bit address of the PHY on the board. Default: 1
config STM32_MII
bool "Use MII interface"

4
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -212,7 +212,7 @@
* should be 3.
*/
# ifdef CONFIG_STM32_DMA
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS != 3
@ -238,7 +238,7 @@
* should be disabled and CONFIG_MM_REGIONS should be 2.
*/
# ifdef CONFIG_STM32_DMA
# ifdef CONFIG_ARCH_DMA
# warning "CCM SRAM is included in the heap AND DMA is enabled"
# endif
# if CONFIG_MM_REGIONS < 2

2
arch/arm/src/stm32/stm32_pwr.c
View File

@ -95,4 +95,4 @@ void stm32_pwr_enablebkp(void)
stm32_pwr_modifyreg(STM32_PWR_CR_OFFSET, 0, PWR_CR_DBP);
}
#endif // defined(CONFIG_STM32_PWR)
#endif /* CONFIG_STM32_PWR */

4
arch/arm/src/stm32/stm32f10xxx_rtc.c
View File

@ -113,6 +113,10 @@
# error "CONFIG_STM32_BKP is required for CONFIG_RTC"
#endif
#ifndef CONFIG_STM32_PWR
# error "CONFIG_STM32_PWR is required for CONFIG_RTC"
#endif
/* RTC/BKP Definitions *************************************************************/
/* STM32_RTC_PRESCALAR_VALUE
* RTC pre-scalar value. The RTC is driven by a 32,768Hz input clock. This input

1
arch/mips/src/pic32mx/Kconfig
View File

@ -544,6 +544,7 @@ config PIC32MX_RTCC
config PIC32MX_DMA
bool "DMA"
default n
select ARCH_DMA
config PIC32MX_FLASH
bool "FLASH"