diff --git a/arch/arm/src/stm32f7/stm32_sai.c b/arch/arm/src/stm32f7/stm32_sai.c index 7d5175bbbc..ba1f9b0a90 100644 --- a/arch/arm/src/stm32f7/stm32_sai.c +++ b/arch/arm/src/stm32f7/stm32_sai.c @@ -152,7 +152,7 @@ DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) # define SAI_TXDMA8_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ - DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ + DMA_SCR_PSIZE_8BITS | DMA_SCR_MSIZE_8BITS | \ DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) # define SAI_TXDMA16_CONFIG (DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ DMA_SCR_PSIZE_16BITS | DMA_SCR_MSIZE_16BITS | \ diff --git a/boards/arm/stm32f7/stm32f746g-disco/include/board.h b/boards/arm/stm32f7/stm32f746g-disco/include/board.h index cde768f798..409ad5650a 100644 --- a/boards/arm/stm32f7/stm32f746g-disco/include/board.h +++ b/boards/arm/stm32f7/stm32f746g-disco/include/board.h @@ -150,12 +150,12 @@ /* SAIx input frequency = 25 / M * N / Q / P * 25000000 / 25 * 192 / 2 / 1 */ -#define STM32F7_SAI1_FREQUENCY (96000000) -#define STM32F7_SAI2_FREQUENCY (96000000) +#define STM32F7_SAI1_FREQUENCY (49142857) +#define STM32F7_SAI2_FREQUENCY (49142857) /* Configure Dedicated Clock Configuration Register */ -#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1) +#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(0) #define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(0) #define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(1) #define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(1) @@ -167,9 +167,9 @@ /* Configure factors for PLLI2S clock */ #define CONFIG_STM32F7_PLLI2S 1 -#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192) +#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(344) #define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2) -#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2) +#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(7) #define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2) /* Configure Dedicated Clock Configuration Register 2 */ diff --git a/drivers/audio/wm8994.c b/drivers/audio/wm8994.c index a7bed7d542..8dee844bb7 100644 --- a/drivers/audio/wm8994.c +++ b/drivers/audio/wm8994.c @@ -340,7 +340,7 @@ static void wm8994_writereg(FAR struct wm8994_dev_s *priv, uint16_t regaddr, * completed. */ - ret = i2c_write(priv->i2c, &config, data, 3); + ret = i2c_write(priv->i2c, &config, data, 4); if (ret < 0) { #ifdef CONFIG_I2C_RESET @@ -1964,7 +1964,7 @@ static void wm8994_audio_output(FAR struct wm8994_dev_s *priv) * 256 works from 8kHz to 48kHz. */ - wm8994_setsamplefreq (priv); + wm8994_setbitrate(priv); /* AIF1 Word Length = 16-bits, AIF1 Format = I2S (Default Register Value) */ @@ -2082,8 +2082,8 @@ static void wm8994_audio_output(FAR struct wm8994_dev_s *priv) /* Enable Class W, Class W Envelope Tracking = AIF1 Timeslot 0 */ - regval = WM8994_CP_DYN_PWR; - regval = 0x0005; /* TODO: Check where this comes from? */ + regval = wm8994_readreg(priv, WM8994_CLASS_W_1); + regval |= WM8994_CP_DYN_PWR; wm8994_writereg(priv, WM8994_CLASS_W_1, regval); } @@ -2118,9 +2118,14 @@ static void wm8994_audio_output(FAR struct wm8994_dev_s *priv) WM8994_HPOUT1R_DLY; wm8994_writereg(priv, WM8994_ANA_HP1, regval); - /* Enable Charge Pump */ + /* Enable Charge Pump + * Note: The STM32Cube_FW_F7_V1.16.0 BSP driver included the + * number 9F25h as write value for this register. This is the + * default value + CP_ENA set. + */ - regval = WM8994_CP_ENA; + regval = wm8994_readreg(priv, WM8994_CHARGE_PUMP1); + regval |= WM8994_CP_ENA; wm8994_writereg(priv, WM8994_CHARGE_PUMP1, regval); /* Add Delay */ @@ -2320,9 +2325,14 @@ static void wm8994_hw_reset(FAR struct wm8994_dev_s *priv) /* wm8994 Errata Work-Arounds */ - /* copy code from STM32Cube_FW_F7_V1.15.0 */ + /* Note: Initially from STM32Cube_FW_F7_V1.15.0. + * The write to 0x56 comes from Linux (drivers/mfd/wm8994-core.c), + * where it is found for wm8994_revc_patch. Neither + * register 0x56 nor 0x817 is documented. + */ wm8994_writereg(priv, 0x102, 0x0003); + wm8994_writereg(priv, 0x56, 0x0003); wm8994_writereg(priv, 0x817, 0x0000); wm8994_writereg(priv, 0x102, 0x0000); diff --git a/drivers/audio/wm8994.h b/drivers/audio/wm8994.h index c2a391122d..0a2ecffc55 100644 --- a/drivers/audio/wm8994.h +++ b/drivers/audio/wm8994.h @@ -663,9 +663,9 @@ #define WM8994_HPOUT1R_ZC_DIABLED (0) /* Zero cross disabled */ #define WM8994_HPOUT1R_ZC_ENABLED (1 << WM8994_HPOUT1R_ZC_SHIFT) /* Zero cross enabled */ #if 0 -#define WM8994_HPOUT1_VU_SHIFT (1 << 8) /* Bit 8: Headphone Output PGA Volume Update */ -#define WM8994_HPOUT1_VU_DISABLE (0) -#define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1L_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and +#define WM8994_HPOUT1_VU_SHIFT (8) /* Bit 8: Headphone Output PGA Volume Update */ +#define WM8994_HPOUT1_VU_DISABLE (0) +#define WM8994_HPOUT1_VU_ENABLED (1 << WM8994_HPOUT1_VU_SHIFT) /* Writing a 1 to this bit will update HPOUT1LVOL and * HPOUT1RVOL volumes simultaneously */ #endif @@ -805,6 +805,7 @@ /* R54 (0x36) - Speaker Mixer */ + #define WM8994_DAC2L_TO_SPKMIXL (1 << 9) /* Bit 9: Left DAC2 to SPKMXL Mute */ #define WM8994_DAC2L_TO_SPKMIXL_MUTE (0) /* Mute */ #define WM8994_DAC2L_TO_SPKMIXL_UNMUTE (WM8994_DAC2L_TO_SPKMIXL) /* Un-mute */ @@ -962,7 +963,7 @@ #define WM8994_DCS_ENA_CHAN_1_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */ #define WM8994_DCS_ENA_CHAN_0 (1 << 0) /* Bit 0: DC Servo enable for HPOUT1L */ #define WM8994_DCS_ENA_CHAN_0_DISABLE (0) /* Diable */ -#define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_1) /* Enable */ +#define WM8994_DCS_ENA_CHAN_0_ENABLE (WM8994_DCS_ENA_CHAN_0) /* Enable */ /* R85 (0x55) - DC Servo (2) */