Cosmetic changes to conditional compilation
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@ -92,6 +92,11 @@
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# define CONFIG_SAMV7_NLLDESC SAMV7_NDMACHAN
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#endif
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/* These cache operations are not yet available */
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#undef HAVE_CLEAN_DCACHE_RANGE
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#undef HAVE_INVALIDATE_DCACHE_RANGE
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -1086,7 +1091,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
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xdmach->lltail = descr;
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#if 0 /* REVISIT */
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#ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
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/* Assume that we will be doing multiple buffer transfers and that
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* that hardware will be accessing the descriptor via DMA.
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*/
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@ -1098,7 +1103,7 @@ sam_allocdesc(struct sam_xdmach_s *xdmach, struct chnext_view1_s *prev,
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}
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}
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#if 1 /* REVISIT */
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#ifndef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
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/* Assume that we will be doing multiple buffer transfers and that
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* that hardware will be accessing the descriptors via DMA.
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*/
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@ -1502,7 +1507,7 @@ static void sam_dmaterminate(struct sam_xdmach_s *xdmach, int result)
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* to force reloads from memory.
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*/
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#if 0 /* Revisit */
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#ifdef HAVE_INVALIDATE_DCACHE_RANGE /* Revisit */
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if (xdmach->rx)
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{
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arch_invalidate_dcache(xdmach->rxaddr, xdmach->rxaddr + xdmach->rxsize);
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@ -1868,7 +1873,7 @@ int sam_dmatxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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/* Clean caches associated with the DMA memory */
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#if 0 /* REVISIT */
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#ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
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arch_clean_dcache(maddr, maddr + nbytes);
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#else
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arch_clean_dcache_all();
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@ -1953,7 +1958,7 @@ int sam_dmarxsetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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/* Clean caches associated with the DMA memory */
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#if 0 /* REVISIT */
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#ifdef HAVE_CLEAN_DCACHE_RANGE /* REVISIT */
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arch_clean_dcache(maddr, maddr + nbytes);
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#else
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arch_clean_dcache_all();
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