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Lok Tep
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@ -78,9 +78,6 @@
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#define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */
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#define STM32_OTG_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2))
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#define STM32_OTG_DIEPTXF1_OFFSET 0x0104 /* Device IN endpoint transmit FIFO1 size register */
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#define STM32_OTG_DIEPTXF2_OFFSET 0x0108 /* Device IN endpoint transmit FIFO2 size register */
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#define STM32_OTG_DIEPTXF3_OFFSET 0x010c /* Device IN endpoint transmit FIFO3 size register */
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/* Host-mode control and status registers */
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@ -99,44 +96,12 @@
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#define STM32_OTG_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */
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#define STM32_OTG_HCCHAR_OFFSET(n) (0x500 + ((n) << 5))
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#define STM32_OTG_HCCHAR0_OFFSET 0x0500 /* Host channel-0 characteristics register */
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#define STM32_OTG_HCCHAR1_OFFSET 0x0520 /* Host channel-1 characteristics register */
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#define STM32_OTG_HCCHAR2_OFFSET 0x0540 /* Host channel-2 characteristics register */
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#define STM32_OTG_HCCHAR3_OFFSET 0x0560 /* Host channel-3 characteristics register */
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#define STM32_OTG_HCCHAR4_OFFSET 0x0580 /* Host channel-4 characteristics register */
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#define STM32_OTG_HCCHAR5_OFFSET 0x05a0 /* Host channel-5 characteristics register */
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#define STM32_OTG_HCCHAR6_OFFSET 0x05c0 /* Host channel-6 characteristics register */
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#define STM32_OTG_HCCHAR7_OFFSET 0x05e0 /* Host channel-7 characteristics register */
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#define STM32_OTG_HCINT_OFFSET(n) (0x508 + ((n) << 5))
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#define STM32_OTG_HCINT0_OFFSET 0x0508 /* Host channel-0 interrupt register */
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#define STM32_OTG_HCINT1_OFFSET 0x0528 /* Host channel-1 interrupt register */
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#define STM32_OTG_HCINT2_OFFSET 0x0548 /* Host channel-2 interrupt register */
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#define STM32_OTG_HCINT3_OFFSET 0x0568 /* Host channel-3 interrupt register */
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#define STM32_OTG_HCINT4_OFFSET 0x0588 /* Host channel-4 interrupt register */
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#define STM32_OTG_HCINT5_OFFSET 0x05a8 /* Host channel-5 interrupt register */
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#define STM32_OTG_HCINT6_OFFSET 0x05c8 /* Host channel-6 interrupt register */
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#define STM32_OTG_HCINT7_OFFSET 0x05e8 /* Host channel-7 interrupt register */
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#define STM32_OTG_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5))
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#define STM32_OTG_HCINTMSK0_OFFSET 0x050c /* Host channel-0 interrupt mask register */
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#define STM32_OTG_HCINTMSK1_OFFSET 0x052c /* Host channel-1 interrupt mask register */
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#define STM32_OTG_HCINTMSK2_OFFSET 0x054c /* Host channel-2 interrupt mask register */
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#define STM32_OTG_HCINTMSK3_OFFSET 0x056c /* Host channel-3 interrupt mask register */
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#define STM32_OTG_HCINTMSK4_OFFSET 0x058c /* Host channel-4 interrupt mask register */
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#define STM32_OTG_HCINTMSK5_OFFSET 0x05ac /* Host channel-5 interrupt mask register */
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#define STM32_OTG_HCINTMSK6_OFFSET 0x05cc /* Host channel-6 interrupt mask register */
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#define STM32_OTG_HCINTMSK7_OFFSET 0x05ec /* Host channel-7 interrupt mask register */
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#define STM32_OTG_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5))
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#define STM32_OTG_HCTSIZ0_OFFSET 0x0510 /* Host channel-0 interrupt register */
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#define STM32_OTG_HCTSIZ1_OFFSET 0x0530 /* Host channel-1 interrupt register */
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#define STM32_OTG_HCTSIZ2_OFFSET 0x0550 /* Host channel-2 interrupt register */
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#define STM32_OTG_HCTSIZ3_OFFSET 0x0570 /* Host channel-3 interrupt register */
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#define STM32_OTG_HCTSIZ4_OFFSET 0x0590 /* Host channel-4 interrupt register */
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#define STM32_OTG_HCTSIZ5_OFFSET 0x05b0 /* Host channel-5 interrupt register */
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#define STM32_OTG_HCTSIZ6_OFFSET 0x05d0 /* Host channel-6 interrupt register */
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#define STM32_OTG_HCTSIZ7_OFFSET 0x05f0 /* Host channel-7 interrupt register */
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/* Device-mode control and status registers */
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@ -158,50 +123,22 @@
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#define STM32_OTG_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */
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#define STM32_OTG_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5))
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#define STM32_OTG_DIEPCTL0_OFFSET 0x0900 /* Device control IN endpoint 0 control register */
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#define STM32_OTG_DIEPCTL1_OFFSET 0x0920 /* Device control IN endpoint 2 control register */
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#define STM32_OTG_DIEPCTL2_OFFSET 0x0940 /* Device control IN endpoint 3 control register */
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#define STM32_OTG_DIEPCTL3_OFFSET 0x0960 /* Device control IN endpoint 4 control register */
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#define STM32_OTG_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5))
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#define STM32_OTG_DIEPINT0_OFFSET 0x0908 /* Device endpoint-0 interrupt register */
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#define STM32_OTG_DIEPINT1_OFFSET 0x0928 /* Device endpoint-1 interrupt register */
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#define STM32_OTG_DIEPINT2_OFFSET 0x0948 /* Device endpoint-2 interrupt register */
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#define STM32_OTG_DIEPINT3_OFFSET 0x0968 /* Device endpoint-3 interrupt register */
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#define STM32_OTG_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5))
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#define STM32_OTG_DIEPTSIZ0_OFFSET 0x0910 /* Device IN endpoint 0 transfer size register */
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#define STM32_OTG_DIEPTSIZ1_OFFSET 0x0930 /* Device IN endpoint 1 transfer size register */
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#define STM32_OTG_DIEPTSIZ2_OFFSET 0x0950 /* Device IN endpoint 2 transfer size register */
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#define STM32_OTG_DIEPTSIZ3_OFFSET 0x0970 /* Device IN endpoint 3 transfer size register */
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#define STM32_OTG_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5))
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#define STM32_OTG_DTXFSTS0_OFFSET 0x0918 /* Device OUT endpoint-0 TxFIFO status register */
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#define STM32_OTG_DTXFSTS1_OFFSET 0x0938 /* Device OUT endpoint-1 TxFIFO status register */
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#define STM32_OTG_DTXFSTS2_OFFSET 0x0958 /* Device OUT endpoint-2 TxFIFO status register */
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#define STM32_OTG_DTXFSTS3_OFFSET 0x0978 /* Device OUT endpoint-3 TxFIFO status register */
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#define STM32_OTG_DOEP_OFFSET(n) (0x0b00 + ((n) << 5))
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#define STM32_OTG_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */
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#define STM32_OTG_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */
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#define STM32_OTG_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5))
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#define STM32_OTG_DOEPCTL0_OFFSET 0x00b00 /* Device OUT endpoint 0 control register */
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#define STM32_OTG_DOEPCTL1_OFFSET 0x00b20 /* Device OUT endpoint 1 control register */
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#define STM32_OTG_DOEPCTL2_OFFSET 0x00b40 /* Device OUT endpoint 2 control register */
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#define STM32_OTG_DOEPCTL3_OFFSET 0x00b60 /* Device OUT endpoint 3 control register */
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#define STM32_OTG_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5))
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#define STM32_OTG_DOEPINT0_OFFSET 0x00b08 /* Device endpoint-0 interrupt register */
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#define STM32_OTG_DOEPINT1_OFFSET 0x00b28 /* Device endpoint-1 interrupt register */
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#define STM32_OTG_DOEPINT2_OFFSET 0x00b48 /* Device endpoint-2 interrupt register */
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#define STM32_OTG_DOEPINT3_OFFSET 0x00b68 /* Device endpoint-3 interrupt register */
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#define STM32_OTG_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5))
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#define STM32_OTG_DOEPTSIZ0_OFFSET 0x00b10 /* Device OUT endpoint-0 transfer size register */
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#define STM32_OTG_DOEPTSIZ1_OFFSET 0x00b30 /* Device OUT endpoint-1 transfer size register */
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#define STM32_OTG_DOEPTSIZ2_OFFSET 0x00b50 /* Device OUT endpoint-2 transfer size register */
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#define STM32_OTG_DOEPTSIZ3_OFFSET 0x00b70 /* Device OUT endpoint-3 transfer size register */
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/* Power and clock gating registers */
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@ -212,17 +149,6 @@
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#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12))
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#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12))
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#define STM32_OTG_DFIFO_DEP0_OFFSET 0x1000 /* 0x1000-0x1ffc Device IN/OUT Endpoint 0 DFIFO Write/Read Access */
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#define STM32_OTG_DFIFO_HCH0_OFFSET 0x1000 /* 0x1000-0x1ffc Host OUT/IN Channel 0 DFIFO Read/Write Access */
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#define STM32_OTG_DFIFO_DEP1_OFFSET 0x2000 /* 0x2000-0x2ffc Device IN/OUT Endpoint 1 DFIFO Write/Read Access */
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#define STM32_OTG_DFIFO_HCH1_OFFSET 0x2000 /* 0x2000-0x2ffc Host OUT/IN Channel 1 DFIFO Read/Write Access */
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#define STM32_OTG_DFIFO_DEP2_OFFSET 0x3000 /* 0x3000-0x3ffc Device IN/OUT Endpoint 2 DFIFO Write/Read Access */
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#define STM32_OTG_DFIFO_HCH2_OFFSET 0x3000 /* 0x3000-0x3ffc Host OUT/IN Channel 2 DFIFO Read/Write Access */
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#define STM32_OTG_DFIFO_DEP3_OFFSET 0x4000 /* 0x4000-0x4ffc Device IN/OUT Endpoint 3 DFIFO Write/Read Access */
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#define STM32_OTG_DFIFO_HCH3_OFFSET 0x4000 /* 0x4000-0x4ffc Host OUT/IN Channel 3 DFIFO Read/Write Access */
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/* Register Addresses *******************************************************************************/
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@ -244,9 +170,6 @@
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#define STM32_OTG_HPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HPTXFSIZ_OFFSET)
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#define STM32_OTG_DIEPTXF(n) (STM32_OTG_BASE+STM32_OTG_DIEPTXF_OFFSET(n))
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#define STM32_OTG_DIEPTXF1 (STM32_OTG_BASE+STM32_OTG_DIEPTXF1_OFFSET)
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#define STM32_OTG_DIEPTXF2 (STM32_OTG_BASE+STM32_OTG_DIEPTXF2_OFFSET)
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#define STM32_OTG_DIEPTXF3 (STM32_OTG_BASE+STM32_OTG_DIEPTXF3_OFFSET)
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/* Host-mode control and status registers */
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@ -261,44 +184,12 @@
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#define STM32_OTG_CHAN(n) (STM32_OTG_BASE+STM32_OTG_CHAN_OFFSET(n))
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#define STM32_OTG_HCCHAR(n) (STM32_OTG_BASE+STM32_OTG_HCCHAR_OFFSET(n))
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#define STM32_OTG_HCCHAR0 (STM32_OTG_BASE+STM32_OTG_HCCHAR0_OFFSET)
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#define STM32_OTG_HCCHAR1 (STM32_OTG_BASE+STM32_OTG_HCCHAR1_OFFSET)
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#define STM32_OTG_HCCHAR2 (STM32_OTG_BASE+STM32_OTG_HCCHAR2_OFFSET)
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#define STM32_OTG_HCCHAR3 (STM32_OTG_BASE+STM32_OTG_HCCHAR3_OFFSET)
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#define STM32_OTG_HCCHAR4 (STM32_OTG_BASE+STM32_OTG_HCCHAR4_OFFSET)
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#define STM32_OTG_HCCHAR5 (STM32_OTG_BASE+STM32_OTG_HCCHAR5_OFFSET)
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#define STM32_OTG_HCCHAR6 (STM32_OTG_BASE+STM32_OTG_HCCHAR6_OFFSET)
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#define STM32_OTG_HCCHAR7 (STM32_OTG_BASE+STM32_OTG_HCCHAR7_OFFSET)
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#define STM32_OTG_HCINT(n) (STM32_OTG_BASE+STM32_OTG_HCINT_OFFSET(n))
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#define STM32_OTG_HCINT0 (STM32_OTG_BASE+STM32_OTG_HCINT0_OFFSET)
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#define STM32_OTG_HCINT1 (STM32_OTG_BASE+STM32_OTG_HCINT1_OFFSET)
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#define STM32_OTG_HCINT2 (STM32_OTG_BASE+STM32_OTG_HCINT2_OFFSET)
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#define STM32_OTG_HCINT3 (STM32_OTG_BASE+STM32_OTG_HCINT3_OFFSET)
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#define STM32_OTG_HCINT4 (STM32_OTG_BASE+STM32_OTG_HCINT4_OFFSET)
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#define STM32_OTG_HCINT5 (STM32_OTG_BASE+STM32_OTG_HCINT5_OFFSET)
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#define STM32_OTG_HCINT6 (STM32_OTG_BASE+STM32_OTG_HCINT6_OFFSET)
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#define STM32_OTG_HCINT7 (STM32_OTG_BASE+STM32_OTG_HCINT7_OFFSET)
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#define STM32_OTG_HCINTMSK(n) (STM32_OTG_BASE+STM32_OTG_HCINTMSK_OFFSET(n))
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#define STM32_OTG_HCINTMSK0 (STM32_OTG_BASE+STM32_OTG_HCINTMSK0_OFFSET)
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#define STM32_OTG_HCINTMSK1 (STM32_OTG_BASE+STM32_OTG_HCINTMSK1_OFFSET)
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#define STM32_OTG_HCINTMSK2 (STM32_OTG_BASE+STM32_OTG_HCINTMSK2_OFFSET)
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#define STM32_OTG_HCINTMSK3 (STM32_OTG_BASE+STM32_OTG_HCINTMSK3_OFFSET)
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#define STM32_OTG_HCINTMSK4 (STM32_OTG_BASE+STM32_OTG_HCINTMSK4_OFFSET)
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#define STM32_OTG_HCINTMSK5 (STM32_OTG_BASE+STM32_OTG_HCINTMSK5_OFFSET)
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#define STM32_OTG_HCINTMSK6 (STM32_OTG_BASE+STM32_OTG_HCINTMSK6_OFFSET)
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#define STM32_OTG_HCINTMSK7 (STM32_OTG_BASE+STM32_OTG_HCINTMSK7_OFFSET)_
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#define STM32_OTG_HCTSIZ(n) (STM32_OTG_BASE+STM32_OTG_HCTSIZ_OFFSET(n))
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#define STM32_OTG_HCTSIZ0 (STM32_OTG_BASE+STM32_OTG_HCTSIZ0_OFFSET)
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#define STM32_OTG_HCTSIZ1 (STM32_OTG_BASE+STM32_OTG_HCTSIZ1_OFFSET)
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#define STM32_OTG_HCTSIZ2 (STM32_OTG_BASE+STM32_OTG_HCTSIZ2_OFFSET)
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#define STM32_OTG_HCTSIZ3 (STM32_OTG_BASE+STM32_OTG_HCTSIZ3_OFFSET)
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#define STM32_OTG_HCTSIZ4 (STM32_OTG_BASE+STM32_OTG_HCTSIZ4_OFFSET)
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#define STM32_OTG_HCTSIZ5 (STM32_OTG_BASE+STM32_OTG_HCTSIZ5_OFFSET)
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#define STM32_OTG_HCTSIZ6 (STM32_OTG_BASE+STM32_OTG_HCTSIZ6_OFFSET)
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#define STM32_OTG_HCTSIZ7 (STM32_OTG_BASE+STM32_OTG_HCTSIZ7_OFFSET)
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/* Device-mode control and status registers */
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@ -316,48 +207,20 @@
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#define STM32_OTG_DIEP(n) (STM32_OTG_BASE+STM32_OTG_DIEP_OFFSET(n))
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#define STM32_OTG_DIEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DIEPCTL_OFFSET(n))
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#define STM32_OTG_DIEPCTL0 (STM32_OTG_BASE+STM32_OTG_DIEPCTL0_OFFSET)
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#define STM32_OTG_DIEPCTL1 (STM32_OTG_BASE+STM32_OTG_DIEPCTL1_OFFSET)
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#define STM32_OTG_DIEPCTL2 (STM32_OTG_BASE+STM32_OTG_DIEPCTL2_OFFSET)
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#define STM32_OTG_DIEPCTL3 (STM32_OTG_BASE+STM32_OTG_DIEPCTL3_OFFSET)
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#define STM32_OTG_DIEPINT(n) (STM32_OTG_BASE+STM32_OTG_DIEPINT_OFFSET(n))
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#define STM32_OTG_DIEPINT0 (STM32_OTG_BASE+STM32_OTG_DIEPINT0_OFFSET)
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#define STM32_OTG_DIEPINT1 (STM32_OTG_BASE+STM32_OTG_DIEPINT1_OFFSET)
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#define STM32_OTG_DIEPINT2 (STM32_OTG_BASE+STM32_OTG_DIEPINT2_OFFSET)
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#define STM32_OTG_DIEPINT3 (STM32_OTG_BASE+STM32_OTG_DIEPINT3_OFFSET)
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#define STM32_OTG_DIEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ_OFFSET(n))
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#define STM32_OTG_DIEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ0_OFFSET)
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#define STM32_OTG_DIEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ1_OFFSET)
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#define STM32_OTG_DIEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ2_OFFSET)
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#define STM32_OTG_DIEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ3_OFFSET)
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#define STM32_OTG_DTXFSTS(n) (STM32_OTG_BASE+STM32_OTG_DTXFSTS_OFFSET(n))
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#define STM32_OTG_DTXFSTS0 (STM32_OTG_BASE+STM32_OTG_DTXFSTS0_OFFSET)
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#define STM32_OTG_DTXFSTS1 (STM32_OTG_BASE+STM32_OTG_DTXFSTS1_OFFSET)
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#define STM32_OTG_DTXFSTS2 (STM32_OTG_BASE+STM32_OTG_DTXFSTS2_OFFSET)
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#define STM32_OTG_DTXFSTS3 (STM32_OTG_BASE+STM32_OTG_DTXFSTS3_OFFSET)
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#define STM32_OTG_DOEP(n) (STM32_OTG_BASE+STM32_OTG_DOEP_OFFSET(n))
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#define STM32_OTG_DOEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DOEPCTL_OFFSET(n))
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#define STM32_OTG_DOEPCTL0 (STM32_OTG_BASE+STM32_OTG_DOEPCTL0_OFFSET)
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#define STM32_OTG_DOEPCTL1 (STM32_OTG_BASE+STM32_OTG_DOEPCTL1_OFFSET)
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#define STM32_OTG_DOEPCTL2 (STM32_OTG_BASE+STM32_OTG_DOEPCTL2_OFFSET)
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#define STM32_OTG_DOEPCTL3 (STM32_OTG_BASE+STM32_OTG_DOEPCTL3_OFFSET)
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#define STM32_OTG_DOEPINT(n) (STM32_OTG_BASE+STM32_OTG_DOEPINT_OFFSET(n))
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#define STM32_OTG_DOEPINT0 (STM32_OTG_BASE+STM32_OTG_DOEPINT0_OFFSET)
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#define STM32_OTG_DOEPINT1 (STM32_OTG_BASE+STM32_OTG_DOEPINT1_OFFSET)
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#define STM32_OTG_DOEPINT2 (STM32_OTG_BASE+STM32_OTG_DOEPINT2_OFFSET)
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#define STM32_OTG_DOEPINT3 (STM32_OTG_BASE+STM32_OTG_DOEPINT3_OFFSET)
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#define STM32_OTG_DOEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ_OFFSET(n))
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#define STM32_OTG_DOEPTSIZ0 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ0_OFFSET)
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#define STM32_OTG_DOEPTSIZ1 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ1_OFFSET)
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#define STM32_OTG_DOEPTSIZ2 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ2_OFFSET)
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#define STM32_OTG_DOEPTSIZ3 (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ3_OFFSET)
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/* Power and clock gating registers */
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#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n))
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#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n))
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#define STM32_OTG_DFIFO_DEP0 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP0_OFFSET)
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#define STM32_OTG_DFIFO_HCH0 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH0_OFFSET)
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#define STM32_OTG_DFIFO_DEP1 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP1_OFFSET)
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#define STM32_OTG_DFIFO_HCH1 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH1_OFFSET)
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#define STM32_OTG_DFIFO_DEP2 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP2_OFFSET)
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#define STM32_OTG_DFIFO_HCH2 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH2_OFFSET)
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#define STM32_OTG_DFIFO_DEP3 (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP3_OFFSET)
|
||||
#define STM32_OTG_DFIFO_HCH3 (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH3_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ********************************************************************/
|
||||
/* Core global control and status registers */
|
||||
|
||||
@ -66,18 +66,18 @@
|
||||
# define GPIO_OTG_DP GPIO_OTGFS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGFS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGFS_SOF
|
||||
|
||||
# define STM32_OTG_FIFO_SIZE 1280
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_OTGHS)
|
||||
# define STM32_IRQ_OTG STM32_IRQ_OTGHS
|
||||
# define STM32_OTG_BASE STM32_USBOTGHS_BASE
|
||||
# define STM32_NENDPOINTS (8) /* ep0-7 x 2 for IN and OUT */
|
||||
# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */
|
||||
# define GPIO_OTG_DM GPIO_OTGHS_DM
|
||||
# define GPIO_OTG_DP GPIO_OTGHS_DP
|
||||
# define GPIO_OTG_ID GPIO_OTGHS_ID
|
||||
# define GPIO_OTG_SOF GPIO_OTGHS_SOF
|
||||
|
||||
# define STM32_OTG_FIFO_SIZE 4096
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@ -89,30 +89,82 @@
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_USBDEV_RXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_RXFIFO_SIZE 512
|
||||
# define CONFIG_USBDEV_RXFIFO_SIZE (STM32_OTG_FIFO_SIZE - STM32_OTG_FIFO_SIZE/4/2/STM32_NENDPOINTS*4*STM32_NENDPOINTS)
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 192
|
||||
#if STM32_NENDPOINTS > 0
|
||||
# ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 192
|
||||
#if STM32_NENDPOINTS > 1
|
||||
# ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 192
|
||||
#if STM32_NENDPOINTS > 2
|
||||
# ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 192
|
||||
#if STM32_NENDPOINTS > 3
|
||||
# ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#if (CONFIG_USBDEV_RXFIFO_SIZE + CONFIG_USBDEV_EP0_TXFIFO_SIZE + \
|
||||
CONFIG_USBDEV_EP2_TXFIFO_SIZE + CONFIG_USBDEV_EP3_TXFIFO_SIZE) > 1280
|
||||
# error "FIFO allocations exceed FIFO memory size"
|
||||
#if STM32_NENDPOINTS > 4
|
||||
# ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 5
|
||||
# ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 6
|
||||
# ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 7
|
||||
# ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 8
|
||||
# ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE
|
||||
# define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS)
|
||||
# endif
|
||||
#else
|
||||
# define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0
|
||||
#endif
|
||||
|
||||
|
||||
/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries;
|
||||
* FIFO sizes must be provided in units of 32-bit words.
|
||||
*/
|
||||
@ -123,29 +175,36 @@
|
||||
#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#if STM32_EP0_TXFIFO_WORDS < 16 || STM32_EP0_TXFIFO_WORDS > 256
|
||||
# error "CONFIG_USBDEV_EP0_TXFIFO_SIZE is out of range"
|
||||
#endif
|
||||
|
||||
#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#if STM32_EP1_TXFIFO_WORDS < 16
|
||||
# error "CONFIG_USBDEV_EP1_TXFIFO_SIZE is out of range"
|
||||
#endif
|
||||
|
||||
#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#if STM32_EP2_TXFIFO_WORDS < 16
|
||||
# error "CONFIG_USBDEV_EP2_TXFIFO_SIZE is out of range"
|
||||
#endif
|
||||
|
||||
#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#if STM32_EP3_TXFIFO_WORDS < 16
|
||||
# error "CONFIG_USBDEV_EP3_TXFIFO_SIZE is out of range"
|
||||
#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
#define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3)
|
||||
#define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2)
|
||||
|
||||
|
||||
#if (STM32_RXFIFO_BYTES + \
|
||||
STM32_EP0_TXFIFO_BYTES + STM32_EP1_TXFIFO_BYTES + STM32_EP2_TXFIFO_BYTES + STM32_EP3_TXFIFO_BYTES + \
|
||||
STM32_EP4_TXFIFO_BYTES + STM32_EP5_TXFIFO_BYTES + STM32_EP6_TXFIFO_BYTES + STM32_EP7_TXFIFO_BYTES + CONFIG_USBDEV_EP8_TXFIFO_SIZE \
|
||||
) > STM32_OTG_FIFO_SIZE
|
||||
# error "FIFO allocations exceed FIFO memory size"
|
||||
#endif
|
||||
|
||||
/* Debug ***********************************************************************/
|
||||
@ -962,7 +1021,7 @@ static void stm32_ep0in_activate(void)
|
||||
|
||||
/* Set the max packet size of the IN EP. */
|
||||
|
||||
regval = stm32_getreg(STM32_OTG_DIEPCTL0);
|
||||
regval = stm32_getreg(STM32_OTG_DIEPCTL(0));
|
||||
regval &= ~OTG_DIEPCTL0_MPSIZ_MASK;
|
||||
|
||||
#if CONFIG_USBDEV_EP0_MAXSIZE == 8
|
||||
@ -977,7 +1036,7 @@ static void stm32_ep0in_activate(void)
|
||||
# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE"
|
||||
#endif
|
||||
|
||||
stm32_putreg(regval, STM32_OTG_DIEPCTL0);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPCTL(0));
|
||||
|
||||
/* Clear global IN NAK */
|
||||
|
||||
@ -1003,13 +1062,13 @@ static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv)
|
||||
regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) |
|
||||
(OTG_DOEPTSIZ0_PKTCNT) |
|
||||
(3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DOEPTSIZ0);
|
||||
stm32_putreg(regval, STM32_OTG_DOEPTSIZ(0));
|
||||
|
||||
/* Then clear NAKing and enable the transfer */
|
||||
|
||||
regval = stm32_getreg(STM32_OTG_DOEPCTL0);
|
||||
regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
|
||||
regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA);
|
||||
stm32_putreg(regval, STM32_OTG_DOEPCTL0);
|
||||
stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -3227,9 +3286,9 @@ static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv)
|
||||
{
|
||||
/* Clear NAKSTS so that we can receive the data */
|
||||
|
||||
regval = stm32_getreg(STM32_OTG_DOEPCTL0);
|
||||
regval = stm32_getreg(STM32_OTG_DOEPCTL(0));
|
||||
regval |= OTG_DOEPCTL0_CNAK;
|
||||
stm32_putreg(regval, STM32_OTG_DOEPCTL0);
|
||||
stm32_putreg(regval, STM32_OTG_DOEPCTL(0));
|
||||
|
||||
/* Wait for the data phase. */
|
||||
|
||||
@ -5235,33 +5294,68 @@ static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv)
|
||||
|
||||
stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ);
|
||||
|
||||
/* EP0 TX */
|
||||
|
||||
#if STM32_NENDPOINTS > 0
|
||||
address = STM32_RXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) |
|
||||
(STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF0);
|
||||
#endif
|
||||
|
||||
/* EP1 TX */
|
||||
|
||||
#if STM32_NENDPOINTS > 1
|
||||
address += STM32_EP0_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF1);
|
||||
|
||||
/* EP2 TX */
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(1));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 2
|
||||
address += STM32_EP1_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF2);
|
||||
|
||||
/* EP3 TX */
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(2));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 3
|
||||
address += STM32_EP2_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF3);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(3));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 4
|
||||
address += STM32_EP3_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(4));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 5
|
||||
address += STM32_EP4_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(5));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 6
|
||||
address += STM32_EP5_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(6));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 7
|
||||
address += STM32_EP6_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(7));
|
||||
#endif
|
||||
|
||||
#if STM32_NENDPOINTS > 8
|
||||
address += STM32_EP7_TXFIFO_WORDS;
|
||||
regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) |
|
||||
(STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT);
|
||||
stm32_putreg(regval, STM32_OTG_DIEPTXF(8));
|
||||
#endif
|
||||
|
||||
/* Flush the FIFOs */
|
||||
|
||||
|
||||
@ -300,13 +300,13 @@ CONFIG_STM32F7_I2C1=y
|
||||
# CONFIG_STM32F7_I2C3 is not set
|
||||
# CONFIG_STM32F7_LPTIM1 is not set
|
||||
# CONFIG_STM32F7_LTDC is not set
|
||||
##CONFIG_STM32F7_OTGFS=y
|
||||
CONFIG_STM32F7_OTGFS=y
|
||||
# CONFIG_STM32F7_OTGHS is not set
|
||||
# CONFIG_STM32F7_QUADSPI is not set
|
||||
# CONFIG_STM32F7_RNG is not set
|
||||
# CONFIG_STM32F7_SAI1 is not set
|
||||
# CONFIG_STM32F7_SAI2 is not set
|
||||
CONFIG_STM32F7_SDMMC1=y
|
||||
##CONFIG_STM32F7_SDMMC1=y
|
||||
# CONFIG_STM32F7_SPDIFRX is not set
|
||||
CONFIG_STM32F7_SPI1=y
|
||||
# CONFIG_STM32F7_SPI2 is not set
|
||||
@ -434,7 +434,7 @@ CONFIG_LIB_BOARDCTL=y
|
||||
# CONFIG_BOARDCTL_PWMTEST is not set
|
||||
# CONFIG_BOARDCTL_GRAPHICS is not set
|
||||
# CONFIG_BOARDCTL_IOCTL is not set
|
||||
##CONFIG_BOARDCTL_USBDEVCTRL=y
|
||||
CONFIG_BOARDCTL_USBDEVCTRL=y
|
||||
|
||||
#
|
||||
# RTOS Features
|
||||
@ -690,7 +690,7 @@ CONFIG_USART6_2STOP=0
|
||||
# CONFIG_USART6_IFLOWCONTROL is not set
|
||||
# CONFIG_USART6_OFLOWCONTROL is not set
|
||||
# CONFIG_USART6_DMA is not set
|
||||
##CONFIG_USBDEV=y
|
||||
CONFIG_USBDEV=y
|
||||
# CONFIG_USBHOST is not set
|
||||
# CONFIG_DRIVERS_WIRELESS is not set
|
||||
|
||||
@ -700,9 +700,9 @@ CONFIG_USART6_2STOP=0
|
||||
#
|
||||
# CONFIG_USBDEV_ISOCHRONOUS is not set
|
||||
# CONFIG_USBDEV_DUALSPEED is not set
|
||||
##CONFIG_USBDEV_SELFPOWERED=y
|
||||
CONFIG_USBDEV_SELFPOWERED=y
|
||||
# CONFIG_USBDEV_BUSPOWERED is not set
|
||||
##CONFIG_USBDEV_MAXPOWER=100
|
||||
CONFIG_USBDEV_MAXPOWER=100
|
||||
# CONFIG_USBDEV_DMA is not set
|
||||
# CONFIG_ARCH_USBDEV_STALLQUEUE is not set
|
||||
# CONFIG_USBDEV_TRACE is not set
|
||||
@ -712,27 +712,26 @@ CONFIG_USART6_2STOP=0
|
||||
#
|
||||
# CONFIG_USBDEV_COMPOSITE is not set
|
||||
# CONFIG_PL2303 is not set
|
||||
##CONFIG_CDCACM=y
|
||||
##CONFIG_CDCACM_CONSOLE=y
|
||||
##CONFIG_CDCACM_EP0MAXPACKET=64
|
||||
##CONFIG_CDCACM_EPINTIN=1
|
||||
##CONFIG_CDCACM_EPINTIN_FSSIZE=64
|
||||
##CONFIG_CDCACM_EPINTIN_HSSIZE=64
|
||||
##CONFIG_CDCACM_EPBULKOUT=3
|
||||
##CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
|
||||
##CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
|
||||
##CONFIG_CDCACM_EPBULKIN=2
|
||||
##CONFIG_CDCACM_EPBULKIN_FSSIZE=64
|
||||
##CONFIG_CDCACM_EPBULKIN_HSSIZE=512
|
||||
##CONFIG_CDCACM_NRDREQS=4
|
||||
##CONFIG_CDCACM_NWRREQS=4
|
||||
##CONFIG_CDCACM_BULKIN_REQLEN=96
|
||||
##CONFIG_CDCACM_RXBUFSIZE=256
|
||||
##CONFIG_CDCACM_TXBUFSIZE=256
|
||||
##CONFIG_CDCACM_VENDORID=0x0525
|
||||
##CONFIG_CDCACM_PRODUCTID=0xa4a7
|
||||
##CONFIG_CDCACM_VENDORSTR="NuttX"
|
||||
##CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
|
||||
CONFIG_CDCACM=y
|
||||
CONFIG_CDCACM_EP0MAXPACKET=64
|
||||
CONFIG_CDCACM_EPINTIN=1
|
||||
CONFIG_CDCACM_EPINTIN_FSSIZE=64
|
||||
CONFIG_CDCACM_EPINTIN_HSSIZE=64
|
||||
CONFIG_CDCACM_EPBULKOUT=2
|
||||
CONFIG_CDCACM_EPBULKOUT_FSSIZE=64
|
||||
CONFIG_CDCACM_EPBULKOUT_HSSIZE=512
|
||||
CONFIG_CDCACM_EPBULKIN=2
|
||||
CONFIG_CDCACM_EPBULKIN_FSSIZE=64
|
||||
CONFIG_CDCACM_EPBULKIN_HSSIZE=512
|
||||
CONFIG_CDCACM_NRDREQS=4
|
||||
CONFIG_CDCACM_NWRREQS=4
|
||||
CONFIG_CDCACM_BULKIN_REQLEN=96
|
||||
CONFIG_CDCACM_RXBUFSIZE=256
|
||||
CONFIG_CDCACM_TXBUFSIZE=256
|
||||
CONFIG_CDCACM_VENDORID=0x03EB
|
||||
CONFIG_CDCACM_PRODUCTID=0x2044
|
||||
CONFIG_CDCACM_VENDORSTR="NuttX"
|
||||
CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial"
|
||||
# CONFIG_USBMSC is not set
|
||||
# CONFIG_USBHOST is not set
|
||||
# CONFIG_DRIVERS_WIRELESS is not set
|
||||
@ -1128,3 +1127,6 @@ CONFIG_READLINE_ECHO=y
|
||||
# CONFIG_SYSTEM_UBLOXMODEM is not set
|
||||
# CONFIG_SYSTEM_VI is not set
|
||||
# CONFIG_SYSTEM_ZMODEM is not set
|
||||
|
||||
CONFIG_SYSTEM_CDCACM=y
|
||||
CONFIG_SYSTEM_CDCACM_DEVMINOR=0
|
||||
|
||||
Loading…
Reference in New Issue
Block a user