Various STM32 SDIO and DMA fixes (SDIO DMA still does not work)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4406 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
5f9533b655
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2726206ac1
@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_sdio.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -355,6 +355,27 @@
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#define DMA_SNDTR_NDT_SHIFT (0) /* Bits 15-0: Number of data to Transfer */
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#define DMA_SNDTR_NDT_MASK (0xffff << DMA_SNDTR_NDT_SHIFT)
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/* DMA stream n FIFO control register */
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#define DMA_SFCR_FTH_SHIFT (0) /* Bits 0-1: FIFO threshold selection */
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#define DMA_SFCR_FTH_MASK (3 << DMA_SFCR_FTH_SHIFT)
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# define DMA_SFCR_FTH_QUARTER (0 << DMA_SFCR_FTH_SHIFT) /* 1/4 full FIFO */
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# define DMA_SFCR_FTH_HALF (1 << DMA_SFCR_FTH_SHIFT) /* 1/2 full FIFO */
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# define DMA_SFCR_FTH_3QUARTER (2 << DMA_SFCR_FTH_SHIFT) /* 3/4 full FIFO */
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# define DMA_SFCR_FTH_FULL (3 << DMA_SFCR_FTH_SHIFT) /* full FIFO */
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#define DMA_SFCR_DMDIS (1 << 2) /* Bit 2: Direct mode disable */
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#define DMA_SFCR_FS_SHIFT (3) /* Bits 3-5: FIFO status */
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#define DMA_SFCR_FS_MASK (7 << DMA_SFCR_FS_SHIFT)
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# define DMA_SFCR_FS_QUARTER (0 << DMA_SFCR_FS_SHIFT) /* 0 < fifo_level < 1/4 */
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# define DMA_SFCR_FS_HALF (1 << DMA_SFCR_FS_SHIFT) /* 1/4 = fifo_level < 1/2 */
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# define DMA_SFCR_FS_3QUARTER (2 << DMA_SFCR_FS_SHIFT) /* 1/2 = fifo_level < 3/4 */
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# define DMA_SFCR_FS_ALMOSTFULL (3 << DMA_SFCR_FS_SHIFT) /* 3/4 = fifo_level < full */
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# define DMA_SFCR_FS_EMPTY (4 << DMA_SFCR_FS_SHIFT) /* FIFO is empty */
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# define DMA_SFCR_FS_FULL (5 << DMA_SFCR_FS_SHIFT) /* FIFO is full */
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/* Bit 6: Reserved */
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#define DMA_SFCR_FEIE (1 << 7) /* Bit 7: FIFO error interrupt enable */
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/* Bits 8-31: Reserved */
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/* DMA Stream mapping. Each DMA stream has a mapping to several possible
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* sources/sinks of data. The requests from peripherals assigned to a stream
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* are simply OR'ed together before entering the DMA block. This means that only
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@ -369,7 +390,7 @@
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* #define DMAMAP_SPI3_RX DMAMAP_SPI3_RX_1
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*/
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#define STM32_DMA_MAP(d,c,s) ((d) << 6 | (s) << 3 | (c))
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#define STM32_DMA_MAP(d,s,c) ((d) << 6 | (s) << 3 | (c))
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#define STM32_DMA_CONTROLLER(m) (((m) >> 6) & 1)
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#define STM32_DMA_STREAM(m) (((m) >> 3) & 7)
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#define STM32_DMA_CHAN(c) ((c) & 7)
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -54,9 +54,18 @@
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************************************************************************************/
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/* Additional Configuration *********************************************************/
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/* Custom debug settings used in the STM32 port. These are managed by STM32-specific
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* logic and not the common logic in include/debug.h. NOTE: Some of these also
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* depend on CONFIG_DEBUG_VERBOSE
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*/
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#if !defined(CONFIG_DEBUG) || !defined(CONFIG_DEBUG_VERBOSE)
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#ifndef CONFIG_DEBUG
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# undef CONFIG_DEBUG_DMA
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# undef CONFIG_DEBUG_RTC
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# undef CONFIG_DEBUG_I2C
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# undef CONFIG_DEBUG_CAN
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# undef CONFIG_DEBUG_PWM
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# undef CONFIG_DEBUG_QENCODER
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#endif
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/* NVIC priority levels *************************************************************/
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@ -71,6 +71,32 @@
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Required system configuration options:
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*
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* CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem
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* initialization. Required if CONFIG_SDIO_DMA is enabled.
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* CONFIG_STM32_DMA2 - Enable STM32 DMA2 support. Required if
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* CONFIG_SDIO_DMA is enabled
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* CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support.
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*
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* Driver-specific configuration options:
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*
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* CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking
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* APIs to manage concurrent accesses on the SDIO bus. This is not
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* needed for the simple case of a single SD card, for example.
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* CONFIG_SDIO_DMA - Enable SDIO. This is a marginally optional. For
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* most usages, SDIO will cause data overruns if used without DMA.
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* NOTE the above system DMA configuration options.
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* CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver
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* operate with only a single data line (the default is to use all
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* 4 SD data lines).
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* CONFIG_SDIO_PRI - SDIO interrupt priority. This setting is not very
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* important since interrupt nesting is not currently supported.
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* CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if
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* CONFIG_SDIO_DMA is enabled.
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* CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output
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* This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_VERBOSE
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*/
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#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_STM32_DMA2)
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# warning "CONFIG_SDIO_DMA support requires CONFIG_STM32_DMA2"
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@ -88,17 +114,32 @@
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# define CONFIG_SDIO_PRI NVIC_SYSH_PRIORITY_DEFAULT
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#endif
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#ifndef CONFIG_SDIO_DMAPRIO
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#ifdef CONFIG_SDIO_DMA
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# ifndef CONFIG_SDIO_DMAPRIO
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# if defined(CONFIG_STM32_STM32F10XX)
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# define CONFIG_SDIO_DMAPRIO DMA_CCR_PRIMED
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# elif defined(CONFIG_STM32_STM32F40XX)
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# define CONFIG_SDIO_DMAPRIO DMA_SCR_PRIMED
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# else
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# error "Unknown STM32 DMA"
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# endif
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# endif
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# if defined(CONFIG_STM32_STM32F10XX)
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# define CONFIG_SDIO_DMAPRIO DMA_CCR_PRIMED
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# if (CONFIG_SDIO_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
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# error "Illegal value for CONFIG_SDIO_DMAPRIO"
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# endif
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# elif defined(CONFIG_STM32_STM32F40XX)
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# define CONFIG_SDIO_DMAPRIO DMA_SCR_PRIMED
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# if (CONFIG_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0
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# error "Illegal value for CONFIG_SDIO_DMAPRIO"
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# endif
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# else
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# error "Unknown STM32 DMA"
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# endif
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#else
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# undef CONFIG_SDIO_DMAPRIO
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#endif
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#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_VERBOSE)
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#if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG)
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# undef CONFIG_SDIO_XFRDEBUG
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#endif
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@ -147,15 +188,17 @@
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# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
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DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
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/* STM32 F4 stream configuration register (SCR) settings */
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/* STM32 F4 stream configuration register (SCR) settings. */
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define SDIO_RXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_SCR_MSIZE_32BITS|\
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DMA_SCR_PSIZE_32BITS|DMA_SCR_MINC|DMA_SCR_DIR_P2M|\
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DMA_SCR_PBURST_SINGLE|DMA_SCR_PBURST_INCR8)
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# define SDIO_TXDMA32_CONFIG (CONFIG_SDIO_DMAPRIO|DMA_SCR_MSIZE_32BITS|\
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DMA_SCR_PSIZE_32BITS|DMA_SCR_MINC|DMA_SCR_DIR_M2P|\
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DMA_SCR_PBURST_SINGLE|DMA_SCR_PBURST_INCR8)
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# define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_P2M|DMA_SCR_MINC|\
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DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
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CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
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DMA_SCR_MBURST_INCR4)
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# define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL|DMA_SCR_DIR_M2P|DMA_SCR_MINC|\
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DMA_SCR_PSIZE_32BITS|DMA_SCR_MSIZE_32BITS|\
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CONFIG_SDIO_DMAPRIO|DMA_SCR_PBURST_INCR4|\
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DMA_SCR_MBURST_INCR4)
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#else
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# error "Unknown STM32 DMA"
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#endif
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@ -765,7 +808,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv,
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****************************************************************************/
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void stm32_dumpsamples(struct stm32_dev_s *priv)
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static void stm32_dumpsamples(struct stm32_dev_s *priv)
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{
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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@ -2282,6 +2325,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
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errout:
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irqrestore(flags);
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stm32_dumpsamples(priv);
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return wkupevent;
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}
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@ -2438,7 +2482,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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stm32_dmasetup(priv->dma, STM32_SDIO_FIFO, (uint32_t)buffer,
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(buflen + 3) >> 2, SDIO_RXDMA32_CONFIG);
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/* Start the DMA */
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/* Start the DMA */
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stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE);
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stm32_dmastart(priv->dma, stm32_dmacallback, priv, false);
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@ -2660,6 +2704,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
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#ifdef CONFIG_SDIO_DMA
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priv->dma = stm32_dmachannel(SDIO_DMACHAN);
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DEBUGASSERT(priv->dma);
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#endif
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/* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of
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@ -270,6 +270,59 @@ static inline void stm32_dmagive(FAR struct stm32_dma_s *dmast)
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(void)sem_post(&dmast->sem);
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}
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/************************************************************************************
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* Name: stm32_dmastream
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*
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* Description:
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* Get the g_dma table entry associated with a DMA controller and a stream number
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*
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************************************************************************************/
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static inline FAR struct stm32_dma_s *stm32_dmastream(unsigned int stream,
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unsigned int controller)
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{
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int index;
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DEBUGASSERT(stream < DMA_NSTREAMS && controller < STM32_NDMA);
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/* Convert the controller + stream based on the fact that there are 8 streams
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* per controller.
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*/
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#if STM32_NDMA > 1
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index = controller << 3 | stream;
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#else
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index = stream;
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#endif
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/* Then return the stream structure associated with the stream index */
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return &g_dma[index];
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}
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/************************************************************************************
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* Name: stm32_dmamap
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*
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* Description:
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* Get the g_dma table entry associated with a bit-encoded DMA selection
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*
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************************************************************************************/
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static inline FAR struct stm32_dma_s *stm32_dmamap(unsigned long dmamap)
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{
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/* Extract the DMA controller number from the bit encoded value */
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unsigned int controller = STM32_DMA_CONTROLLER(dmamap);
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/* Extact the stream number from the bit encoded value */
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unsigned int stream = STM32_DMA_STREAM(dmamap);
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/* Return the table entry associated with the controller + stream */
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return stm32_dmastream(stream, controller);
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}
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/************************************************************************************
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* Name: stm32_dmastreamdisable
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*
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@ -322,28 +375,31 @@ static int stm32_dmainterrupt(int irq, void *context)
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struct stm32_dma_s *dmast;
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uint32_t isr;
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uint32_t regoffset = 0;
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int stndx = 0;
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unsigned int stream = 0;
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unsigned int controller = 0;
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/* Get the stream structure from the interrupt number */
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if (irq >= STM32_IRQ_DMA1S0 && irq <= STM32_IRQ_DMA1S7)
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{
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stndx = irq - STM32_IRQ_DMA1S0;
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regoffset = STM32_DMA_LISR_OFFSET;
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stream = irq - STM32_IRQ_DMA1S0;
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controller = DMA1;
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regoffset = STM32_DMA_LISR_OFFSET;
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}
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else
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#if STM32_NDMA > 1
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if (irq >= STM32_IRQ_DMA2S0 && irq <= STM32_IRQ_DMA2S7)
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{
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stndx = irq - STM32_IRQ_DMA2S0 + DMA1_NSTREAMS;
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regoffset = STM32_DMA_HISR_OFFSET;
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stream = irq - STM32_IRQ_DMA2S0 + DMA1_NSTREAMS;
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controller = DMA2;
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regoffset = STM32_DMA_HISR_OFFSET;
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}
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else
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#endif
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{
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PANIC(OSERR_INTERNAL);
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}
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dmast = &g_dma[stndx];
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dmast = stm32_dmastream(stream, controller);
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/* Get the interrupt status for this stream */
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@ -380,13 +436,13 @@ static int stm32_dmainterrupt(int irq, void *context)
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void weak_function up_dmainitialize(void)
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{
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struct stm32_dma_s *dmast;
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int stndx;
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int stream;
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/* Initialize each DMA stream */
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for (stndx = 0; stndx < DMA_NSTREAMS; stndx++)
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for (stream = 0; stream < DMA_NSTREAMS; stream++)
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{
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dmast = &g_dma[stndx];
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dmast = &g_dma[stream];
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sem_init(&dmast->sem, 0, 1);
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/* Attach DMA interrupt vectors */
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@ -412,7 +468,7 @@ void weak_function up_dmainitialize(void)
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*
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* Description:
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* Allocate a DMA channel. This function gives the caller mutually
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* exclusive access to the DMA channel specified by the 'stndx' argument.
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* exclusive access to the DMA channel specified by the 'dmamap' argument.
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* DMA channels are shared on the STM32: Devices sharing the same DMA
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* channel cannot do DMA concurrently! See the DMACHAN_* definitions in
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* stm32_dma.h.
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@ -428,13 +484,13 @@ void weak_function up_dmainitialize(void)
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* version. Feel free to do that if that is what you need.
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*
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* Input parameter:
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* chan - Identifies the stream/channel resource. For the STM32 F4, this
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* dmamap - Identifies the stream/channel resource. For the STM32 F4, this
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* is a bit-encoded value as provided by the the DMAMAP_* definitions
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* in chip/stm32f40xxx_dma.h
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*
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* Returned Value:
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* Provided that 'stndx' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'stndx' is invalid, the function will
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* Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL,
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* void* DMA channel handle. (If 'dmamap' is invalid, the function will
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* assert if debug is enabled or do something ignorant otherwise).
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*
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* Assumptions:
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@ -444,19 +500,14 @@ void weak_function up_dmainitialize(void)
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*
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****************************************************************************/
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DMA_HANDLE stm32_dmachannel(unsigned int chan)
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DMA_HANDLE stm32_dmachannel(unsigned int dmamap)
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{
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struct stm32_dma_s *dmast;
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int stndx;
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FAR struct stm32_dma_s *dmast;
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/* Get the stream index from the bit-encoded channel value */
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stndx = STM32_DMA_STREAM(chan);
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DEBUGASSERT(stndx < DMA_NSTREAMS);
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/* Then get the stream structure associated with the stream index */
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dmast = &g_dma[stndx];
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dmast = stm32_dmamap(dmamap);
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DEBUGASSERT(dmast != NULL);
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/* Get exclusive access to the DMA channel -- OR wait until the channel
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* is available if it is currently being used by another driver
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@ -507,45 +558,110 @@ void stm32_dmafree(DMA_HANDLE handle)
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*
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****************************************************************************/
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void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr, size_t ntransfers, uint32_t scr)
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void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
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size_t ntransfers, uint32_t scr)
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{
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struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
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uint32_t regoffset;
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uint32_t regval;
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/* Set the peripheral register address in the DMA_SPARx register. The data
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* will be moved from/to this address to/from the memory after the
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* peripheral event.
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dmadbg("paddr: %08x maddr: %08x ntransfers: %d scr: %08x\n",
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paddr, maddr, ntransfers, scr);
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/* "If the stream is enabled, disable it by resetting the EN bit in the
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* DMA_SxCR register, then read this bit in order to confirm that there is no
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* ongoing stream operation. Writing this bit to 0 is not immediately
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* effective since it is actually written to 0 once all the current transfers
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* have finished. When the EN bit is read as 0, this means that the stream is
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* ready to be configured. It is therefore necessary to wait for the EN bit
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* to be cleared before starting any stream configuration. ..."
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*/
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while ((dmast_getreg(dmast, STM32_DMA_SCR_OFFSET) & DMA_SCR_EN) != 0);
|
||||
|
||||
/* "... All the stream dedicated bits set in the status register (DMA_LISR
|
||||
* and DMA_HISR) from the previous data block DMA transfer should be cleared
|
||||
* before the stream can be re-enabled."
|
||||
*
|
||||
* Clear pending stream interrupts by setting bits in the upper or lower IFCR
|
||||
* register
|
||||
*/
|
||||
|
||||
if (dmast->stream < 4)
|
||||
{
|
||||
regoffset = STM32_DMA_LIFCR_OFFSET;
|
||||
}
|
||||
else
|
||||
{
|
||||
regoffset = STM32_DMA_HIFCR_OFFSET;
|
||||
}
|
||||
|
||||
dmabase_putreg(dmast, regoffset, (DMA_STREAM_MASK << dmast->shift));
|
||||
|
||||
/* "Set the peripheral register address in the DMA_SPARx register. The data
|
||||
* will be moved from/to this address to/from the memory after the
|
||||
* peripheral event.
|
||||
*/
|
||||
|
||||
dmast_putreg(dmast, STM32_DMA_SPAR_OFFSET, paddr);
|
||||
|
||||
/* Set the memory address in the DMA_SM0ARx register. The data will be
|
||||
* written to or read from this memory after the peripheral event.
|
||||
/* "Set the memory address in the DMA_SM0ARx ... register. The data will be
|
||||
* written to or read from this memory after the peripheral event."
|
||||
*
|
||||
* Note that only single-buffer mode is currently supported so SM1ARx
|
||||
* is not used.
|
||||
* is not used."
|
||||
*/
|
||||
|
||||
dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr);
|
||||
|
||||
/* Configure the total number of data items to be transferred in the DMA_SNDTRx
|
||||
* register. After each peripheral event, this value will be decremented.
|
||||
/* "Configure the total number of data items to be transferred in the
|
||||
* DMA_SNDTRx register. After each peripheral event, this value will be
|
||||
* decremented."
|
||||
*/
|
||||
|
||||
dmast_putreg(dmast, STM32_DMA_SNDTR_OFFSET, ntransfers);
|
||||
|
||||
/* Configure the stream priority using the PL[1:0] bits in the DMA_SCRx
|
||||
* register. Configure data transfer direction, circular mode, peripheral & memory
|
||||
* incremented mode, peripheral & memory data size, and interrupt after
|
||||
* half and/or full transfer in the DMA_CCRx register.
|
||||
/* "Select the DMA channel (request) using CHSEL[2:0] in the DMA_SxCR register."
|
||||
*
|
||||
* "Configure the stream priority using the PL[1:0] bits in the DMA_SCRx"
|
||||
* register."
|
||||
*/
|
||||
|
||||
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
||||
regval &= ~(DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|DMA_SCR_PSIZE_MASK|
|
||||
DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|DMA_SCR_PL_MASK|DMA_SCR_PBURST_MASK|
|
||||
DMA_SCR_MBURST_MASK);
|
||||
scr &= (DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|DMA_SCR_PSIZE_MASK|
|
||||
DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|DMA_SCR_PL_MASK|DMA_SCR_PBURST_MASK|
|
||||
DMA_SCR_MBURST_MASK);
|
||||
regval &= ~(DMA_SCR_PL_MASK|DMA_SCR_CHSEL_MASK);
|
||||
regval |= scr & DMA_SCR_PL_MASK;
|
||||
regval |= (uint32_t)dmast->stream << DMA_SCR_CHSEL_SHIFT;
|
||||
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
|
||||
|
||||
/* "Configure the FIFO usage (enable or disable, threshold in transmission and
|
||||
* reception)"
|
||||
*
|
||||
* "Caution is required when choosing the FIFO threshold (bits FTH[1:0] of the
|
||||
* DMA_SxFCR register) and the size of the memory burst (MBURST[1:0] of the
|
||||
* DMA_SxCR register): The content pointed by the FIFO threshold must exactly
|
||||
* match to an integer number of memory burst transfers. If this is not in the
|
||||
* case, a FIFO error (flag FEIFx of the DMA_HISR or DMA_LISR register) will be
|
||||
* generated when the stream is enabled, then the stream will be automatically
|
||||
* disabled."
|
||||
*/
|
||||
|
||||
regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
|
||||
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK);
|
||||
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS | DMA_SFCR_FEIE);
|
||||
dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval);
|
||||
|
||||
/* "Configure data transfer direction, circular mode, peripheral & memory
|
||||
* incremented mode, peripheral & memory data size, and interrupt after
|
||||
* half and/or full transfer in the DMA_CCRx register."
|
||||
*/
|
||||
|
||||
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
||||
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
|
||||
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
|
||||
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
|
||||
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
|
||||
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
|
||||
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
|
||||
regval |= scr;
|
||||
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
|
||||
}
|
||||
@ -631,8 +747,8 @@ void stm32_dmasample(DMA_HANDLE handle, struct stm32_dmaregs_s *regs)
|
||||
|
||||
flags = irqsave();
|
||||
regs->lisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET);
|
||||
regs->hisr = dmabase_getreg(dmast, STM32_DMA_LISR_OFFSET);
|
||||
regs->scr = dmast_getreg(dmast, STM32_DMA_HISR_OFFSET);
|
||||
regs->hisr = dmabase_getreg(dmast, STM32_DMA_HISR_OFFSET);
|
||||
regs->scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
||||
regs->sndtr = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
|
||||
regs->spar = dmast_getreg(dmast, STM32_DMA_SPAR_OFFSET);
|
||||
regs->sm0ar = dmast_getreg(dmast, STM32_DMA_SM0AR_OFFSET);
|
||||
@ -668,7 +784,7 @@ void stm32_dmadump(DMA_HANDLE handle, const struct stm32_dmaregs_s *regs,
|
||||
dmadbg(" SPAR[%08x]: %08x\n", dmast->base + STM32_DMA_SPAR_OFFSET, regs->spar);
|
||||
dmadbg(" SM0AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM0AR_OFFSET, regs->sm0ar);
|
||||
dmadbg(" SM1AR[%08x]: %08x\n", dmast->base + STM32_DMA_SM1AR_OFFSET, regs->sm1ar);
|
||||
dmadbg(" SFCRF[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
|
||||
dmadbg(" SFCR[%08x]: %08x\n", dmast->base + STM32_DMA_SFCR_OFFSET, regs->sfcr);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user