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Definitions for ARMv7-M AIRCR register, Fixes for ADS7843 and SSD1289 driver, Missing build logic for examples/watchdog

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5198 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2012-09-27 15:29:53 +00:00
parent 3da15ce551
commit 272ee75f8e
1 changed files with 8 additions and 0 deletions
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8
arch/arm/src/armv7-m/nvic.h
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@ -500,6 +500,14 @@
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
/* Application Interrupt and Reset Control Register (AIRCR) */
/* Bit 0: Reserved */
#define NVIC_AIRC_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */
#define NVIC_AIRC_SYSRESETREQ (1 << 2) /* Bit 2: System reset */
/* Bits 3-14: Reserved */
#define NVIC_AIRC_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */
/* Bits 16-31: Reserved */
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */