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esp32s3: Add support to RTC

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This commit is contained in:
Alan Carvalho de Assis 2023-04-26 10:13:23 -03:00 committed by Xiang Xiao
parent 9f8d418cd1
commit 276d1c8f48
15 changed files with 4955 additions and 14 deletions
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4
arch/xtensa/src/esp32s3/Kconfig
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@ -313,6 +313,10 @@ config ESP32S3_DMA
default n
select ARCH_DMA
config ESP32S3_RTC
bool "Real Time Clock (RTC)"
default y
config ESP32S3_UART0
bool "UART 0"
default n

7
arch/xtensa/src/esp32s3/Make.defs
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@ -135,3 +135,10 @@ endif
ifeq ($(CONFIG_ESP32S3_WIRELESS),y)
include chip/Wireless.mk
endif
ifeq ($(CONFIG_ESP32S3_RTC),y)
CHIP_CSRCS += esp32s3_rtc.c
ifeq ($(CONFIG_RTC_DRIVER),y)
CHIP_CSRCS += esp32s3_rtc_lowerhalf.c
endif
endif

2773
arch/xtensa/src/esp32s3/esp32s3_rtc.c Normal file
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File diff suppressed because it is too large Load Diff

769
arch/xtensa/src/esp32s3/esp32s3_rtc.h Normal file
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@ -0,0 +1,769 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/timers/rtc.h>
#include <sys/types.h>
#include <time.h>
#include "hardware/esp32s3_soc.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of cycles to wait from the 32k XTAL oscillator to
* consider it running. Larger values increase startup delay.
* Smaller values may cause false positive detection
* (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES 1024
/* Indicates that 32k oscillator gets input from external oscillator
* instead of a crystal.
*/
#define EXT_OSC_FLAG BIT(3)
/****************************************************************************
* Public Types
****************************************************************************/
/* CPU clock source */
enum esp32s3_rtc_cpu_freq_src_e
{
RTC_CPU_FREQ_SRC_XTAL, /* XTAL */
RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */
RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */
};
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32s3_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_32M = 32, /* 32 MHz XTAL */
RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */
};
/* RTC SLOW_CLK frequency values */
enum esp32s3_rtc_slow_freq_e
{
RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */
RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */
RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */
};
/* RTC FAST_CLK frequency values */
enum esp32s3_rtc_fast_freq_e
{
RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */
RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */
};
/* This is almost the same as esp32s3_rtc_slow_freq_e, except that we define
* an extra enum member for the external 32k oscillator. For convenience,
* lower 2 bits should correspond to esp32s3_rtc_slow_freq_e values.
*/
enum esp32s3_slow_clk_sel_e
{
/* Internal 150 kHz RC oscillator */
SLOW_CLK_150K = RTC_SLOW_FREQ_RTC,
/* External 32 kHz XTAL */
SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL,
/* Internal 8 MHz RC oscillator, divided by 256 */
SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256,
/* External 32k oscillator connected to 32K_XP pin */
SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG
};
/* Clock source to be calibrated using rtc_clk_cal function */
enum esp32s3_rtc_cal_sel_e
{
RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */
RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */
RTC_CAL_32K_XTAL = 2, /* External 32 kHz XTAL */
RTC_CAL_INTERNAL_OSC = 3 /* Internal 150 kHz oscillator */
};
/* CPU clock configuration structure */
struct esp32s3_cpu_freq_config_s
{
/* The clock from which CPU clock is derived */
enum esp32s3_rtc_cpu_freq_src_e source;
uint32_t source_freq_mhz; /* Source clock frequency */
uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */
uint32_t freq_mhz; /* CPU clock frequency */
};
#ifdef CONFIG_RTC_ALARM
/* The form of an alarm callback */
typedef void (*alm_callback_t)(void *arg, unsigned int alarmid);
enum alm_id_e
{
RTC_ALARM0 = 0, /* RTC ALARM 0 */
RTC_ALARM1 = 1, /* RTC ALARM 1 */
RTC_ALARM_LAST,
};
/* Structure used to pass parameters to set an alarm */
struct alm_setalarm_s
{
int as_id; /* enum alm_id_e */
struct timespec as_time; /* Alarm expiration time */
alm_callback_t as_cb; /* Callback (if non-NULL) */
void *as_arg; /* Argument for callback */
};
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtc_clk_slow_freq_get_hz
*
* Description:
* Get the approximate frequency of RTC_SLOW_CLK, in Hz
*
* Input Parameters:
* None
*
* Returned Value:
* slow_clk_freq - RTC_SLOW_CLK frequency, in Hz
*
****************************************************************************/
uint32_t esp32s3_rtc_clk_slow_freq_get_hz(void);
/****************************************************************************
* Name: esp32s3_rtc_clk_fast_freq_get_hz
*
* Description:
* Get fast_clk_rtc source in Hz.
*
* Input Parameters:
* None
*
* Returned Value:
* The clock source in Hz.
*
****************************************************************************/
uint32_t esp32s3_rtc_clk_fast_freq_get_hz(void);
/****************************************************************************
* Name: esp32s3_rtc_get_slow_clk_rtc
*
* Description:
* Get slow_clk_rtc source.
*
* Input Parameters:
* None
*
* Returned Value:
* The clock source:
* - SLOW_CK
* - CK_XTAL_32K
* - CK8M_D256_OUT
*
****************************************************************************/
enum esp32s3_rtc_slow_freq_e esp32s3_rtc_get_slow_clk(void);
/****************************************************************************
* Name: esp32s3_rtc_clk_cal
*
* Description:
* Measure RTC slow clock's period, based on main XTAL frequency
*
* Input Parameters:
* cal_clk - clock to be measured
* slowclk_cycles - number of slow clock cycles to average
*
* Returned Value:
* Average slow clock period in microseconds, Q13.19 fixed point format
* or 0 if calibration has timed out
*
****************************************************************************/
uint32_t esp32s3_rtc_clk_cal(enum esp32s3_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
/****************************************************************************
* Name: esp32s3_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s3_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s3_rtc_xtal_freq_e esp32s3_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32s3_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s3_rtc_update_to_xtal(int freq, int div);
/****************************************************************************
* Name: esp32s3_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_bbpll_enable(void);
/****************************************************************************
* Name: esp32s3_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
static void IRAM_ATTR esp32s3_rtc_bbpll_configure(
enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq);
/****************************************************************************
* Name: esp32s3_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_clk_set(void);
/****************************************************************************
* Name: esp32s3_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_init(void);
/****************************************************************************
* Name: esp32s3_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32s3_rtc_time_get(void);
/****************************************************************************
* Name: esp32s3_rtc_time_us_to_slowclk
*
* Description:
* Convert time interval from microseconds to RTC_SLOW_CLK cycles.
*
* Input Parameters:
* time_in_us - Time interval in microseconds
* slow_clk_period - Period of slow clock in microseconds
*
* Returned Value:
* number of slow clock cycles
*
****************************************************************************/
uint64_t esp32s3_rtc_time_us_to_slowclk(uint64_t time_in_us,
uint32_t period);
/****************************************************************************
* Name: esp32s3_rtc_time_slowclk_to_us
*
* Description:
* Convert time interval from RTC_SLOW_CLK to microseconds
*
* Input Parameters:
* rtc_cycles - Time interval in RTC_SLOW_CLK cycles
* period - Period of slow clock in microseconds
*
* Returned Value:
* Time interval in microseconds
*
****************************************************************************/
uint64_t esp32s3_rtc_time_slowclk_to_us(uint64_t rtc_cycles,
uint32_t period);
/****************************************************************************
* Name: esp32s3_clk_slowclk_cal_get
*
* Description:
* Get the calibration value of RTC slow clock.
*
* Input Parameters:
* None
*
* Returned Value:
* the calibration value obtained using rtc_clk_cal
*
****************************************************************************/
uint32_t esp32s3_clk_slowclk_cal_get(void);
/****************************************************************************
* Name: esp32s3_rtc_bbpll_disable
*
* Description:
* disable BBPLL.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_bbpll_disable(void);
/****************************************************************************
* Name: esp32s3_rtc_sleep_set_wakeup_time
*
* Description:
* Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source.
*
* Input Parameters:
* t - value of RTC counter at which wakeup from sleep will happen.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_sleep_set_wakeup_time(uint64_t t);
/****************************************************************************
* Name: esp32s3_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s3_rtc_wait_for_slow_cycle(void);
/****************************************************************************
* Name: esp32s3_rtc_cpu_freq_set_xtal
*
* Description:
* Switch CPU clock source to XTAL
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_cpu_freq_set_xtal(void);
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_rtc_clk_get_cpu_freq(void);
/****************************************************************************
* Name: esp32s3_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32s3_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
int esp32s3_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
/****************************************************************************
* Name: esp32s3_rtc_get_time_us
*
* Description:
* Get current value of RTC counter in microseconds
*
* Input Parameters:
* None
*
* Returned Value:
* Current value of RTC counter in microseconds
*
****************************************************************************/
uint64_t esp32s3_rtc_get_time_us(void);
/****************************************************************************
* Name: esp32s3_rtc_set_boot_time
*
* Description:
* Set time to RTC register to replace the original boot time.
*
* Input Parameters:
* time_us - set time in microseconds.
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_set_boot_time(uint64_t time_us);
/****************************************************************************
* Name: esp32s3_rtc_get_boot_time
*
* Description:
* Get time of RTC register to indicate the original boot time.
*
* Input Parameters:
* None
*
* Returned Value:
* time_us - get time in microseconds.
*
****************************************************************************/
uint64_t esp32s3_rtc_get_boot_time(void);
/****************************************************************************
* Name: esp32s3_rtc_clk_cpu_freq_set_config
*
* Description:
* Set CPU frequency configuration.
*
* Input Parameters:
* config - CPU frequency configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s3_rtc_clk_cpu_freq_set_config(
const struct esp32s3_cpu_freq_config_s *config);
/****************************************************************************
* Name: esp32s3_rtc_clk_cpu_freq_get_config
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU clock configuration structure
*
****************************************************************************/
void esp32s3_rtc_clk_cpu_freq_get_config(
struct esp32s3_cpu_freq_config_s *out_config);
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Name: up_rtc_time
*
* Description:
* Get the current time in seconds. This is similar to the standard time()
* function. This interface is only required if the low-resolution
* RTC/counter hardware implementation selected. It is only used by the
* RTOS during initialization to set up the system time when CONFIG_RTC is
* set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set.
*
* Input Parameters:
* None
*
* Returned Value:
* The current time in seconds
*
****************************************************************************/
#ifndef CONFIG_RTC_HIRES
time_t up_rtc_time(void);
#endif
/****************************************************************************
* Name: up_rtc_settime
*
* Description:
* Set the RTC to the provided time. All RTC implementations must be
* able to set their time based on a standard timespec.
*
* Input Parameters:
* tp - the time to use
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_settime(const struct timespec *ts);
/****************************************************************************
* Name: up_rtc_initialize
*
* Description:
* Initialize the hardware RTC per the selected configuration.
* This function is called once during the OS initialization sequence
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_initialize(void);
/****************************************************************************
* Name: up_rtc_gettime
*
* Description:
* Get the current time from the high resolution RTC clock/counter. This
* interface is only supported by the high-resolution RTC/counter hardware
* implementation. It is used to replace the system timer.
*
* Input Parameters:
* tp - The location to return the high resolution time value.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
#ifdef CONFIG_RTC_HIRES
int up_rtc_gettime(struct timespec *tp);
#endif
#ifdef CONFIG_RTC_ALARM
/****************************************************************************
* Name: up_rtc_setalarm
*
* Description:
* Set up an alarm.
*
* Input Parameters:
* alminfo - Information about the alarm configuration.
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_setalarm(struct alm_setalarm_s *alminfo);
/****************************************************************************
* Name: up_rtc_cancelalarm
*
* Description:
* Cancel an alaram.
*
* Input Parameters:
* alarmid - Identifies the alarm to be cancelled
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_cancelalarm(enum alm_id_e alarmid);
/****************************************************************************
* Name: up_rtc_rdalarm
*
* Description:
* Query an alarm configured in hardware.
*
* Input Parameters:
* tp - Location to return the timer match register.
* alarmid - Identifies the alarm to be cancelled
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid);
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: up_rtc_timer_init
*
* Description:
* Init RTC timer.
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) on success; a negated errno on failure
*
****************************************************************************/
int up_rtc_timer_init(void);
#endif /* CONFIG_RTC_DRIVER */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H */

555
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c Normal file
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@ -0,0 +1,555 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spinlock.h>
#include <sys/types.h>
#include <stdbool.h>
#include <string.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/rtc.h>
#include "esp32s3_rtc.h"
#include "hardware/esp32s3_tim.h"
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
struct esp32s3_cbinfo_s
{
volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */
volatile void *priv; /* Private argurment to accompany callback */
};
#endif
/* This is the private type for the RTC state. It must be cast compatible
* with struct rtc_lowerhalf_s.
*/
struct esp32s3_lowerhalf_s
{
/* This is the contained reference to the read-only, lower-half
* operations vtable (which may lie in FLASH or ROM)
*/
const struct rtc_ops_s *ops;
#ifdef CONFIG_RTC_ALARM
/* Alarm callback information */
struct esp32s3_cbinfo_s cbinfo[RTC_ALARM_LAST];
#endif
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Prototypes for static methods in struct rtc_ops_s */
static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower,
struct rtc_time *rtctime);
static int rtc_lh_settime(struct rtc_lowerhalf_s *lower,
const struct rtc_time *rtctime);
static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower);
#ifdef CONFIG_RTC_ALARM
static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid);
static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower,
const struct lower_setalarm_s *alarminfo);
static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower,
const struct lower_setrelative_s *alarminfo);
static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower,
int alarmid);
static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower,
struct lower_rdalarm_s *alarminfo);
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/* ESP32 RTC driver operations */
static const struct rtc_ops_s g_rtc_ops =
{
.rdtime = rtc_lh_rdtime,
.settime = rtc_lh_settime,
.havesettime = rtc_lh_havesettime,
#ifdef CONFIG_RTC_ALARM
.setalarm = rtc_lh_setalarm,
.setrelative = rtc_lh_setrelative,
.cancelalarm = rtc_lh_cancelalarm,
.rdalarm = rtc_lh_rdalarm,
#endif
};
/* ESP32 RTC device state */
static struct esp32s3_lowerhalf_s g_rtc_lowerhalf =
{
.ops = &g_rtc_ops,
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rtc_lh_alarm_callback
*
* Description:
* This is the function that is called from the RTC driver when the alarm
* goes off. It just invokes the upper half drivers callback.
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid)
{
struct esp32s3_lowerhalf_s *lower;
struct esp32s3_cbinfo_s *cbinfo;
rtc_alarm_callback_t cb;
void *priv;
DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST));
lower = (struct esp32s3_lowerhalf_s *)arg;
cbinfo = &lower->cbinfo[alarmid];
/* Sample and clear the callback information to minimize the window in
* time in which race conditions can occur.
*/
cb = (rtc_alarm_callback_t)cbinfo->cb;
priv = (void *)cbinfo->priv;
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Perform the callback */
if (cb != NULL)
{
cb(priv, alarmid);
}
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: rtc_lh_rdtime
*
* Description:
* Returns the current RTC time.
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The location in which to return the current RTC time.
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower,
struct rtc_time *rtctime)
{
#if defined(CONFIG_RTC_HIRES)
struct timespec ts;
int ret;
/* Get the higher resolution time */
ret = up_rtc_gettime(&ts);
if (ret < 0)
{
goto errout;
}
/* Convert the one second epoch time to a struct tm. This operation
* depends on the fact that struct rtc_time and struct tm are cast
* compatible.
*/
if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime))
{
ret = -get_errno();
goto errout;
}
return OK;
errout:
rtcerr("ERROR: failed to get RTC time: %d\n", ret);
return ret;
#else
time_t timer;
/* The resolution of time is only 1 second */
timer = up_rtc_time();
/* Convert the one second epoch time to a struct tm */
if (gmtime_r(&timer, (struct tm *)rtctime) == 0)
{
int errcode = get_errno();
DEBUGASSERT(errcode > 0);
rtcerr("ERROR: gmtime_r failed: %d\n", errcode);
return -errcode;
}
return OK;
#endif
}
/****************************************************************************
* Name: rtc_lh_settime
*
* Description:
* Implements the settime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* rcttime - The new time to set
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
static int rtc_lh_settime(struct rtc_lowerhalf_s *lower,
const struct rtc_time *rtctime)
{
struct timespec ts;
/* Convert the struct rtc_time to a time_t. Here we assume that struct
* rtc_time is cast compatible with struct tm.
*/
ts.tv_sec = mktime((struct tm *)rtctime);
ts.tv_nsec = 0;
/* Now set the time (with a accuracy of seconds) */
return up_rtc_settime(&ts);
}
/****************************************************************************
* Name: rtc_lh_havesettime
*
* Description:
* Implements the havesettime() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
*
* Returned Value:
* Returns true if RTC date-time have been previously set.
*
****************************************************************************/
static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower)
{
if (esp32s3_rtc_get_boot_time() == 0)
{
return false;
}
return true;
}
/****************************************************************************
* Name: rtc_lh_setalarm
*
* Description:
* Set a new alarm. This function implements the setalarm() method of the
* RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower,
const struct lower_setalarm_s *alarminfo)
{
struct esp32s3_lowerhalf_s *priv;
struct esp32s3_cbinfo_s *cbinfo;
struct alm_setalarm_s lowerinfo;
int ret;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) &&
(alarminfo->id < RTC_ALARM_LAST));
priv = (struct esp32s3_lowerhalf_s *)lower;
/* Remember the callback information */
cbinfo = &priv->cbinfo[alarminfo->id];
cbinfo->cb = alarminfo->cb;
cbinfo->priv = alarminfo->priv;
/* Set the alarm */
lowerinfo.as_id = alarminfo->id;
lowerinfo.as_cb = rtc_lh_alarm_callback;
lowerinfo.as_arg = priv;
/* Convert the RTC time to a timespec (1 second accuracy) */
lowerinfo.as_time.tv_sec = mktime((struct tm *)&alarminfo->time);
lowerinfo.as_time.tv_nsec = 0;
/* And set the alarm */
ret = up_rtc_setalarm(&lowerinfo);
if (ret < 0)
{
cbinfo->cb = NULL;
cbinfo->priv = NULL;
}
return ret;
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: rtc_lh_setrelative
*
* Description:
* Set a new alarm relative to the current time. This function implements
* the setrelative() method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to set the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower,
const struct lower_setrelative_s *alarminfo)
{
struct lower_setalarm_s setalarm;
time_t seconds;
int ret = -EINVAL;
irqstate_t flags;
DEBUGASSERT(lower != NULL && alarminfo != NULL);
DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) &&
(alarminfo->id < RTC_ALARM_LAST));
if (alarminfo->reltime > 0)
{
flags = spin_lock_irqsave(NULL);
seconds = alarminfo->reltime;
gmtime_r(&seconds, (struct tm *)&setalarm.time);
/* The set the alarm using this absolute time */
setalarm.id = alarminfo->id;
setalarm.cb = alarminfo->cb;
setalarm.priv = alarminfo->priv;
ret = rtc_lh_setalarm(lower, &setalarm);
spin_unlock_irqrestore(NULL, flags);
}
return ret;
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: rtc_lh_cancelalarm
*
* Description:
* Cancel the current alarm. This function implements the cancelalarm()
* method of the RTC driver interface
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarmid - the alarm id
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid)
{
struct esp32s3_lowerhalf_s *priv;
struct esp32s3_cbinfo_s *cbinfo;
DEBUGASSERT(lower != NULL);
DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST));
priv = (struct esp32s3_lowerhalf_s *)lower;
/* Nullify callback information to reduce window for race conditions */
cbinfo = &priv->cbinfo[alarmid];
cbinfo->cb = NULL;
cbinfo->priv = NULL;
/* Then cancel the alarm */
return up_rtc_cancelalarm((enum alm_id_e)alarmid);
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Name: rtc_lh_rdalarm
*
* Description:
* Query the RTC alarm.
*
* Input Parameters:
* lower - A reference to RTC lower half driver state structure
* alarminfo - Provided information needed to query the alarm
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned
* on any failure.
*
****************************************************************************/
#ifdef CONFIG_RTC_ALARM
static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower,
struct lower_rdalarm_s *alarminfo)
{
struct timespec ts;
int ret;
irqstate_t flags;
DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL);
DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) &&
(alarminfo->id < RTC_ALARM_LAST));
flags = spin_lock_irqsave(NULL);
ret = up_rtc_rdalarm(&ts, alarminfo->id);
localtime_r((const time_t *)&ts.tv_sec,
(struct tm *)alarminfo->time);
spin_unlock_irqrestore(NULL, flags);
return ret;
}
#endif /* CONFIG_RTC_ALARM */
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtc_lowerhalf
*
* Description:
* Instantiate the RTC lower half driver for the ESP32.
*
* Input Parameters:
* None
*
* Returned Value:
* On success, a non-NULL RTC lower interface is returned. NULL is
* returned on any failure.
*
****************************************************************************/
struct rtc_lowerhalf_s *esp32s3_rtc_lowerhalf(void)
{
return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf;
}
/****************************************************************************
* Name: esp32s3_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int esp32s3_rtc_driverinit(void)
{
int ret = ERROR;
struct rtc_lowerhalf_s *lower;
/* Instantiate the ESP32 lower-half RTC driver */
lower = esp32s3_rtc_lowerhalf();
if (lower == NULL)
{
return ret;
}
else
{
/* Bind the lower half driver and register the combined RTC driver
* as /dev/rtc0
*/
ret = rtc_initialize(0, lower);
}
/* Init RTC timer */
up_rtc_timer_init();
return ret;
}

56
arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h Normal file
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@ -0,0 +1,56 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifdef CONFIG_RTC_DRIVER
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32_rtc_driverinit
*
* Description:
* Bind the configuration timer to a timer lower half instance and register
* the timer drivers at 'devpath'
*
* Input Parameters:
* None
*
* Returned Value:
* Zero (OK) is returned on success; A negated errno value is returned
* to indicate the nature of any failure.
*
****************************************************************************/
int esp32_rtc_driverinit(void);
#endif /* CONFIG_RTC_DRIVER */
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H */

195
arch/xtensa/src/esp32s3/esp32s3_rtcheap.c Normal file
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@ -0,0 +1,195 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtcheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/mm/mm.h>
#include <malloc.h>
#include "esp32s3_rtcheap.h"
/****************************************************************************
* Private Data
****************************************************************************/
static struct mm_heap_s *g_rtcheap;
/****************************************************************************
* Extern values declaration
****************************************************************************/
/* These values come from the linker scripts. Check boards/xtensa/esp32s3. */
extern uint8_t _srtcheap[];
extern uint8_t _ertcheap[];
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: esp32s3_rtcheap_initialize
*
* Description:
* Initialize the RTC heap.
*
****************************************************************************/
void esp32s3_rtcheap_initialize(void)
{
void *start;
size_t size;
start = (void *)_srtcheap;
size = _ertcheap - _srtcheap;
g_rtcheap = mm_initialize("rtcheap", start, size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_malloc
*
* Description:
* Allocate memory from the RTC heap.
*
* Parameters:
* size - Size (in bytes) of the memory region to be allocated.
*
****************************************************************************/
void *esp32s3_rtcheap_malloc(size_t size)
{
return mm_malloc(g_rtcheap, size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_calloc
*
* Description:
* Calculates the size of the allocation and allocate memory from
* the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_calloc(size_t n, size_t elem_size)
{
return mm_calloc(g_rtcheap, n, elem_size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_realloc
*
* Description:
* Reallocate memory from the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_realloc(void *ptr, size_t size)
{
return mm_realloc(g_rtcheap, ptr, size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_zalloc
*
* Description:
* Allocate and zero memory from the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_zalloc(size_t size)
{
return mm_zalloc(g_rtcheap, size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_free
*
* Description:
* Free memory from the RTC heap.
*
****************************************************************************/
void esp32s3_rtcheap_free(void *mem)
{
mm_free(g_rtcheap, mem);
}
/****************************************************************************
* Name: esp32s3_rtcheap_memalign
*
* Description:
* memalign requests more than enough space from malloc, finds a region
* within that chunk that meets the alignment request and then frees any
* leading or trailing space.
*
* The alignment argument must be a power of two (not checked). 8-byte
* alignment is guaranteed by normal malloc calls.
*
* Parameters:
* alignment - Requested alignment.
* size - Size (in bytes) of the memory region to be allocated.
*
****************************************************************************/
void *esp32s3_rtcheap_memalign(size_t alignment, size_t size)
{
return mm_memalign(g_rtcheap, alignment, size);
}
/****************************************************************************
* Name: esp32s3_rtcheap_heapmember
*
* Description:
* Check if an address lies in the RTC heap.
*
* Parameters:
* mem - The address to check.
*
* Return Value:
* True if the address is a member of the RTC heap. False if not.
*
****************************************************************************/
bool esp32s3_rtcheap_heapmember(void *mem)
{
return mm_heapmember(g_rtcheap, mem);
}
/****************************************************************************
* Name: esp32s3_rtcheap_mallinfo
*
* Description:
* mallinfo returns a copy of updated current heap information for the
* user heap.
*
* Parameters:
* info - Where memory information will be copied.
*
****************************************************************************/
int esp32s3_rtcheap_mallinfo(struct mallinfo *info)
{
return mm_mallinfo(g_rtcheap, info);
}

149
arch/xtensa/src/esp32s3/esp32s3_rtcheap.h Normal file
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@ -0,0 +1,149 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/esp32s3_rtcheap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTCHEAP_H
#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTCHEAP_H
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
struct mallinfo; /* Forward reference, see malloc.h */
/****************************************************************************
* Name: esp32s3_rtcheap_initialize
*
* Description:
* Initialize the RTC heap.
*
****************************************************************************/
void esp32s3_rtcheap_initialize(void);
/****************************************************************************
* Name: esp32s3_rtcheap_malloc
*
* Description:
* Allocate memory from the RTC heap.
*
* Parameters:
* size - Size (in bytes) of the memory region to be allocated.
*
****************************************************************************/
void *esp32s3_rtcheap_malloc(size_t size);
/****************************************************************************
* Name: esp32s3_rtcheap_calloc
*
* Description:
* Calculates the size of the allocation and allocate memory from
* the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_calloc(size_t n, size_t elem_size);
/****************************************************************************
* Name: esp32s3_rtcheap_realloc
*
* Description:
* Reallocate memory from the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_realloc(void *ptr, size_t size);
/****************************************************************************
* Name: esp32s3_rtcheap_zalloc
*
* Description:
* Allocate and zero memory from the RTC heap.
*
****************************************************************************/
void *esp32s3_rtcheap_zalloc(size_t size);
/****************************************************************************
* Name: esp32s3_rtcheap_free
*
* Description:
* Free memory from the RTC heap.
*
****************************************************************************/
void esp32s3_rtcheap_free(void *mem);
/****************************************************************************
* Name: esp32s3_rtcheap_memalign
*
* Description:
* memalign requests more than enough space from malloc, finds a region
* within that chunk that meets the alignment request and then frees any
* leading or trailing space.
*
* The alignment argument must be a power of two (not checked). 8-byte
* alignment is guaranteed by normal malloc calls.
*
****************************************************************************/
void *esp32s3_rtcheap_memalign(size_t alignment, size_t size);
/****************************************************************************
* Name: esp32s3_rtcheap_heapmember
*
* Description:
* Check if an address lies in the RTC heap.
*
* Parameters:
* mem - The address to check
*
* Return Value:
* True if the address is a member of the RTC heap. False if not.
*
****************************************************************************/
bool esp32s3_rtcheap_heapmember(void *mem);
/****************************************************************************
* Name: esp32s3_rtcheap_mallinfo
*
* Description:
* mallinfo returns a copy of updated current heap information for the
* user heap.
*
****************************************************************************/
int esp32s3_rtcheap_mallinfo(struct mallinfo *info);
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTCHEAP_H */

75
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h
View File

@ -71,8 +71,8 @@
#define RTC_WDT_RESET_LENGTH_1600_NS 6
#define RTC_WDT_RESET_LENGTH_3200_NS 7
#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG
#define RTC_CNTL_TIME0_REG RTC_CNTL_RTC_TIME_LOW0_REG
#define RTC_CNTL_TIME1_REG RTC_CNTL_RTC_TIME_HIGH0_REG
/* RTC_CNTL_RTC_OPTIONS0_REG register
* RTC common configure register
@ -474,6 +474,7 @@
#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S)
#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000ff
#define RTC_CNTL_PLL_BUF_WAIT_S 24
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80;
* XTAL wait cycles in slow_clk_rtc
@ -483,15 +484,18 @@
#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S)
#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003ff
#define RTC_CNTL_XTL_BUF_WAIT_S 14
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16;
* CK8M wait cycles in slow_clk_rtc
*/
#define RTC_CNTL_CK8M_WAIT 0x000000ff
#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S)
#define RTC_CNTL_CK8M_WAIT_V 0x000000ff
#define RTC_CNTL_CK8M_WAIT_S 6
#define RTC_CNTL_CK8M_WAIT 0x000000ff
#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S)
#define RTC_CNTL_CK8M_WAIT_V 0x000000ff
#define RTC_CNTL_CK8M_WAIT_S 6
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5
/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1;
* CPU stall wait cycles in fast_clk_rtc
@ -630,10 +634,11 @@
* minimal sleep cycles in slow_clk_rtc
*/
#define RTC_CNTL_MIN_SLP_VAL 0x000000ff
#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S)
#define RTC_CNTL_MIN_SLP_VAL_V 0x000000ff
#define RTC_CNTL_MIN_SLP_VAL_S 8
#define RTC_CNTL_MIN_SLP_VAL 0x000000ff
#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S)
#define RTC_CNTL_MIN_SLP_VAL_V 0x000000ff
#define RTC_CNTL_MIN_SLP_VAL_S 8
#define RTC_CNTL_MIN_SLP_VAL_MIN 2
/* RTC_CNTL_RTC_TIMER6_REG register
* No public
@ -5831,4 +5836,54 @@
#define RTC_CNTL_DATE_V 0x0fffffff
#define RTC_CNTL_DATE_S 0
/* Deep sleep (power down digital domain) */
#define RTC_SLEEP_PD_DIG BIT(0)
/* Power down RTC peripherals */
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1)
/* Power down RTC SLOW memory */
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2)
/* Power down RTC FAST memory */
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3)
/* RTC FAST and SLOW memories are automatically
* powered up and down along with the CPU
*/
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)
/* Power down VDDSDIO regulator */
#define RTC_SLEEP_PD_VDDSDIO BIT(5)
/* Power down WIFI */
#define RTC_SLEEP_PD_WIFI BIT(6)
/* Power down BT */
#define RTC_SLEEP_PD_BT BIT(7)
/* Power down CPU when in lightsleep, but not restart */
#define RTC_SLEEP_PD_CPU BIT(8)
/* Power down DIG peripherals */
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9)
/* Power down Internal 8M oscillator */
#define RTC_SLEEP_PD_INT_8M BIT(10)
/* Power down main XTAL */
#define RTC_SLEEP_PD_XTAL BIT(11)
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H */

10
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h
View File

@ -441,6 +441,16 @@
#define RTC_PLL_FREQ_320M 320
#define RTC_PLL_FREQ_480M 480
#define DPORT_CPUPERIOD_SEL_80 0
#define DPORT_CPUPERIOD_SEL_160 1
#define DPORT_CPUPERIOD_SEL_240 2
#define DPORT_SOC_CLK_SEL_XTAL 0
#define DPORT_SOC_CLK_SEL_PLL 1
#define DPORT_SOC_CLK_SEL_8M 2
#define RTC_FAST_CLK_FREQ_8M 8500000
#ifndef __ASSEMBLY__
/****************************************************************************

192
arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h Normal file
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@ -0,0 +1,192 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/regi2c_bbpll.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H
/**
* @file regi2c_bbpll.h
* @brief Register definitions for digital PLL (BBPLL)
*
* This file lists register fields of BBPLL, located on an internal
* configuration bus. These definitions are used via macros defined
* in regi2c_ctrl.h, by rtc_clk_cpu_freq_set function in rtc_clk.c.
*/
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 1
#define I2C_BBPLL_IR_CAL_DELAY 0
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
#define I2C_BBPLL_IR_CAL_CK_DIV 0
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
#define I2C_BBPLL_IR_CAL_RSTB 1
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
#define I2C_BBPLL_IR_CAL_START 1
#define I2C_BBPLL_IR_CAL_START_MSB 6
#define I2C_BBPLL_IR_CAL_START_LSB 6
#define I2C_BBPLL_IR_CAL_UNSTOP 1
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
#define I2C_BBPLL_OC_REF_DIV 2
#define I2C_BBPLL_OC_REF_DIV_MSB 3
#define I2C_BBPLL_OC_REF_DIV_LSB 0
#define I2C_BBPLL_OC_DCHGP 2
#define I2C_BBPLL_OC_DCHGP_MSB 6
#define I2C_BBPLL_OC_DCHGP_LSB 4
#define I2C_BBPLL_OC_ENB_FCAL 2
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
#define I2C_BBPLL_OC_DIV_7_0 3
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
#define I2C_BBPLL_RSTB_DIV_ADC 4
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
#define I2C_BBPLL_MODE_HF 4
#define I2C_BBPLL_MODE_HF_MSB 1
#define I2C_BBPLL_MODE_HF_LSB 1
#define I2C_BBPLL_DIV_ADC 4
#define I2C_BBPLL_DIV_ADC_MSB 3
#define I2C_BBPLL_DIV_ADC_LSB 2
#define I2C_BBPLL_DIV_DAC 4
#define I2C_BBPLL_DIV_DAC_MSB 4
#define I2C_BBPLL_DIV_DAC_LSB 4
#define I2C_BBPLL_DIV_CPU 4
#define I2C_BBPLL_DIV_CPU_MSB 5
#define I2C_BBPLL_DIV_CPU_LSB 5
#define I2C_BBPLL_OC_ENB_VCON 4
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
#define I2C_BBPLL_OC_TSCHGP 4
#define I2C_BBPLL_OC_TSCHGP_MSB 7
#define I2C_BBPLL_OC_TSCHGP_LSB 7
#define I2C_BBPLL_OC_DR1 5
#define I2C_BBPLL_OC_DR1_MSB 2
#define I2C_BBPLL_OC_DR1_LSB 0
#define I2C_BBPLL_OC_DR3 5
#define I2C_BBPLL_OC_DR3_MSB 6
#define I2C_BBPLL_OC_DR3_LSB 4
#define I2C_BBPLL_EN_USB 5
#define I2C_BBPLL_EN_USB_MSB 7
#define I2C_BBPLL_EN_USB_LSB 7
#define I2C_BBPLL_OC_DCUR 6
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_INC_CUR 6
#define I2C_BBPLL_INC_CUR_MSB 3
#define I2C_BBPLL_INC_CUR_LSB 3
#define I2C_BBPLL_OC_DHREF_SEL 6
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
#define I2C_BBPLL_OC_DLREF_SEL 6
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
#define I2C_BBPLL_OR_CAL_CAP 8
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
#define I2C_BBPLL_OR_CAL_UDF 8
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
#define I2C_BBPLL_OR_CAL_OVF 8
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
#define I2C_BBPLL_OR_CAL_END 8
#define I2C_BBPLL_OR_CAL_END_MSB 6
#define I2C_BBPLL_OR_CAL_END_LSB 6
#define I2C_BBPLL_OR_LOCK 8
#define I2C_BBPLL_OR_LOCK_MSB 7
#define I2C_BBPLL_OR_LOCK_LSB 7
#define I2C_BBPLL_OC_VCO_DBIAS 9
#define I2C_BBPLL_OC_VCO_DBIAS_MSB 1
#define I2C_BBPLL_OC_VCO_DBIAS_LSB 0
#define I2C_BBPLL_BBADC_DELAY2 9
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
#define I2C_BBPLL_BBADC_DVDD 9
#define I2C_BBPLL_BBADC_DVDD_MSB 5
#define I2C_BBPLL_BBADC_DVDD_LSB 4
#define I2C_BBPLL_BBADC_DREF 9
#define I2C_BBPLL_BBADC_DREF_MSB 7
#define I2C_BBPLL_BBADC_DREF_LSB 6
#define I2C_BBPLL_BBADC_DCUR 10
#define I2C_BBPLL_BBADC_DCUR_MSB 1
#define I2C_BBPLL_BBADC_DCUR_LSB 0
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3
#define I2C_BBPLL_DTEST 10
#define I2C_BBPLL_DTEST_MSB 5
#define I2C_BBPLL_DTEST_LSB 4
#define I2C_BBPLL_ENT_ADC 10
#define I2C_BBPLL_ENT_ADC_MSB 7
#define I2C_BBPLL_ENT_ADC_LSB 6
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_BBPLL_H */

69
arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h Normal file
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@ -0,0 +1,69 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/regi2c_ctrl.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_CTRL_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_CTRL_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include "esp32s3_soc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Analog function control register */
#define I2C_MST_ANA_CONF0_REG 0x6000E040
#define I2C_MST_BBPLL_STOP_FORCE_HIGH (BIT(2))
#define I2C_MST_BBPLL_STOP_FORCE_LOW (BIT(3))
/* ROM functions which read/write internal control bus */
extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id,
uint8_t reg_add);
extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb);
extern void rom_i2c_writereg(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t data);
extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
/* Convenience macros for the above functions, these use register
* definitions from regi2c_bbpll.h/regi2c_dig_reg.h/regi2c_lp_bias.h/
* regi2c_bias.h header files.
*/
#define REGI2C_WRITE_MASK(block, reg_add, indata) \
rom_i2c_writereg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata)
#define REGI2C_READ_MASK(block, reg_add) \
rom_i2c_readreg_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB)
#define REGI2C_WRITE(block, reg_add, indata) \
rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)
#define REGI2C_READ(block, reg_add) \
rom_i2c_readreg(block, block##_HOSTID, reg_add)
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_CTRL_H */

59
arch/xtensa/src/esp32s3/hardware/regi2c_dig_reg.h Normal file
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@ -0,0 +1,59 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/regi2c_dig_reg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_DIG_REG_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_DIG_REG_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register definitions for digital to get rtc voltage & digital voltage
* by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
*/
#define I2C_DIG_REG 0x6D
#define I2C_DIG_REG_HOSTID 1
#define I2C_DIG_REG_EXT_RTC_DREG 4
#define I2C_DIG_REG_EXT_RTC_DREG_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_LSB 0
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP 5
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_EXT_DIG_DREG 6
#define I2C_DIG_REG_EXT_DIG_DREG_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_LSB 0
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP 7
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB 4
#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB 0
#define I2C_DIG_REG_XPD_RTC_REG 13
#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
#define I2C_DIG_REG_XPD_DIG_REG 13
#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_DIG_REG_H */

48
arch/xtensa/src/esp32s3/hardware/regi2c_lp_bias.h Normal file
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@ -0,0 +1,48 @@
/****************************************************************************
* arch/xtensa/src/esp32s3/hardware/regi2c_lp_bias.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_LP_BIAS_H
#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_LP_BIAS_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register definitions for analog to calibrate o_code for getting a more
* precise voltage. This file lists register fields of low power dbais,
* located on an internal configuration bus.
*/
#define I2C_ULP 0x61
#define I2C_ULP_HOSTID 1
#define I2C_ULP_IR_RESETB 0
#define I2C_ULP_IR_RESETB_MSB 0
#define I2C_ULP_IR_RESETB_LSB 0
#define I2C_ULP_O_DONE_FLAG 3
#define I2C_ULP_O_DONE_FLAG_MSB 0
#define I2C_ULP_O_DONE_FLAG_LSB 0
#define I2C_ULP_BG_O_DONE_FLAG 3
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_REGI2C_LP_BIAS_H */

8
boards/xtensa/esp32s3/common/scripts/esp32s3_rom.ld
View File

@ -2122,10 +2122,10 @@ rom_get_bbgain_db = 0x40005d18;
rom_get_data_sat = 0x40005d24;
rom_get_i2c_read_mask = 0x40005d30;
rom_get_pwctrl_correct = 0x40005d3c;
rom_i2c_readReg = 0x40005d48;
rom_i2c_readReg_Mask = 0x40005d54;
rom_i2c_writeReg = 0x40005d60;
rom_i2c_writeReg_Mask = 0x40005d6c;
rom_i2c_readreg = 0x40005d48;
rom_i2c_readreg_mask = 0x40005d54;
rom_i2c_writereg = 0x40005d60;
rom_i2c_writereg_mask = 0x40005d6c;
rom_index_to_txbbgain = 0x40005d78;
rom_iq_est_disable = 0x40005d84;
rom_iq_est_enable = 0x40005d90;