diff --git a/configs/nucleo-l476rg/include/nucleo-l476rg.h b/configs/nucleo-l476rg/include/nucleo-l476rg.h
index e49f7c1cf0..c3e861280d 100644
--- a/configs/nucleo-l476rg/include/nucleo-l476rg.h
+++ b/configs/nucleo-l476rg/include/nucleo-l476rg.h
@@ -190,8 +190,8 @@
 #define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(10)
 #define STM32L4_PLLCFG_PLLP             0
 #undef  STM32L4_PLLCFG_PLLP_ENABLED
-#define STM32L4_PLLCFG_PLLQ             0
-#undef  STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLQ             RCC_PLLCFG_PLLQ_2
+#define STM32L4_PLLCFG_PLLQ_ENABLED
 #define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR(2)
 #define STM32L4_PLLCFG_PLLR_ENABLED
 
@@ -199,8 +199,8 @@
 #define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(10)
 #define STM32L4_PLLSAI1CFG_PLLP         0
 #undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
-#define STM32L4_PLLSAI1CFG_PLLQ         0
-#undef  STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_4
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
 #define STM32L4_PLLSAI1CFG_PLLR         RCC_PLLSAI1CFG_PLLR(2)
 #undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
 
@@ -213,6 +213,11 @@
 
 #define STM32L4_SYSCLK_FREQUENCY  80000000ul
 
+/* CLK48 will come from PLLSAI1 (implicitly Q) */
+
+#define STM32L4_USE_CLK48
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
 /* AHB clock (HCLK) is SYSCLK (80MHz) */
 
 #define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */