Gix spelling in inclusion guards
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@ -34,8 +34,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
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#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H
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/************************************************************************************
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* Included Files
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@ -255,4 +255,4 @@
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#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
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#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
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#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H */
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_SPI_H */
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@ -34,8 +34,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
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#define __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H
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/************************************************************************************
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* Included Files
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@ -368,4 +368,4 @@
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#define USART_TDR_MASK (0x1ff << USART_TDR_SHIFT)
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#endif /* CONFIG_STM32F7_STM32F74XX || CONFIG_STM32F7_STM32F75XX */
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#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
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#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_UART_H */
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@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32F7_STM32_UART_H
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#define __ARCH_ARM_STC_STM32F7_STM32_UART_H
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#ifndef __ARCH_ARM_SRC_STM32F7_STM32_UART_H
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#define __ARCH_ARM_SRC_STM32F7_STM32_UART_H
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/************************************************************************************
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* Included Files
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@ -342,4 +342,4 @@ void stm32_serial_dma_poll(void);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_STC_STM32F7_STM32_UART_H */
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#endif /* __ARCH_ARM_SRC_STM32F7_STM32_UART_H */
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