Add STM32L15X segment LCD register definitions; Updated documentatin and README files
This commit is contained in:
Gregory Nutt
parent
e4d906960a
commit
28112cea0f
@ -4756,3 +4756,6 @@
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vector definition file, the STM32L-Discovery NSH port now seems to be
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fully functional. Also fixed an error that was causing the LEDs to be
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controlled incorrectly (2013-5-21).
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* arch/arm/src/stm32/chip/stm32_lcd.h: Add definitions for STM32L15X
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segment LCD (2013-5-21).
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@ -2124,7 +2124,7 @@ nsh>
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Initial support for the STM32L-Discovery was released in NuttX-6.28.
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This initial support is very minimal:
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There is a configuration using the NuttShell (<a href="NuttShell.html">NSH</a>) that might be the basis for an application development.
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As of this writing, more device drivers are needed to make this a more complete port.
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As of this writing, a few more things are needed to make this a more complete port: 1) Verfication of more device drivers, and 2) logic that actually uses the low-power consumption modes of the EnergyLite part.
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</p>
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<p>
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<b>Memory Usage</b>.
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@ -4371,6 +4371,7 @@ pascal-3.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org>
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<li>Cygwin is a trademark of Red Hat, Incorporated.</li>
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<li>Linux is a registered trademark of Linus Torvalds.</li>
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<li>Eagle-100 is a trademark of <a href=" http://www.micromint.com/">Micromint USA, LLC</a>.
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<li>EnergyLite is a trademark of STMicroelectronics.</li>
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<li>LPC2148 is a trademark of NXP Semiconductors.</li>
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<li>TI is a tradename of Texas Instruments Incorporated.</li>
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<li>UNIX is a registered trademark of The Open Group.</li>
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@ -4378,8 +4379,8 @@ pascal-3.0 2011-05-15 Gregory Nutt <gnutt@nuttx.org>
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<li>ZDS, ZNEO, Z16F, Z80, and Zilog are a registered trademark of Zilog, Inc.</li>
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</ul>
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<p>
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NOTE: NuttX is <i>not</i> licensed to use the POSIX trademark. NuttX uses the POSIX
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standard as a development guideline only.
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NOTE: NuttX is <i>not</i> licensed to use the POSIX trademark.
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NuttX uses the POSIX standard as a development guideline only.
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</p>
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</small>
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212
arch/arm/src/stm32/chip/stm32_lcd.h
Normal file
212
arch/arm/src/stm32/chip/stm32_lcd.h
Normal file
@ -0,0 +1,212 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_lcd.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H
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#define __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/* These definitions are valid only if the MCU supports a segment LCD */
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#if STM32_NLCD > 0
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_LCD_CR_OFFSET 0x0000 /* LCD control register */
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#define STM32_LCD_FCR_OFFSET 0x0004 /* LCD frame control register */
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#define STM32_LCD_SR_OFFSET 0x0008 /* LCD status register */
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#define STM32_LCD_CLR_OFFSET 0x000c /* LCD clear register */
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#define STM32_LCD_RAM_OFFSET(n) (0x0014+((n) << 3)) /* LCD display memory, COMn */
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#define STM32_LCD_RAML_OFFSET(n) (0x0014+((n) << 3)) /* LCD display memory, COMn, S00-S31 */
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#define STM32_LCD_RAMH_OFFSET(n) (0x0018+((n) << 3)) /* LCD display memory, COMn, S32-S39 */
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#define STM32_LCD_RAM0L_OFFSET 0x0014 /* LCD display memory, COM0, S00-S31 */
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#define STM32_LCD_RAM0H_OFFSET 0x0018 /* LCD display memory, COM0, S32-S39 */
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#define STM32_LCD_RAM1L_OFFSET 0x001c /* LCD display memory, COM1, S00-S31 */
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#define STM32_LCD_RAM1H_OFFSET 0x0020 /* LCD display memory, COM1, S32-S39 */
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#define STM32_LCD_RAM2L_OFFSET 0x0024 /* LCD display memory, COM2, S00-S31 */
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#define STM32_LCD_RAM2H_OFFSET 0x0028 /* LCD display memory, COM2, S32-S39 */
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#define STM32_LCD_RAM3L_OFFSET 0x002c /* LCD display memory, COM3, S00-S31 */
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#define STM32_LCD_RAM3H_OFFSET 0x0020 /* LCD display memory, COM3, S32-S39 */
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#define STM32_LCD_RAM4L_OFFSET 0x0034 /* LCD display memory, COM4, S00-S31 */
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#define STM32_LCD_RAM4H_OFFSET 0x0038 /* LCD display memory, COM4, S32-S39 */
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#define STM32_LCD_RAM5L_OFFSET 0x003c /* LCD display memory, COM5, S00-S31 */
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#define STM32_LCD_RAM5H_OFFSET 0x0040 /* LCD display memory, COM5, S32-S39 */
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#define STM32_LCD_RAM6L_OFFSET 0x0044 /* LCD display memory, COM6, S00-S31 */
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#define STM32_LCD_RAM6H_OFFSET 0x0048 /* LCD display memory, COM6, S32-S39 */
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#define STM32_LCD_RAM7L_OFFSET 0x004c /* LCD display memory, COM7, S00-S31 */
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#define STM32_LCD_RAM7H_OFFSET 0x0050 /* LCD display memory, COM7, S32-S39 */
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/* Register Addresses ***************************************************************/
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#define STM32_LCD_CR (STM32_LCD_BASE+STM32_LCD_CR_OFFSET)
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#define STM32_LCD_FCR (STM32_LCD_BASE+STM32_LCD_FCR_OFFSET)
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#define STM32_LCD_SR (STM32_LCD_BASE+STM32_LCD_SR_OFFSET)
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#define STM32_LCD_CLR (STM32_LCD_BASE+STM32_LCD_CLR_OFFSET)
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#define STM32_LCD_RAM(n) (STM32_LCD_BASE+STM32_LCD_RAM_OFFSET(n))
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#define STM32_LCD_RAML(n) (STM32_LCD_BASE+STM32_LCD_RAML_OFFSET(n))
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#define STM32_LCD_RAMH(n) (STM32_LCD_BASE+STM32_LCD_RAMH_OFFSET(n))
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#define STM32_LCD_RAM0L (STM32_LCD_BASE+STM32_LCD_RAM0L_OFFSET)
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#define STM32_LCD_RAM0H (STM32_LCD_BASE+STM32_LCD_RAM0H_OFFSET)
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#define STM32_LCD_RAM1L (STM32_LCD_BASE+STM32_LCD_RAM1L_OFFSET)
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#define STM32_LCD_RAM1H (STM32_LCD_BASE+STM32_LCD_RAM1H_OFFSET)
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#define STM32_LCD_RAM2L (STM32_LCD_BASE+STM32_LCD_RAM2L_OFFSET)
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#define STM32_LCD_RAM2H (STM32_LCD_BASE+STM32_LCD_RAM2H_OFFSET)
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#define STM32_LCD_RAM3L (STM32_LCD_BASE+STM32_LCD_RAM3L_OFFSET)
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#define STM32_LCD_RAM3H (STM32_LCD_BASE+STM32_LCD_RAM3H_OFFSET)
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#define STM32_LCD_RAM4L (STM32_LCD_BASE+STM32_LCD_RAM4L_OFFSET)
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#define STM32_LCD_RAM4H (STM32_LCD_BASE+STM32_LCD_RAM4H_OFFSET)
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#define STM32_LCD_RAM5L (STM32_LCD_BASE+STM32_LCD_RAM5L_OFFSET)
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#define STM32_LCD_RAM5H (STM32_LCD_BASE+STM32_LCD_RAM5H_OFFSET)
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#define STM32_LCD_RAM6L (STM32_LCD_BASE+STM32_LCD_RAM6L_OFFSET)
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#define STM32_LCD_RAM6H (STM32_LCD_BASE+STM32_LCD_RAM6H_OFFSET)
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#define STM32_LCD_RAM7L (STM32_LCD_BASE+STM32_LCD_RAM7L_OFFSET)
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#define STM32_LCD_RAM7H (STM32_LCD_BASE+STM32_LCD_RAM7H_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* LCD control register */
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#define LCD_CR_LCDEN (1 << 0) /* Bit 0: LCD controller enable */
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#define LCD_CR_VSEL (1 << 1) /* Bit 1: Voltage source selection */
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#define LCD_CR_DUTY_SHIFT (2) /* Bits 2-4: Duty selection */
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#define LCD_CR_DUTY_MASK (7 << LCD_CR_DUTY_SHIFT)
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# define LCD_CR_DUTY_STATIC (7 << LCD_CR_DUTY_SHIFT) /* 000: Static duty */
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# define LCD_CR_DUTY_1TO2 (7 << LCD_CR_DUTY_SHIFT) /* 001: 1/2 duty */
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# define LCD_CR_DUTY_1TO3 (7 << LCD_CR_DUTY_SHIFT) /* 010: 1/3 duty */
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# define LCD_CR_DUTY_1TO4 (7 << LCD_CR_DUTY_SHIFT) /* 011: 1/4 duty */
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# define LCD_CR_DUTY_1TO8 (7 << LCD_CR_DUTY_SHIFT) /* 100: 1/8 duty */
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#define LCD_CR_BIAS_SHIFT (5) /* Bits 5-6: Bias selector */
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#define LCD_CR_BIAS_MASK (3 << LCD_CR_BIAS_SHIFT)
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# define LCD_CR_BIAS_1TO4 (3 << LCD_CR_BIAS_SHIFT) /* 00: Bias 1/4 */
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# define LCD_CR_BIAS_1TO2 (3 << LCD_CR_BIAS_SHIFT) /* 01: Bias 1/2 */
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# define LCD_CR_BIAS_1TO3 (3 << LCD_CR_BIAS_SHIFT) /* 10: Bias 1/3 */
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/* Bits 8-31 Reserved */
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/* LCD frame control register */
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#define LCD_FCR_HD (1 << 0) /* Bit 0: High drive enable */
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#define LCD_FCR_SOFIE (1 << 1) /* Bit 1: Start of frame interrupt enable */
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/* Bit 2 Reserved */
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#define LCD_FCR_UDDIE (1 << 3) /* Bit 3: Update display done interrupt enable */
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#define LCD_FCR_PON_SHIFT (4) /* Bits 4-6: Pulse ON duration */
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#define LCD_FCR_PON_MASK (7 << LCD_FCR_PON_SHIFT)
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# define LCD_FCR_PON(n) ((n) << LCD_FCR_PON_SHIFT) /* n=0-7 */
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#define LCD_FCR_DEAD_SHIFT (7) /* Bits 7-9: Dead time duration */
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#define LCD_FCR_DEAD_MASK (7 << LCD_FCR_DEAD_SHIFT)
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# define LCD_FCR_DEAD_NONE (7 << LCD_FCR_DEAD_SHIFT)
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# define LCD_FCR_DEAD(n) ((n) << LCD_FCR_DEAD_SHIFT) /* n=1..7 */
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#define LCD_FCR_CC_SHIFT (10) /* Bits 10-12: Contrast control */
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#define LCD_FCR_CC_MASK (7 << LCD_FCR_CC_SHIFT)
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# define LCD_FCR_CC_VLCD(n) ((n) << LCD_FCR_CC_SHIFT) /* VLCDn, n=0..7 */
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#define LCD_FCR_BLINKF_SHIFT (13) /* Bits 13-15: Blink frequency selection */
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#define LCD_FCR_BLINKF_MASK (7 << LCD_FCR_BLINKF_SHIFT)
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# define LCD_FCR_BLINKF_DIV8 (0 << LCD_FCR_BLINKF_SHIFT) /* 000: fLCD/8 */
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# define LCD_FCR_BLINKF_DIV16 (1 << LCD_FCR_BLINKF_SHIFT) /* 001: fLCD/16 */
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# define LCD_FCR_BLINKF_DIV32 (2 << LCD_FCR_BLINKF_SHIFT) /* 010: fLCD/32 */
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# define LCD_FCR_BLINKF_DIV64 (3 << LCD_FCR_BLINKF_SHIFT) /* 011: fLCD/64 */
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# define LCD_FCR_BLINKF_DIV128 (4 << LCD_FCR_BLINKF_SHIFT) /* 100: fLCD/128 */
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# define LCD_FCR_BLINKF_DIV256 (5 << LCD_FCR_BLINKF_SHIFT) /* 101: fLCD/256 */
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# define LCD_FCR_BLINKF_DIV512 (6 << LCD_FCR_BLINKF_SHIFT) /* 110: fLCD/512 */
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# define LCD_FCR_BLINKF_DIV1024 (7 << LCD_FCR_BLINKF_SHIFT) /* 111: fLCD/1024 */
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#define LCD_FCR_BLINK_SHIFT (16) /* Bits 16-17: Blink mode selection */
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#define LCD_FCR_BLINK_MASK (3 << LCD_FCR_BLINK_SHIFT)
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# define LCD_FCR_BLINK_DISABLE (0 << LCD_FCR_BLINK_SHIFT) /* 00: Blink disabled */
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# define LCD_FCR_BLINK_S0C0 (1 << LCD_FCR_BLINK_SHIFT) /* 01: Blink enabled on SEG[0], COM[0] (1 pixel) */
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# define LCD_FCR_BLINK_S0CALL (2 << LCD_FCR_BLINK_SHIFT) /* 10: Blink enabled on SEG[0], all COMs */
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# define LCD_FCR_BLINK_SALLCALL (3 << LCD_FCR_BLINK_SHIFT) /* 11: Blink enabled on all SEGs and all COMs */
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#define LCD_FCR_DIV_SHIFT (18) /* Bits 18-21: DIV clock divider */
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#define LCD_FCR_DIV_MASK (15 << LCD_FCR_DIV_SHIFT)
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# define LCD_FCR_DIV(n) (((n)-16) << LCD_FCR_DIV_SHIFT) /* n=16-31 */
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#define LCD_FCR_PS_SHIFT (22) /* Bits 22-25: PS 16-bit prescaler */
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#define LCD_FCR_PS_MASK (15 << LCD_FCR_PS_SHIFT)
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# define LCD_FCR_PS_DIV1 (0 << LCD_FCR_PS_SHIFT) /* 0000: ck_ps = LCDCLK */
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# define LCD_FCR_PS_DIV2 (1 << LCD_FCR_PS_SHIFT) /* 0001: ck_ps = LCDCLK/2 */
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# define LCD_FCR_PS_DIV4 (2 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4 */
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# define LCD_FCR_PS_DIV8 (3 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8 */
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# define LCD_FCR_PS_DIV16 (4 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16 */
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# define LCD_FCR_PS_DIV32 (5 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32 */
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# define LCD_FCR_PS_DIV64 (6 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/64 */
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# define LCD_FCR_PS_DIV128 (7 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/128 */
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# define LCD_FCR_PS_DIV256 (8 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/256 */
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# define LCD_FCR_PS_DIV512 (9 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/512 */
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# define LCD_FCR_PS_DIV1024 (10 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/1024 */
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# define LCD_FCR_PS_DIV2048 (11 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/2048 */
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# define LCD_FCR_PS_DIV4096 (12 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/4096 */
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# define LCD_FCR_PS_DIV8192 (13 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/8192 */
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# define LCD_FCR_PS_DIV16384 (14 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/16384 */
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# define LCD_FCR_PS_DIV32768 (15 << LCD_FCR_PS_SHIFT) /* 0011: ck_ps = LCDCLK/32768 */
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/* Bits 26-31 Reserved
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/* LCD status register */
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#define LCD_SR_ENS (1 << 0) /* Bit 0: LCD enabled status */
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#define LCD_SR_SOF (1 << 1) /* Bit 1: Start of frame flag */
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#define LCD_SR_UDR (1 << 2) /* Bit 2: Update display request */
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#define LCD_SR_UDD (1 << 3) /* Bit 3: Update Display Done */
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#define LCD_SR_RDY (1 << 4) /* Bit 4: Ready flag */
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#define LCD_SR_FCRSF (1 << 5) /* Bit 5: LCD Frame Control Register Synchronization flag */
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/* Bits 6-31 Reserved
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/* LCD clear register */
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/* Bit 0 Reserved */
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#define LCD_CLR_SOFC (1 << 1) /* Bit 1: Start of frame flag clear */
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/* Bit 2 Reserved */
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#define LCD_CLR_UDDC (1 << 2) /* Bit 3: Update display done clear
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/* Bits 31:2-31 Reserved */
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/* LCD display memory, COMn, S00-S31 */
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#define LCD_RAML_S(n) (1 << (n))
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/* LCD display memory, COMn, S32-S39 */
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#define LCD_RAMH_S(n) (1 << ((n)-32))
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#endif /* STM32_NLCD */
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#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32_LCD_H */
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@ -520,10 +520,11 @@ CONFIGURATION
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6. This configuration has been used for verifying the touchscreen on
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on the 4.3" LCD module.
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a) As of this writing, this touchscreen is still not function.
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Rommel Marcelo has tracked this problem done to noise on the
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a) As of this writing, this touchscreen is still not functional.
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Rommel Marcelo has tracked this problem down to noise on the
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PENIRQ interrupt. There are so many false interrupts that
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the NuttX interrupt-driven touchscreen driver cannot be used.
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Other compatible LCDs, however, may not have this issue.
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b) You can enable the touchscreen by modifying the configuration
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in the following ways:
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@ -447,9 +447,17 @@ RS-232 transceiver.
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NOTE: The crystal X3 is not installed on the STM32L3-Discovery. As a
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result, the HSE clock is not availabled and the less acurate HSI must be
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used. This may limit the accuracy of the computed baud, especially at
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higher BAUD.
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higher BAUD. The HSI is supposedly calibrated in the factory to within 1%
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at room temperatures so perhaps this not a issue.
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A USB serial console is another option.
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I have had no problems using the USART1 with PA9 and PA10 with a 3.3-5V
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RS-232 transceiver module at 57600 baud. I have not tried higher baud rates.
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There is no support for a USB serial connector on the STM32L-Discovery board.
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The STM32L152 does support USB, but the USB pins are "free I/O" on the board
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and no USB connector is provided. So the use of a USB console is not option.
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If you need console output, you will need to disable either LCD (and use any
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USART) or the LEDs (and use USART1)
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Debugging
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=========
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@ -712,7 +720,7 @@ Where <subdir> is one of the following:
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USB converter. The UART1 TX and RX pins should be available on
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PA9 and PA10, respectively.
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The serial console is configured for 57600 8N1
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The serial console is configured for 57600 8N1 by default.
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3. Support for NSH built-in applications is *not* enabled.
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@ -723,44 +731,3 @@ Where <subdir> is one of the following:
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CONFIG_HOST_WINDOWS=y : Builds under Windows
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CONFIG_WINDOWS_CYGWIN=y : Using Cygwin
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CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW=y : CodeSourcery for Windows
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5. This configuration can support USB (CDC/ACM device)
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||||
a) Enable NSH builtin application support
|
||||
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
|
||||
b) Enable USB device and CDC/ACM class support
|
||||
|
||||
CONFIG_STM32_USB=y : STM32 USB device support
|
||||
CONFIG_USBDEV=y : USB device support must be enabled
|
||||
CONFIG_CDCACM=y : The CDC/ACM driver must be built
|
||||
CONFIG_NSH_BUILTIN_APPS=y : NSH built-in application support must be enabled
|
||||
CONFIG_NSH_ARCHINIT=y : To perform USB initialization
|
||||
|
||||
c) Enable the CDC/ACM example
|
||||
|
||||
The CDC/ACM example is included as two NSH "built-in" commands.
|
||||
|
||||
CONFIG_EXAMPLES_CDCACM=y : Enable apps/examples/cdcacm
|
||||
|
||||
The two commands are:
|
||||
|
||||
sercon : Connect the serial device a create /dev/ttyACM0
|
||||
serdis : Disconnect the serial device.
|
||||
|
||||
NOTE: The serial connections/disconnections do not work as advertised.
|
||||
This is because the STM32L-Discovery board does not provide circuitry for
|
||||
control of the "soft connect" USB pullup. As a result, the host PC
|
||||
does not know the USB has been logically connected or disconnected. You
|
||||
have to follow these steps to use USB:
|
||||
|
||||
1) Start NSH with USB disconnected
|
||||
2) enter to 'sercon' command to start the CDC/ACM device, then
|
||||
3) Connect the USB device to the host.
|
||||
|
||||
and to close the connection:
|
||||
|
||||
4) Disconnect the USB device from the host
|
||||
5) Enter the 'serdis' command
|
||||
|
||||
Loading…
Reference in New Issue
Block a user