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Make some spacing comply better with coding standard

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This commit is contained in:
Gregory Nutt 2015-10-06 16:23:47 -06:00
parent 0ca999e119
commit 281c6cc704
27 changed files with 131 additions and 130 deletions
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6
arch/arm/src/a1x/a1x_boot.c
View File

@ -268,9 +268,9 @@ static void a1x_copyvectorblock(void)
* 0xffff0000)
*/
src = (uint32_t*)&_vector_start;
end = (uint32_t*)&_vector_end;
dest = (uint32_t*)(A1X_VECTOR_VSRAM + VECTOR_TABLE_OFFSET);
src = (uint32_t *)&_vector_start;
end = (uint32_t *)&_vector_end;
dest = (uint32_t *)(A1X_VECTOR_VSRAM + VECTOR_TABLE_OFFSET);
while (src < end)
{

10
arch/arm/src/a1x/a1x_lowputc.c
View File

@ -264,15 +264,15 @@ void a1x_lowsetup(void)
/* Clear fifos */
putreg32(UART_FCR_RFIFOR|UART_FCR_XFIFOR, CONSOLE_BASE+A1X_UART_FCR_OFFSET);
putreg32(UART_FCR_RFIFOR | UART_FCR_XFIFOR, CONSOLE_BASE + A1X_UART_FCR_OFFSET);
/* Set trigger */
putreg32(UART_FCR_FIFOE|UART_FCR_RT_HALF, CONSOLE_BASE+A1X_UART_FCR_OFFSET);
putreg32(UART_FCR_FIFOE | UART_FCR_RT_HALF, CONSOLE_BASE + A1X_UART_FCR_OFFSET);
/* Set up the LCR and set DLAB=1 */
putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+A1X_UART_LCR_OFFSET);
putreg32(CONSOLE_LCR_VALUE | UART_LCR_DLAB, CONSOLE_BASE + A1X_UART_LCR_OFFSET);
/* Set the BAUD divisor */
@ -285,8 +285,8 @@ void a1x_lowsetup(void)
/* Configure the FIFOs */
putreg32(UART_FCR_RT_HALF|UART_FCR_XFIFOR|UART_FCR_RFIFOR|UART_FCR_FIFOE,
CONSOLE_BASE+A1X_UART_FCR_OFFSET);
putreg32(UART_FCR_RT_HALF | UART_FCR_XFIFOR | UART_FCR_RFIFOR | UART_FCR_FIFOE,
CONSOLE_BASE + A1X_UART_FCR_OFFSET);
#endif
#endif /* HAVE_UART_DEVICE */
}

49
arch/arm/src/a1x/a1x_serial.c
View File

@ -948,17 +948,17 @@ static inline uint32_t a1x_uartdl(uint32_t baud)
static int up_setup(struct uart_dev_s *dev)
{
#ifndef CONFIG_SUPPRESS_UART_CONFIG
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint16_t dl;
uint32_t lcr;
/* Clear fifos */
up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_RFIFOR|UART_FCR_XFIFOR));
up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_RFIFOR | UART_FCR_XFIFOR));
/* Set trigger */
up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_FIFOE|UART_FCR_RT_HALF));
up_serialout(priv, A1X_UART_FCR_OFFSET, (UART_FCR_FIFOE | UART_FCR_RT_HALF));
/* Set up the IER */
@ -1019,7 +1019,8 @@ static int up_setup(struct uart_dev_s *dev)
/* Configure the FIFOs */
up_serialout(priv, A1X_UART_FCR_OFFSET,
(UART_FCR_RT_HALF|UART_FCR_XFIFOR|UART_FCR_RFIFOR|UART_FCR_FIFOE));
(UART_FCR_RT_HALF | UART_FCR_XFIFOR | UART_FCR_RFIFOR |
UART_FCR_FIFOE));
/* Enable Auto-Flow Control in the Modem Control Register */
@ -1041,7 +1042,7 @@ static int up_setup(struct uart_dev_s *dev)
static void up_shutdown(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disableuartint(priv, NULL);
}
@ -1062,7 +1063,7 @@ static void up_shutdown(struct uart_dev_s *dev)
static int up_attach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret;
/* Attach and enable the IRQ */
@ -1070,11 +1071,11 @@ static int up_attach(struct uart_dev_s *dev)
ret = irq_attach(priv->irq, priv->handler);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
*/
/* Enable the interrupt (RX and TX interrupts are still disabled
* in the UART
*/
up_enable_irq(priv->irq);
up_enable_irq(priv->irq);
}
return ret;
@ -1092,7 +1093,7 @@ static int up_attach(struct uart_dev_s *dev)
static void up_detach(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_disable_irq(priv->irq);
irq_detach(priv->irq);
}
@ -1115,7 +1116,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
uint32_t status;
int passes;
priv = (struct up_dev_s*)dev->priv;
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
* until we have been looping for a long time.
@ -1268,7 +1269,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
{
struct inode *inode = filep->f_inode;
struct uart_dev_s *dev = inode->i_private;
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
int ret = OK;
switch (cmd)
@ -1276,7 +1277,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
case TIOCSERGSTRUCT:
{
struct up_dev_s *user = (struct up_dev_s*)arg;
struct up_dev_s *user = (struct up_dev_s *)arg;
if (!user)
{
ret = -EINVAL;
@ -1309,7 +1310,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
#ifdef CONFIG_SERIAL_TERMIOS
case TCGETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
if (!termiosp)
{
@ -1329,7 +1330,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
case TCSETS:
{
struct termios *termiosp = (struct termios*)arg;
struct termios *termiosp = (struct termios *)arg;
uint32_t lcr; /* Holds current values of line control register */
uint16_t dl; /* Divisor latch */
@ -1391,7 +1392,7 @@ static int up_ioctl(struct file *filep, int cmd, unsigned long arg)
static int up_receive(struct uart_dev_s *dev, uint32_t *status)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
uint32_t rbr;
*status = up_serialin(priv, A1X_UART_LSR_OFFSET);
@ -1409,7 +1410,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
static void up_rxint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
if (enable)
{
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
@ -1434,7 +1435,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_DR) != 0);
}
@ -1448,7 +1449,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
up_serialout(priv, A1X_UART_THR_OFFSET, (uint32_t)ch);
}
@ -1462,7 +1463,7 @@ static void up_send(struct uart_dev_s *dev, int ch)
static void up_txint(struct uart_dev_s *dev, bool enable)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
irqstate_t flags;
flags = irqsave();
@ -1498,7 +1499,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
}
@ -1512,7 +1513,7 @@ static bool up_txready(struct uart_dev_s *dev)
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
return ((up_serialin(priv, A1X_UART_LSR_OFFSET) & UART_LSR_THRE) != 0);
}
@ -1653,7 +1654,7 @@ void up_serialinit(void)
int up_putc(int ch)
{
#ifdef HAVE_SERIAL_CONSOLE
struct up_dev_s *priv = (struct up_dev_s*)CONSOLE_DEV.priv;
struct up_dev_s *priv = (struct up_dev_s *)CONSOLE_DEV.priv;
uint32_t ier;
up_disableuartint(priv, &ier);
#endif

2
arch/arm/src/arm/up_allocpage.c
View File

@ -236,7 +236,7 @@ int up_allocpage(FAR struct tcb_s *tcb, FAR void **vpage)
/* Finally, return the virtual address of allocated page */
*vpage = (void*)(vaddr & ~PAGEMASK);
*vpage = (void *)(vaddr & ~PAGEMASK);
return OK;
}

10
arch/arm/src/arm/up_assert.c
View File

@ -126,7 +126,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t*)stack;
uint32_t *ptr = (uint32_t *)stack;
lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
@ -153,7 +153,7 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t*)&current_regs[regs];
uint32_t *ptr = (uint32_t *)&current_regs[regs];
lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
@ -198,7 +198,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace, FAR void *arg)
#ifdef CONFIG_ARCH_STACKDUMP
static void up_dumpstate(void)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
uint32_t sp = up_getsp();
uint32_t ustackbase;
uint32_t ustacksize;
@ -310,7 +310,7 @@ static void _up_assert(int errorcode)
{
/* Are we in an interrupt handler or the idle task? */
if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
@ -340,7 +340,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);

6
arch/arm/src/arm/up_blocktask.c
View File

@ -76,7 +76,7 @@
void up_block_task(struct tcb_s *tcb, tstate_t task_state)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
/* Verify that the context switch can be performed */
@ -128,7 +128,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Reset scheduler parameters */
@ -152,7 +152,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously

2
arch/arm/src/arm/up_dataabort.c
View File

@ -113,7 +113,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
*/
savestate = (uint32_t*)current_regs;
savestate = (uint32_t *)current_regs;
#endif
current_regs = regs;

2
arch/arm/src/arm/up_doirq.c
View File

@ -109,7 +109,7 @@ void up_doirq(int irq, uint32_t *regs)
#ifdef CONFIG_ARCH_FPU
/* Restore floating point registers */
up_restorefpu((uint32_t*)current_regs);
up_restorefpu((uint32_t *)current_regs);
#endif
#ifdef CONFIG_ARCH_ADDRENV

32
arch/arm/src/arm/up_elf.c
View File

@ -173,10 +173,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = (*(uint32_t*)addr & 0x00ffffff) << 2;
offset = (*(uint32_t *)addr & 0x00ffffff) << 2;
if (offset & 0x02000000)
{
offset -= 0x04000000;
@ -193,8 +193,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset >>= 2;
*(uint32_t*)addr &= 0xff000000;
*(uint32_t*)addr |= offset & 0x00ffffff;
*(uint32_t *)addr &= 0xff000000;
*(uint32_t *)addr |= offset & 0x00ffffff;
}
break;
@ -202,34 +202,34 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t*)addr += sym->st_value;
*(uint32_t *)addr += sym->st_value;
}
break;
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t*)addr));
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
*(uint32_t*)addr &= 0xf000000f;
*(uint32_t *)addr &= 0xf000000f;
/* Change instruction to 'mov pc, Rm' */
*(uint32_t*)addr |= 0x01a0f000;
*(uint32_t *)addr |= 0x01a0f000;
}
break;
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t*)addr + sym->st_value - addr;
*(uint32_t*)addr = offset & 0x7fffffff;
offset = *(uint32_t *)addr + sym->st_value - addr;
*(uint32_t *)addr = offset & 0x7fffffff;
}
break;
@ -237,10 +237,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = *(uint32_t*)addr;
offset = *(uint32_t *)addr;
offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
offset = (offset ^ 0x8000) - 0x8000;
@ -250,8 +250,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset >>= 16;
}
*(uint32_t*)addr &= 0xfff0f000;
*(uint32_t*)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
*(uint32_t *)addr &= 0xfff0f000;
*(uint32_t *)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
}
break;

2
arch/arm/src/arm/up_prefetchabort.c
View File

@ -96,7 +96,7 @@ void up_prefetchabort(uint32_t *regs)
* for register dumps and possibly context switching.
*/
savestate = (uint32_t*)current_regs;
savestate = (uint32_t *)current_regs;
#endif
current_regs = regs;

6
arch/arm/src/arm/up_releasepending.c
View File

@ -65,7 +65,7 @@
void up_release_pending(void)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
slldbg("From TCB=%p\n", rtcb);
@ -96,7 +96,7 @@ void up_release_pending(void)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -121,7 +121,7 @@ void up_release_pending(void)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously

6
arch/arm/src/arm/up_reprioritizertr.c
View File

@ -92,7 +92,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
}
else
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
slldbg("TCB=%p PRI=%d\n", tcb, priority);
@ -150,7 +150,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -174,7 +174,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously

2
arch/arm/src/arm/up_schedulesigaction.c
View File

@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs);
if (tcb == (struct tcb_s*)g_readytorun.head)
if (tcb == (struct tcb_s *)g_readytorun.head)
{
/* CASE 1: We are not in an interrupt handler and
* a task is signalling itself for some reason.

2
arch/arm/src/arm/up_sigdeliver.c
View File

@ -82,7 +82,7 @@
void up_sigdeliver(void)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
uint32_t regs[XCPTCONTEXT_REGS];
sig_deliver_t sigdeliver;

18
arch/arm/src/arm/up_unblocktask.c
View File

@ -71,7 +71,7 @@
void up_unblock_task(struct tcb_s *tcb)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
/* Verify that the context switch can be performed */
@ -110,7 +110,7 @@ void up_unblock_task(struct tcb_s *tcb)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -136,16 +136,16 @@ void up_unblock_task(struct tcb_s *tcb)
* g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
#ifdef CONFIG_ARCH_ADDRENV
/* Make sure that the address environment for the previously
* running task is closed down gracefully (data caches dump,
* MMU flushed) and set up the address environment for the new
* thread at the head of the ready-to-run list.
*/
/* Make sure that the address environment for the previously
* running task is closed down gracefully (data caches dump,
* MMU flushed) and set up the address environment for the new
* thread at the head of the ready-to-run list.
*/
(void)group_addrenv(rtcb);
(void)group_addrenv(rtcb);
#endif
/* Update scheduler parameters */

4
arch/arm/src/arm/up_va2pte.c
View File

@ -101,11 +101,11 @@ uint32_t *up_va2pte(uintptr_t vaddr)
/* Get the L1 table entry associated with this virtual address */
L1 = *(uint32_t*)PG_POOL_VA2L1VADDR(vaddr);
L1 = *(uint32_t *)PG_POOL_VA2L1VADDR(vaddr);
/* Get the address of the L2 page table from the L1 entry */
L2 = (uint32_t*)PG_POOL_L12VPTABLE(L1);
L2 = (uint32_t *)PG_POOL_L12VPTABLE(L1);
/* Get the index into the L2 page table. Each L1 entry maps
* 256 x 4Kb or 1024 x 1Kb pages.

6
arch/arm/src/armv6-m/up_assert.c
View File

@ -240,7 +240,7 @@ static int assert_tracecallback(FAR struct usbtrace_s *trace,FAR void *arg)
#ifdef CONFIG_ARCH_STACKDUMP
static void up_dumpstate(void)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
uint32_t sp = up_getsp();
uint32_t ustackbase;
uint32_t ustacksize;
@ -365,7 +365,7 @@ static void _up_assert(int errorcode)
{
/* Are we in an interrupt handler or the idle task? */
if (current_regs || ((struct tcb_s*)g_readytorun.head)->pid == 0)
if (current_regs || ((struct tcb_s *)g_readytorun.head)->pid == 0)
{
(void)irqsave();
for (;;)
@ -395,7 +395,7 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);

6
arch/arm/src/armv6-m/up_blocktask.c
View File

@ -74,7 +74,7 @@
void up_block_task(struct tcb_s *tcb, tstate_t task_state)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
/* Verify that the context switch can be performed */
@ -126,7 +126,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Reset scheduler parameters */
@ -141,7 +141,7 @@ void up_block_task(struct tcb_s *tcb, tstate_t task_state)
else
{
struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head;
/* Reset scheduler parameters */

4
arch/arm/src/armv6-m/up_doirq.c
View File

@ -90,7 +90,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* current_regs is also used to manage interrupt level context switches.
*/
savestate = (uint32_t*)current_regs;
savestate = (uint32_t *)current_regs;
current_regs = regs;
/* Acknowledge the interrupt */
@ -107,7 +107,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* switch occurred during interrupt processing.
*/
regs = (uint32_t*)current_regs;
regs = (uint32_t *)current_regs;
/* Restore the previous value of current_regs. NULL would indicate that
* we are no longer in an interrupt handler. It will be non-NULL if we

48
arch/arm/src/armv6-m/up_elf.c
View File

@ -169,10 +169,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_JUMP24:
{
bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = (*(uint32_t*)addr & 0x00ffffff) << 2;
offset = (*(uint32_t *)addr & 0x00ffffff) << 2;
if (offset & 0x02000000)
{
offset -= 0x04000000;
@ -189,8 +189,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset >>= 2;
*(uint32_t*)addr &= 0xff000000;
*(uint32_t*)addr |= offset & 0x00ffffff;
*(uint32_t *)addr &= 0xff000000;
*(uint32_t *)addr |= offset & 0x00ffffff;
}
break;
@ -198,9 +198,9 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
{
bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
*(uint32_t*)addr += sym->st_value;
*(uint32_t *)addr += sym->st_value;
}
break;
@ -242,8 +242,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
* J2 = lower_insn[11]
*/
upper_insn = (uint32_t)(*(uint16_t*)addr);
lower_insn = (uint32_t)(*(uint16_t*)(addr + 2));
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
@ -315,10 +315,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
J2 = S ^ (~(offset >> 22) & 1);
upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff));
*(uint16_t*)addr = (uint16_t)upper_insn;
*(uint16_t *)addr = (uint16_t)upper_insn;
lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
*(uint16_t*)(addr + 2) = (uint16_t)lower_insn;
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" S=%d J1=%d J2=%d insn [%04x %04x]\n",
S, J1, J2, (int)upper_insn, (int)lower_insn);
@ -328,25 +328,25 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_V4BX:
{
bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
(long)addr, (long)(*(uint32_t*)addr));
(long)addr, (long)(*(uint32_t *)addr));
/* Preserve only Rm and the condition code */
*(uint32_t*)addr &= 0xf000000f;
*(uint32_t *)addr &= 0xf000000f;
/* Change instruction to 'mov pc, Rm' */
*(uint32_t*)addr |= 0x01a0f000;
*(uint32_t *)addr |= 0x01a0f000;
}
break;
case R_ARM_PREL31:
{
bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
(long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
(long)addr, (long)(*(uint32_t *)addr), sym, (long)sym->st_value);
offset = *(uint32_t*)addr + sym->st_value - addr;
*(uint32_t*)addr = offset & 0x7fffffff;
offset = *(uint32_t *)addr + sym->st_value - addr;
*(uint32_t *)addr = offset & 0x7fffffff;
}
break;
@ -354,10 +354,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
case R_ARM_MOVT_ABS:
{
bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t *)addr),
sym, (long)sym->st_value);
offset = *(uint32_t*)addr;
offset = *(uint32_t *)addr;
offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
offset = (offset ^ 0x8000) - 0x8000;
@ -367,8 +367,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
offset >>= 16;
}
*(uint32_t*)addr &= 0xfff0f000;
*(uint32_t*)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
*(uint32_t *)addr &= 0xfff0f000;
*(uint32_t *)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
}
break;
@ -405,8 +405,8 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
* imm8 = imm16[0:7] = lower_insn[7:0]
*/
upper_insn = (uint32_t)(*(uint16_t*)addr);
lower_insn = (uint32_t)(*(uint16_t*)(addr + 2));
upper_insn = (uint32_t)(*(uint16_t *)addr);
lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
@ -440,10 +440,10 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
}
upper_insn = ((upper_insn & 0xfbf0) | ((offset & 0xf000) >> 12) | ((offset & 0x0800) >> 1));
*(uint16_t*)addr = (uint16_t)upper_insn;
*(uint16_t *)addr = (uint16_t)upper_insn;
lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff));
*(uint16_t*)(addr + 2) = (uint16_t)lower_insn;
*(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
bvdbg(" insn [%04x %04x]\n",
(int)upper_insn, (int)lower_insn);

4
arch/arm/src/armv6-m/up_hardfault.c
View File

@ -89,11 +89,11 @@
int up_hardfault(int irq, FAR void *context)
{
uint32_t *regs = (uint32_t*)context;
uint32_t *regs = (uint32_t *)context;
/* Get the value of the program counter where the fault occurred */
uint16_t *pc = (uint16_t*)regs[REG_PC] - 1;
uint16_t *pc = (uint16_t *)regs[REG_PC] - 1;
/* Check if the pc lies in known FLASH memory.
* REVISIT: What if the PC lies in "unknown" external memory?

6
arch/arm/src/armv6-m/up_releasepending.c
View File

@ -64,7 +64,7 @@
void up_release_pending(void)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
slldbg("From TCB=%p\n", rtcb);
@ -95,7 +95,7 @@ void up_release_pending(void)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -110,7 +110,7 @@ void up_release_pending(void)
else
{
struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */

6
arch/arm/src/armv6-m/up_reprioritizertr.c
View File

@ -91,7 +91,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
}
else
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
bool switch_needed;
slldbg("TCB=%p PRI=%d\n", tcb, priority);
@ -150,7 +150,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -165,7 +165,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
else
{
struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */

2
arch/arm/src/armv6-m/up_schedulesigaction.c
View File

@ -122,7 +122,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
sdbg("rtcb=0x%p current_regs=0x%p\n", g_readytorun.head, current_regs);
if (tcb == (struct tcb_s*)g_readytorun.head)
if (tcb == (struct tcb_s *)g_readytorun.head)
{
/* CASE 1: We are not in an interrupt handler and a task is
* signalling itself for some reason.

2
arch/arm/src/armv6-m/up_sigdeliver.c
View File

@ -87,7 +87,7 @@ void up_sigdeliver(void)
* copy an may overwrite the regs[] array contents. Sorry.
*/
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
uint32_t regs[XCPTCONTEXT_REGS + 4];
sig_deliver_t sigdeliver;

12
arch/arm/src/armv6-m/up_svcall.c
View File

@ -159,7 +159,7 @@ static void dispatch_syscall(void)
int up_svcall(int irq, FAR void *context)
{
uint32_t *regs = (uint32_t*)context;
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
DEBUGASSERT(regs && regs == current_regs);
@ -211,7 +211,7 @@ int up_svcall(int irq, FAR void *context)
case SYS_save_context:
{
DEBUGASSERT(regs[REG_R1] != 0);
memcpy((uint32_t*)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
}
break;
@ -233,7 +233,7 @@ int up_svcall(int irq, FAR void *context)
case SYS_restore_context:
{
DEBUGASSERT(regs[REG_R1] != 0);
current_regs = (uint32_t*)regs[REG_R1];
current_regs = (uint32_t *)regs[REG_R1];
}
break;
@ -256,8 +256,8 @@ int up_svcall(int irq, FAR void *context)
case SYS_switch_context:
{
DEBUGASSERT(regs[REG_R1] != 0 && regs[REG_R2] != 0);
memcpy((uint32_t*)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
current_regs = (uint32_t*)regs[REG_R2];
memcpy((uint32_t *)regs[REG_R1], regs, XCPTCONTEXT_SIZE);
current_regs = (uint32_t *)regs[REG_R2];
}
break;
@ -407,7 +407,7 @@ int up_svcall(int irq, FAR void *context)
* parameter will reside at an offset of 4 from the stack pointer.
*/
regs[REG_R3] = *(uint32_t*)(regs[REG_SP]+4);
regs[REG_R3] = *(uint32_t *)(regs[REG_SP]+4);
}
break;
#endif

6
arch/arm/src/armv6-m/up_unblocktask.c
View File

@ -69,7 +69,7 @@
void up_unblock_task(struct tcb_s *tcb)
{
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
/* Verify that the context switch can be performed */
@ -108,7 +108,7 @@ void up_unblock_task(struct tcb_s *tcb)
* of the g_readytorun task list.
*/
rtcb = (struct tcb_s*)g_readytorun.head;
rtcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */
@ -123,7 +123,7 @@ void up_unblock_task(struct tcb_s *tcb)
else
{
struct tcb_s *nexttcb = (struct tcb_s*)g_readytorun.head;
struct tcb_s *nexttcb = (struct tcb_s *)g_readytorun.head;
/* Update scheduler parameters */