stm32wl5: add EXTI support for GPIO
This patch implements working support for EXTI GPIO. Signed-off-by: Michał Łyszczek <michal.lyszczek@bofc.pl> -- v1 -> v2: Suggested by: Petro Karashchenko - change (1 << n) to (1 << (n)) in macro definition - change 1 << X to (1 << X) in code - fix alignment v2 -> v3: Suggested by: Petro Karashchenko - I was supposed to change (1 << pin) to 1 << pin, not the other way around:)
This commit is contained in:
Michał Łyszczek
Xiang Xiao
parent
cb8c992914
commit
288b57d5ca
@ -30,14 +30,14 @@ Peripheral Support Notes
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========== ======= =====
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IRQs Yes
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GPIO Yes
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EXTI No
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EXTI Yes
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HSE Yes
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PLL Yes Tested @ 48MHz
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HSI Yes Not tested
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MSI Yes Not tested
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LSE Yes Not tested
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RCC Yes All registers defined, not all peripherals enabled
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SYSCFG Yes All registers defined, remapping not tested
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SYSCFG Yes All registers defined, GPIO EXTI works, remapping not tested
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USART Yes
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LPUART Yes full speed with HSE works, low power mode with LSE not implemented
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DMA No
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@ -102,7 +102,7 @@ SYSCFG
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------
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System configuration controller. Can be used to remap memory or
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manage external interrupts.
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manage GPIO multiplexer for EXTI.
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GPIO
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----
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@ -123,6 +123,16 @@ IPCC
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Inter-processor communication controller. IPCC is used to exchange data
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between Cortex-M4 and Cortex-M0 CPUs.
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EXTI
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----
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Extended interrupts and event controller. Extends interrupts not provided
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by NVIC. For example, there is only one interrupt for GPIO5..9 in NVIC,
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but thanks to EXTI we can differentiate which GPIO caused interrupt. Such
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interrupt first goes through EXTI and is then forwarded to main NVIC.
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EXTI for gpio can be enabled via `stm32wl5_gpiosetevent` function.
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Supported Boards
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================
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@ -32,43 +32,48 @@
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* Pre-processor Definitions
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****************************************************************************/
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#define STM32WL5_NEXTI1 31
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#define STM32WL5_EXTI1_MASK 0xffffffff
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#define STM32WL5_NEXTI2 9
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#define STM32WL5_EXTI2_MASK 0x000001ff
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/* Register Offsets *********************************************************/
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#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising Trigger Selection 1 */
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#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling Trigger Selection 1 */
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#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software Interrupt Event 1 */
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#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */
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#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising Trigger Selection 2 */
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#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling Trigger Selection 2 */
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#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software Interrupt Event 2 */
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#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */
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#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* CPU Wakeup with Interrupt Mask 1 for cpu1 */
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#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* CPU Wakeup with Event Mask 1 for cpu1 */
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#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* CPU Wakeup with Interrupt Mask 2 for cpu1 */
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#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* CPU Wakeup with Event Mask 2 for cpu1 */
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#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* CPU Wakeup with Interrupt Mask 1 for cpu2 */
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#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* CPU Wakeup with Event Mask 1 for cpu2 */
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#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* CPU Wakeup with Interrupt Mask 2 for cpu2 */
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#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* CPU Wakeup with Event Mask 2 for cpu2 */
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#define STM32WL5_EXTI_RTSR1_OFFSET 0x0000 /* Rising trigger selection 1 */
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#define STM32WL5_EXTI_FTSR1_OFFSET 0x0004 /* Falling trigger selection 1 */
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#define STM32WL5_EXTI_SWIER1_OFFSET 0x0008 /* Software interrupt event 1 */
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#define STM32WL5_EXTI_PR1_OFFSET 0x000c /* Pending 1 */
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#define STM32WL5_EXTI_RTSR2_OFFSET 0x0020 /* Rising trigger selection 2 */
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#define STM32WL5_EXTI_FTSR2_OFFSET 0x0024 /* Falling trigger selection 2 */
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#define STM32WL5_EXTI_SWIER2_OFFSET 0x0028 /* Software interrupt event 2 */
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#define STM32WL5_EXTI_PR2_OFFSET 0x002c /* Pending 2 */
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#define STM32WL5_EXTI_C1IMR1_OFFSET 0x0080 /* Interrupt mask 1 for cpu1 */
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#define STM32WL5_EXTI_C1EMR1_OFFSET 0x0084 /* Event mask 1 for cpu1 */
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#define STM32WL5_EXTI_C1IMR2_OFFSET 0x0090 /* Interrupt mask 2 for cpu1 */
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#define STM32WL5_EXTI_C1EMR2_OFFSET 0x0094 /* Event mask 2 for cpu1 */
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#define STM32WL5_EXTI_C2IMR1_OFFSET 0x00c0 /* Interrupt mask 1 for cpu2 */
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#define STM32WL5_EXTI_C2EMR1_OFFSET 0x00c4 /* Event mask 1 for cpu2 */
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#define STM32WL5_EXTI_C2IMR2_OFFSET 0x00d0 /* Interrupt mask 2 for cpu2 */
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#define STM32WL5_EXTI_C2EMR2_OFFSET 0x00d4 /* Event mask 2 for cpu2 */
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/* Register Addresses *******************************************************/
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#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET)
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#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET)
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#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET)
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#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET)
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#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET)
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#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET)
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#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET)
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#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET)
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#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET)
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#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET)
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#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET)
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#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET)
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#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET)
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#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET)
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#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET)
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#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET)
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#define STM32WL5_EXTI_RTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR1_OFFSET)
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#define STM32WL5_EXTI_FTSR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR1_OFFSET)
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#define STM32WL5_EXTI_SWIER1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER1_OFFSET)
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#define STM32WL5_EXTI_PR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR1_OFFSET)
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#define STM32WL5_EXTI_RTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_RTSR2_OFFSET)
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#define STM32WL5_EXTI_FTSR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_FTSR2_OFFSET)
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#define STM32WL5_EXTI_SWIER2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_SWIER2_OFFSET)
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#define STM32WL5_EXTI_PR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_PR2_OFFSET)
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#define STM32WL5_EXTI_C1IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR1_OFFSET)
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#define STM32WL5_EXTI_C1EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR1_OFFSET)
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#define STM32WL5_EXTI_C1IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1IMR2_OFFSET)
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#define STM32WL5_EXTI_C1EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C1EMR2_OFFSET)
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#define STM32WL5_EXTI_C2IMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR1_OFFSET)
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#define STM32WL5_EXTI_C2EMR1 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR1_OFFSET)
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#define STM32WL5_EXTI_C2IMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2IMR2_OFFSET)
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#define STM32WL5_EXTI_C2EMR2 (STM32WL5_EXTI_BASE+STM32WL5_EXTI_C2EMR2_OFFSET)
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/* Register Bitfield Definitions ********************************************/
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@ -103,4 +108,84 @@
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#define EXTI2_RADIOBSY (1 << 14) /* EXTI line 45: Radio busy wakeup */
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#define EXTI2_CDBGPWRUPREQ (1 << 15) /* EXTI line 46: Debug power-up request wakup */
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/* Rising Trigger selection register */
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#define EXTI_RTSR1_BIT(n) (1 << (n)) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_RTSR1_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
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#define EXTI_RTSR1_MASK (0x0061ffff)
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#define EXTI_RTSR2_BIT(n) (1 << (n)) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_RTSR2_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
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#define EXTI_RTSR2_MASK (0x00002304)
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/* Falling Trigger selection register */
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#define EXTI_FTSR1_BIT(n) (1 << (n)) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_FTSR1_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
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#define EXTI_FTSR1_MASK (0x0061ffff)
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#define EXTI_FTSR2_BIT(n) (1 << (n)) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
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#define EXTI_FTSR2_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
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#define EXTI_FTSR2_MASK (0x00002304)
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/* Software interrupt event register */
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#define EXTI_SWIER1_BIT(n) (1 << (n)) /* 1=Sets the corresponding pending bit in EXTI_PR */
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#define EXTI_SWIER1_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
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#define EXTI_SWIER1_MASK (0x0061ffff)
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#define EXTI_SWIER2_BIT(n) (1 << (n)) /* 1=Sets the corresponding pending bit in EXTI_PR */
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#define EXTI_SWIER2_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
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#define EXTI_SWIER2_MASK (0x00002304)
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/* Pending register */
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#define EXTI_PR1_BIT(n) (1 << (n)) /* 1=Selected trigger request occurred */
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#define EXTI_PR1_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR1_MASK (0x0061ffff)
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#define EXTI_PR2_BIT(n) (1 << (n)) /* 1=Selected trigger request occurred */
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#define EXTI_PR2_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
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#define EXTI_PR2_MASK (0x00002304)
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/* Interrupt mask register */
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#define EXTI_C1IMR1_BIT(n) (1 << (n)) /* 1=Interrupt request from line x is not masked */
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#define EXTI_C1IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_C1IMR1_MASK (0xffffffff)
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#define EXTI_C1IMR2_BIT(n) (1 << (n)) /* 1=Interrupt request from line x is not masked */
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#define EXTI_C1IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_C1IMR2_MASK (0x007effff)
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/* Event mask register */
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#define EXTI_C1EMR1_BIT(n) (1 << (n)) /* 1=Event request from line x is not mask */
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#define EXTI_C1EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_C1EMR1_MASK (0x00007ff4)
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#define EXTI_C1EMR2_BIT(n) (1 << (n)) /* 1=Event request from line x is not mask */
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#define EXTI_C1EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_C1EMR2_MASK (0x00000300)
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/* Interrupt mask register */
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#define EXTI_C2IMR1_BIT(n) (1 << (n)) /* 1=Interrupt request from line x is not masked */
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#define EXTI_C2IMR1_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_C2IMR1_MASK (0xffffffff)
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#define EXTI_C2IMR2_BIT(n) (1 << (n)) /* 1=Interrupt request from line x is not masked */
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#define EXTI_C2IMR2_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
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#define EXTI_C2IMR2_MASK (0x007effff)
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/* Event mask register */
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#define EXTI_C2EMR1_BIT(n) (1 << (n)) /* 1=Event request from line x is not mask */
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#define EXTI_C2EMR1_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_C2EMR1_MASK (0x00007ff4)
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#define EXTI_C2EMR2_BIT(n) (1 << (n)) /* 1=Event request from line x is not mask */
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#define EXTI_C2EMR2_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
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#define EXTI_C2EMR2_MASK (0x00000300)
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#endif /* __ARCH_ARM_SRC_STM32WL5_HARDWARE_STM32WL5_EXTI_H */
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@ -28,7 +28,6 @@
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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@ -62,28 +61,23 @@ static struct gpio_callback_s g_gpio_handlers[16];
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****************************************************************************/
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/****************************************************************************
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* Interrupt Service Routine - Dispatcher
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* Interrupt Service Routines - Dispatchers
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****************************************************************************/
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static int stm32wl5_exti0_15_isr(int irq, void *context, FAR void *arg)
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static int stm32wl5_exti0_isr(int irq, void *context, void *arg)
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{
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int ret = OK;
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int exti;
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(void)arg;
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exti = irq - STM32WL5_IRQ_EXTI0;
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DEBUGASSERT((exti >= 0) && (exti <= 15));
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/* Clear the pending interrupt */
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/* Clear the pending interrupt for both rising and falling edges. */
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putreg32(0x0001 << exti, STM32WL5_EXTI_PR1);
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putreg32(0x0001, STM32WL5_EXTI_PR1);
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/* And dispatch the interrupt to the handler */
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if (g_gpio_handlers[exti].callback != NULL)
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if (g_gpio_handlers[0].callback != NULL)
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{
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xcpt_t callback = g_gpio_handlers[exti].callback;
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void *cbarg = g_gpio_handlers[exti].arg;
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xcpt_t callback = g_gpio_handlers[0].callback;
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void *cbarg = g_gpio_handlers[0].arg;
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ret = callback(irq, context, cbarg);
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}
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@ -91,6 +85,144 @@ static int stm32wl5_exti0_15_isr(int irq, void *context, FAR void *arg)
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return ret;
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}
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static int stm32wl5_exti1_isr(int irq, void *context, void *arg)
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{
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int ret = OK;
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/* Clear the pending interrupt */
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putreg32(0x0002, STM32WL5_EXTI_PR1);
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/* And dispatch the interrupt to the handler */
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if (g_gpio_handlers[1].callback != NULL)
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{
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xcpt_t callback = g_gpio_handlers[1].callback;
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void *cbarg = g_gpio_handlers[1].arg;
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ret = callback(irq, context, cbarg);
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}
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return ret;
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}
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static int stm32wl5_exti2_isr(int irq, void *context, void *arg)
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{
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int ret = OK;
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/* Clear the pending interrupt */
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putreg32(0x0004, STM32WL5_EXTI_PR1);
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/* And dispatch the interrupt to the handler */
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if (g_gpio_handlers[2].callback != NULL)
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{
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xcpt_t callback = g_gpio_handlers[2].callback;
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void *cbarg = g_gpio_handlers[2].arg;
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ret = callback(irq, context, cbarg);
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}
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return ret;
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}
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static int stm32wl5_exti3_isr(int irq, void *context, void *arg)
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{
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int ret = OK;
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/* Clear the pending interrupt */
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putreg32(0x0008, STM32WL5_EXTI_PR1);
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/* And dispatch the interrupt to the handler */
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if (g_gpio_handlers[3].callback != NULL)
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{
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xcpt_t callback = g_gpio_handlers[3].callback;
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void *cbarg = g_gpio_handlers[3].arg;
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ret = callback(irq, context, cbarg);
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}
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return ret;
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}
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static int stm32wl5_exti4_isr(int irq, void *context, void *arg)
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{
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int ret = OK;
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/* Clear the pending interrupt */
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putreg32(0x0010, STM32WL5_EXTI_PR1);
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/* And dispatch the interrupt to the handler */
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if (g_gpio_handlers[4].callback != NULL)
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{
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xcpt_t callback = g_gpio_handlers[4].callback;
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void *cbarg = g_gpio_handlers[4].arg;
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ret = callback(irq, context, cbarg);
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}
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return ret;
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}
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static int stm32wl5_exti_multiisr(int irq, void *context, void *arg,
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int first, int last)
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{
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uint32_t pr;
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int pin;
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int ret = OK;
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/* Examine the state of each pin in the group */
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pr = getreg32(STM32WL5_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
for (pin = first; pin <= last; pin++)
|
||||
{
|
||||
/* Is an interrupt pending on this pin? */
|
||||
|
||||
uint32_t mask = 1 << pin;
|
||||
if ((pr & mask) != 0)
|
||||
{
|
||||
/* Clear the pending interrupt */
|
||||
|
||||
putreg32(mask, STM32WL5_EXTI_PR1);
|
||||
|
||||
/* And dispatch the interrupt to the handler */
|
||||
|
||||
if (g_gpio_handlers[pin].callback != NULL)
|
||||
{
|
||||
xcpt_t callback = g_gpio_handlers[pin].callback;
|
||||
void *cbarg = g_gpio_handlers[pin].arg;
|
||||
int tmp;
|
||||
|
||||
tmp = callback(irq, context, cbarg);
|
||||
if (tmp < 0)
|
||||
{
|
||||
ret = tmp;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32wl5_exti95_isr(int irq, void *context, void *arg)
|
||||
{
|
||||
return stm32wl5_exti_multiisr(irq, context, arg, 5, 9);
|
||||
}
|
||||
|
||||
static int stm32wl5_exti1510_isr(int irq, void *context, void *arg)
|
||||
{
|
||||
return stm32wl5_exti_multiisr(irq, context, arg, 10, 15);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -121,9 +253,60 @@ static int stm32wl5_exti0_15_isr(int irq, void *context, FAR void *arg)
|
||||
int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
bool event, xcpt_t func, void *arg)
|
||||
{
|
||||
struct gpio_callback_s *shared_cbs;
|
||||
uint32_t pin = pinset & GPIO_PIN_MASK;
|
||||
uint32_t exti = 1 << pin;
|
||||
int irq = STM32WL5_IRQ_EXTI0 + pin;
|
||||
int irq;
|
||||
xcpt_t handler;
|
||||
int nshared;
|
||||
int i;
|
||||
|
||||
/* Select the interrupt handler for this EXTI pin */
|
||||
|
||||
if (pin < 5)
|
||||
{
|
||||
irq = pin + STM32WL5_IRQ_EXTI0;
|
||||
nshared = 1;
|
||||
shared_cbs = &g_gpio_handlers[pin];
|
||||
switch (pin)
|
||||
{
|
||||
case 0:
|
||||
handler = stm32wl5_exti0_isr;
|
||||
break;
|
||||
|
||||
case 1:
|
||||
handler = stm32wl5_exti1_isr;
|
||||
break;
|
||||
|
||||
case 2:
|
||||
handler = stm32wl5_exti2_isr;
|
||||
break;
|
||||
|
||||
case 3:
|
||||
handler = stm32wl5_exti3_isr;
|
||||
break;
|
||||
|
||||
default:
|
||||
handler = stm32wl5_exti4_isr;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else if (pin < 10)
|
||||
{
|
||||
irq = STM32WL5_IRQ_EXTI95;
|
||||
handler = stm32wl5_exti95_isr;
|
||||
shared_cbs = &g_gpio_handlers[5];
|
||||
nshared = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
irq = STM32WL5_IRQ_EXTI1510;
|
||||
handler = stm32wl5_exti1510_isr;
|
||||
shared_cbs = &g_gpio_handlers[10];
|
||||
nshared = 6;
|
||||
}
|
||||
|
||||
/* Get the previous GPIO IRQ handler; Save the new IRQ handler. */
|
||||
|
||||
g_gpio_handlers[pin].callback = func;
|
||||
g_gpio_handlers[pin].arg = arg;
|
||||
@ -132,12 +315,27 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
|
||||
if (func)
|
||||
{
|
||||
irq_attach(irq, stm32wl5_exti0_15_isr, NULL);
|
||||
irq_attach(irq, handler, NULL);
|
||||
up_enable_irq(irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
up_disable_irq(irq);
|
||||
/* Only disable IRQ if shared handler does not have any active
|
||||
* callbacks.
|
||||
*/
|
||||
|
||||
for (i = 0; i < nshared; i++)
|
||||
{
|
||||
if (shared_cbs[i].callback != NULL)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (i == nshared)
|
||||
{
|
||||
up_disable_irq(irq);
|
||||
}
|
||||
}
|
||||
|
||||
/* Configure GPIO, enable EXTI line enabled if event or interrupt is
|
||||
@ -169,5 +367,7 @@ int stm32wl5_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
|
||||
func ? 0 : exti,
|
||||
func ? exti : 0);
|
||||
|
||||
/* Return the old IRQ handler */
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
@ -279,6 +279,30 @@ int stm32wl5_configgpio(uint32_t cfgset)
|
||||
|
||||
putreg32(regval, base + STM32WL5_GPIO_OTYPER_OFFSET);
|
||||
|
||||
/* Otherwise, it is an input pin. Should it configured as an
|
||||
* EXTI interrupt?
|
||||
*/
|
||||
|
||||
if (pinmode != GPIO_MODER_OUTPUT && (cfgset & GPIO_EXTI) != 0)
|
||||
{
|
||||
/* The selection of the EXTI line source is performed through the EXTIx
|
||||
* bits in the SYSCFG_EXTICRx registers.
|
||||
*/
|
||||
|
||||
uint32_t regaddr;
|
||||
int shift;
|
||||
|
||||
/* Set the bits in the SYSCFG EXTICR register */
|
||||
|
||||
regaddr = STM32WL5_SYSCFG_EXTICR(pin);
|
||||
regval = getreg32(regaddr);
|
||||
shift = SYSCFG_EXTICR_EXTI_SHIFT(pin);
|
||||
regval &= ~(SYSCFG_EXTICR_PORT_MASK << shift);
|
||||
regval |= (((uint32_t)port) << shift);
|
||||
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user